Altera Stratix V GX Edition Reference Manual
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Altera Stratix V GX Edition Reference Manual

Transceiver signal integrity development kit
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Transceiver Signal Integrity Development Kit Stratix V GX
Edition Reference Manual
Transceiver Signal Integrity Development Kit,
101 Innovation Drive
San Jose, CA 95134
www.altera.com
MNL-01064-1.0
Stratix V GX Edition Reference Manual
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  • Page 1 Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual Transceiver Signal Integrity Development Kit, Stratix V GX Edition Reference Manual 101 Innovation Drive San Jose, CA 95134 www.altera.com MNL-01064-1.0 Subscribe...
  • Page 2 © 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at www.altera.com/common/legal.html.

  • Page 3: Table Of Contents

    Statement of China-RoHS Compliance ........... . 2–40 September 2011 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual...
  • Page 4 Typographic Conventions ..............1–1 Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual...

  • Page 5: Chapter 1. Overview

    FPGA designs that interface with all components of the board. General Description The Transceiver Signal Integrity Development Kit, Stratix V GX Edition, allows you to evaluate the performance the Stratix V GX FPGA which is optimized for high-performance and high-bandwidth applications with integrated transceivers supporting backplane, chip-to-chip, and chip-to-module operation.
  • Page 6 General User I/O 8 user LEDs ■ Three configuration status LEDs (factory, user, error)Six Ethernet LEDs ■ One 16-character × 2-line character LCD display ■ Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual September 2011 Altera Corporation...
  • Page 7 ■ Power monitor and trim capability ■ Power sequence capability ■ ■ System Monitoring Temperature—FPGA die ■ Mechanical ■ 7.5" x 10.5" board dimension ■ September 2011 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual...

  • Page 8: Development Board Block Diagram

    The Stratix V GX transceiver signal integrity development board must be stored between –40º C and 100º C. The recommended operating temperature is between 0º C and 55º C. Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual September 2011 Altera Corporation...

  • Page 9: Introduction

    “Components and Interfaces” on page 2–31 ■ “Flash Memory” on page 2–35 ■ ■ “Power Supply” on page 2–37 ■ “Statement of China-RoHS Compliance” on page 2–40 September 2011 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual...

  • Page 10: Board Overview

    Enables or disables the MAX II CPLD in the JTAG chain. The MAX II S7 (pin 6-7) MAX II bypass switch CPLD is disabled by default. Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual September 2011 Altera Corporation...
  • Page 11 Spread spectrum selection Select either the core or spread spectrum clock. Pin 1-2 selects S0 and switch S1 while pin 3-4 selects SS0 and SS1. September 2011 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual...
  • Page 12 Four user push buttons. Driven low when pressed . A single 14-pin 0.1" pitch dual-row header which interfaces to the 16 Character LCD header character × 2 line LCD module. Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual September 2011 Altera Corporation...
  • Page 13 Ground banana jack Banana jack connected to ground. U10 and U11 Power monitor devices Linear Technology LTC2978, octal PMBus power supply monitor and controller. September 2011 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual...

  • Page 14: Featured Device: Stratix V Gx

    LVDS input 4 pairs Differential REFCLK input for one SMA pair per clock buffer. FPGA Global Clocks 50-MHz clock 2.5-V CMOS input Global clock input. Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual September 2011 Altera Corporation...
  • Page 15 Flash write protect Reset ® CPU_RESETn 2.5-V CMOS input Nios II CPU reset Switches, Buttons, LEDS User push buttons 2.5-V CMOS input 4 user push buttons September 2011 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual...
  • Page 16 Transceiver channel 12.5G channels to XFP cage 1.4-V PCML Transceiver channel Spares Spare[7:0] 2.5-V CMOS Spare signals to the MAX II CPLD Device I/O Total: Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual September 2011 Altera Corporation...

  • Page 17: Max Ii Cpld System Controller

    Chapter 2: Board Components 2–9 MAX II CPLD System Controller MAX II CPLD System Controller The board utilizes the EPM2210F256C3N System Controller, an Altera MAX II CPLD, for the following purposes: ■ FPGA configuration from flash memory ■ Temperature monitoring ■...
  • Page 18 F_AD20 AK12 2.5-V Flash address bus F_AD21 AK11 2.5-V Flash address bus F_AD22 AL12 2.5-V Flash address bus F_AD23 AL11 2.5-V Flash address bus F_AD24 Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual September 2011 Altera Corporation...
  • Page 19 FPP programming data out MAX_FPP_TDO AN15 2.5-V Flash bus MAX II byte enable 0 MAXLL_BEN0 AN14 2.5-V Flash bus MAX II byte enable 1 MAXLL_BEN1 September 2011 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual...
  • Page 20 2.5-V FPGA partial reconfiguration request PR_REQUEST Power good signal to indicate that all voltage rails — — PWR_GOOD have come up to their proper levels. Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual September 2011 Altera Corporation...
  • Page 21 Table 2–6. MAX II CPLD EPM2210 System Controller Component Reference and Manufacturing Information Manufacturing Manufacturer Board Reference Description Manufacturer Part Number Website MAX II CPLD 256FBGA -3 LF Altera Corporation EPM2210F256C3N www.altera.com 3.3 V VCCINT September 2011 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual...

  • Page 22: Configuration, Status, And Setup Elements

    FPGA Programming over Embedded USB-Blaster Programming the FPGA over embedded USB-Blaster is implemented using a type-B USB connector (CN1), a USB 2.0 PHY device, and an Altera MAX II CPLD EPM2210F256C3N (U19). This allows configuration of the FPGA using a USB cable directly connected between the USB port on the board (CN1) and a USB port of a PC running the Quartus II software.

  • Page 23: Fpga Programming From Flash Memory

    (FPP) format. This 8-bit data is then written to the FPGA’s dedicated configuration pins during configuration. The FPP configuration is implemented with an Altera MAX II CPLD together with the Micron PC2800AP30BF 1-Gbit CFI NOR-type flash device (U21). The CPLD shares the flash interface with the FPGA.

  • Page 24: Fpga Programming Over External Usb-Blaster

    The PFL megafunction is a block of logic that is programmed into an Altera programmable logic device (FPGA or CPLD). The PFL functions as a utility for writing to a compatible flash device. This pre-built design contains the PFL megafunction that allows you to write either page 0, page 1, or other areas of flash over the USB interface using the Quartus II software.

  • Page 25: Jtag Header

    2–17 Configuration, Status, and Setup Elements JTAG Header The JTAG header provides another method for configuring the FPGA using an Altera USB-Blaster dongle with the Quartus II Programmer running on a PC. Figure 2–5 shows the schematic connections for the dedicated JTAG programming header (J93).
  • Page 26 D8, D10-D17 Green LEDs Lumex Inc. SML-LX1206GC-TR www.lumex.com Red LED Lumex Inc. SML-LX1206IC-TR www.lumex.com Blue LED Lumex Inc. SML-LX1206USBC-TR www.lumex.com Amber LED Lite-On LTST-C150KYKT www.lite-on.com Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual September 2011 Altera Corporation...

  • Page 27: Setup Elements

    Controller configures the FPGA to either factory or user image. For information on the jumper settings, refer to “FPGA Programming from Flash Memory” on page 2–15. September 2011 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual...

  • Page 28: Reset Push Button

    Each oscillator supports a programmable frequency range of 10 MHz–1.4 GHz and provide a trigger output to an SMA connector for scope or other lab equipment triggering purposes. Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual September 2011 Altera Corporation...

  • Page 29: General-Purpose Clocks

    The available frequencies and down spread percentages available from the spread spectrum buffer is shown in Table 2–15. ■ An external differential clock source from SMA at CLK10p/n (J70/J71). September 2011 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual...

  • Page 30: Embedded Usb-Blaster Clocks

    Part Number Crystal oscillator, 6.0 MHz, SMD ESC Inc. ECSX-60-32-5P-TR www.ecsxtal.com Crystal oscillator, CMOS, 2.5 V, SG-310SDF 24.0000M- www.epsontoyocom.co.jp/ Epson 24.000 MHz, SMT, ±50ppm english/index.html Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual September 2011 Altera Corporation...

  • Page 31: Transceiver Channels

    2-12.5-Gbps RX to Tyco backplane connector (right side of transceiver block) Length matched between this RX pair 5-12.5-Gbps TX to Amphenol/FCI backplane connector (left side of transceiver Length matched between this TX group block) September 2011 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual...

  • Page 32: Backplane Connectors

    1.4-V PCML GXB transmit GXB_TXLN_22 1.4-V PCML GXB transmit GXB_TXLP_22 1.4-V PCML GXB transmit GXB_TXLN_23 1.4-V PCML GXB transmit GXB_TXLP_23 1.4-V PCML GXB transmit GXB_TXRN_18 Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual September 2011 Altera Corporation...
  • Page 33 1.4-V PCML GXB transmit GXB_TXRN_0 1.4-V PCML GXB transmit GXB_TXRN_5 1.4-V PCML GXB transmit GXB_TXRP_0 1.4-V PCML GXB transmit GXB_TXRP_5 1.4-V PCML AV39 GXB receive GXBRXLN_0 September 2011 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual...
  • Page 34 GXBRXLN_6 1.4-V PCML AE37 GXB receive GXBRXLN_7 1.4-V PCML AF39 GXB receive GXBRXLN_8 1.4-V PCML AD39 GXB receive GXBRXLN_9 1.4-V PCML AB39 GXB receive GXBRXLN_10 Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual September 2011 Altera Corporation...

  • Page 35: General User Input/Output

    0; when the push button is released, the device pin is set to logic 1. There is no board-specific function for these general user push buttons. September 2011 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual...

  • Page 36: User-Defined Dip Switch

    1 is selected. When the 2.5-V USER_DIP3 switch is in the CLOSED or OFF position, a logic 0 is 2.5-V USER_DIP2 selected. 2.5-V USER_DIP1 2.5-V USER_DIP0 Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual September 2011 Altera Corporation...

  • Page 37: User-Defined Leds

    14-pin header, so it can be easily removed for access to components under the display. You can also use the header for debugging or other purposes. September 2011 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual...
  • Page 38 H: Data read (module to MPU) L: Data write (MPU to module) H, H to L Enable 7–14 DB0–DB7 Data bus, software selectable 4-bit or 8-bit mode Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual September 2011 Altera Corporation...

  • Page 39: Components And Interfaces

    Figure 2–9. SGMII Interface between FPGA (MAC) and Marvell 88E1111 PHY ± S_OUT CAT 5 UTP: - 10BASE-T 88E1111 RJ45 ± Transformer S_IN - 100BASE-TX Device - 1000BASE-T SGMII Interface September 2011 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual...
  • Page 40 TXD0 2.5-V AL17 SGMII transmit data TXD1 2.5-V AJ16 SGMII transmit data TXD2 2.5-V AJ17 SGMII transmit data TXD3 2.5-V AF16 SGMII transmit enable TXEN Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual September 2011 Altera Corporation...

  • Page 41: Transceiver Interfaces

    Part Number Website Amphenol XFP 30-pin connector, 30UM 1367500-1 gold plating, high speed Tyco www.amphenol.com Amphenol www.te.com XFP cage without light pipe, 1489951-1 press fit Tyco September 2011 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual...

  • Page 42: Sfp+ Interface

    Board Reference Description Manufacturer Part Number Website SFP+ connector - Mect family standard SFP right-angle Samtec MECT-110-01-M-D-RA1 www.samtec.com 20-pin SMT SFP+ cage Molex 74754-0101 www.molex.com Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual September 2011 Altera Corporation...

  • Page 43: Flash Memory

    F_AD22 1.8-V AL12 Address bus F_AD23 1.8-V AL11 Address bus F_AD24 1.8-V AM13 Address bus F_AD25 1.8-V AL13 Address bus F_AD26 1.8-V Address valid F_ADVN September 2011 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual...
  • Page 44 Table 2–38. Flash Memory Component Reference and Manufacturing Information Manufacturing Manufacturer Board Reference Description Manufacturer Part Number Website 1-Gbit synchronous flash Micron PC28F00AP30BF www.micron.com Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual September 2011 Altera Corporation...

  • Page 45: Power Supply

    XFP_1p8V MAX II (for USB-Blaster) Core or I/O 2p5V EEPROM — USBVCC Core USBVCC USB PHY 2p5V_USB Power monitor — Temperature sense ADC — 3p3V September 2011 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual...

  • Page 46: Power Measurement

    Table 2–41. Power Measurement ADC Component References and Manufacturing Information Manufacturing Manufacturer Board Reference Description Manufacturer Part Number Website IC, power supply monitor U10, U11 Linear Technology LTC2978CUP#PBF www.linear.com w/EPROM, octal PMBUS Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual September 2011 Altera Corporation...

  • Page 47: Power Distribution System

    The device connects to the MAX II CPLD EPM2210 System Controller and the Stratix V GX device by a 2-wire SMB interface. The MAX1619 device is located at slave address 0011000b (18h). September 2011 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual...

  • Page 48: Statement Of China-Rohs Compliance

    (2) X* indicates that the concentration of the hazardous substance of at least one of all homogeneous materials in the parts is above the relevant threshold of the SJ/T11363-2006 standard, but it is exempted by EU RoHS. Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual September 2011 Altera Corporation...
  • Page 49 Stratix V GX transceiver signal integrity development board. Table A–1. Transceiver Signal Integrity Development Kit Revision History Version Release Date Description Engineering silicon September 2011 Initial release. September 2011 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual...
  • Page 50 A–2 Appendix A: Board Revision History Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual September 2011 Altera Corporation...
  • Page 51 (Software Licensing) Email authorization@altera.com Note to Table: (1) You can also contact your local Altera sales office or sales representative. Typographic Conventions The following table shows the typographic conventions this document uses. Visual Cue Meaning Indicate command names, dialog box titles, dialog box options, and other GUI Bold Type with Initial Capital labels.
  • Page 52 The envelope links to the Email Subscription Management Center page of the Altera website, where you can sign up to receive update notifications for Altera documents. Transceiver Signal Integrity Development Kit Stratix V GX Edition Reference Manual September 2011 Altera Corporation...

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