Status Register Set Contents - Keithley 2606B System SourceMeter Reference Manual

In this appendix:
Overview
Each 2606B provides a number of status registers and queues that are collectively referred to as the
status model. Through manipulation and monitoring of these registers and queues, you can view and
control various instrument events. You can include commands in your test program that can
determine if a service request (SRQ) event has occurred and the cause of the event.
The heart of the status model is the Status Byte Register. All status model registers and queues flow
into the Status Byte Register. The entire status model is illustrated in the
page E-4).

Status register set contents

Typically, a status register set contains the following registers:
•
Condition (.condition): A read-only register that is constantly updated to reflect the present
operating conditions of the instrument.
•
Enable Register (.enable): A read-write register that allows a summary bit to be set when an
enabled event occurs.
•
Event Register (.event): A read-only register that sets a bit to 1 when the applicable event
occurs. If the enable register bit for that event is also set, the summary bit of the register will set
to 1.
•
Negative Transition Register (NTR) (.ntr): When a bit is set in this read-write register, it
enables a 1 to 0 change in the corresponding bit of the condition register to cause the
corresponding bit in the event register to be set.
•
Positive Transition Register (PTR) (.ptr): When a bit is set in this read-write register, it
enables a 0 to 1 change in the corresponding bit of the condition register to cause the
corresponding bit in the event register to be set.
An event is represented by a condition register bit changing from a 1 to 0 or 0 to 1. When an event
occurs and the appropriate NTR or PTR bit is set, the corresponding event register bit is set to 1. The
event bit remains latched to 1 until the event register is read or the status model is reset. When an
event register bit is set and its corresponding enable bit is set, the summary bit of the register is set
to 1. This, in turn, sets a bit in a higher-level condition register, potentially cascading to the associated
summary bit of the Status Byte Register.
Overview .................................................................................. E-1
Clearing registers ................................................................... E-11
Programming and reading registers ....................................... E-12
Status byte and service request (SRQ) .................................. E-13
Status register sets ................................................................. E-16
TSP-Link system status .......................................................... E-22
Appendix E
Status model
Status model diagrams (on