Related Manuals for Altera APEX
Summary of Contents for Altera APEX
- Page 1 APEX PCI Development Kit Getting Started User Guide 101 Innovation Drive Kit Version: 2.1.0 San Jose, CA 95134 Document Version: 2.1.0 rev. 1 (408) 544-7000 Document Date: April 2002 http://www.altera.com...
- Page 2 Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S.
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Page 3: About This User Guide
Refer to the APEX PCI Development Kit readme file on the APEX PCI Development Kit for late-breaking information that is not available in this user guide. -
Page 4: How To Contact Altera
Altera literature services lit_req@altera.com (1) lit_req@altera.com (1) Non-technical customer (800) 767-3753 (408) 544-7000 service (7:30 a.m. to 5:30 p.m. Pacific Time) FTP site ftp.altera.com ftp.altera.com Note: You can also contact your local Altera sales office or sales representative. Altera Corporation... -
Page 5: Typographic Conventions
APEX PCI Development Kit Getting Started User Guide Typographic The APEX PCI Development Kit Getting Started User Guide uses the typographic conventions shown in Table Conventions Table 3. Conventions Visual Cue Meaning Bold Type with Initial Command names, dialog box titles, checkbox options, and dialog box options are Capital Letters shown in bold, initial capital letters. -
Page 7: Table Of Contents
Example 5. Address Offset & Target Loop (Debug) ............22 Configuring the APEX Device .....................24 Serial Configuration Using Flash Memory ................24 Selecting the Flash Section to Configure the APEX Device ........25 Flash Programming Walkthrough ................26 JTAG Configuration ......................28 Prototyping Overview ........................29 Install PCI Compiler ......................30... - Page 8 Contents Prototyping Walkthrough ......................32 Before You Begin ........................32 Synthesize the Reference Design ..................34 Compile the Reference Design in the Quartus II Software ..........36 Write the .rbf into the Flash Memory ..................37 Hardware Test the Reference Design ..................38 viii Altera Corporation...
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Page 9: About This Kit
You can also add a PCI mezzanine card (PMC), i.e., daughter card, to the board. Refer to the APEX PCI Development Board Data Sheet for more information on the board. -
Page 10: Features
The APEX PCI Development Kit contains the following documentation: APEX PCI Development Board Data Sheet—Describes the specifications of the board and how to load design data into the APEX device. PCI MegaCore Function User Guide—Provides the specifications of Altera PCI MegaCore functions and explains how to use them. -
Page 11: Getting Started
Jungo WinDriver device driver CD-ROM Note: The kit includes a CD-ROM containing a free 30-day evaluation of Jungo’s WinDriver device driver. Altera developed the kit application using WinDriver. For more information on the driver, refer to the documentation on the WinDriver CD-ROM. -
Page 12: Hardware Requirements
Hardware Requirements The APEX PCI development board is a 3.3-V PCI card that should only be used in 3.3-V PCI systems. To use the board in 5.0-V PCI systems, you must use a 5.0-V to 3.3-V PCI extender card to convert the 5.0-V PCI system to a 3.3-V PCI system. -
Page 13: Software Installation
The slot must be able to accommodate a long PCI form factor. Insert the APEX PCI development board into the PCI slot with the RS-232 connector facing the back of the computer. Make sure the board is firmly seated. Secure the board by installing the screw on the bracket on the back of the board. - Page 14 PC) show a counting pattern where LED 1 is the least significant bit and LED 7 is the most significant bit. The flashing LEDs indicate that the APEX device has been configured. Close your PC’s case.
- Page 15 APEX PCI Development Kit Getting Started User Guide Figure 1. APEX PCI Development Kit Directory Structure <path>\apex_pci_kit-v<version> Contains the executable file for the APEX PCI Development Kit Application. Contains the kit documentation. const_files Contains constraint files for the pci_mt64 MegaCore function that is used with the board.
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Page 16: Kit Application Walkthrough
(Debug) Example 5. Address Offset & Target Loop (Debug) To run the kit application, choose Programs > Altera > APEX PCI Development Kit (Windows Start menu). The kit application opens to the Demo tab with a PCI target write transaction selected for one iteration of 2,048 bytes of random data. -
Page 17: Example 1. Pci Target Write (Demo)
Getting Started APEX PCI Development Kit Getting Started User Guide Example 1. PCI Target Write (Demo) In this example, the data source is the system and the destination is the PCI card. You can verify this setup in the Command Information section of the kit application. -
Page 18: Example 2. Pci Master Write (Demo)
APEX PCI Development Kit Getting Started User Guide Getting Started Figure 3. PCI Target Write (Demo) Example 2. PCI Master Write (Demo) In this example, the data source is the PCI card and the destination is the system memory. You can verify this setup in the Command Information section of the kit application. -
Page 19: Example 3. Pci Master Loop (Debug)
Getting Started APEX PCI Development Kit Getting Started User Guide Review the results in the Display Window. Figure 4 shows the results. Figure 4. PCI Master Write (Demo) Example 3. PCI Master Loop (Debug) In this example, a PCI master read transaction is performed followed by a PCI master write. - Page 20 APEX PCI Development Kit Getting Started User Guide Getting Started Select AA55 Packet from the Data Type drop-down list box. Click Execute. Review the speed of transaction in the Display Window. Review the results in the Display Window. Figure 5 shows the results.
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Page 21: Example 4. Latency Timer Configuration Register & Pci Master Loop (Debug)
Getting Started APEX PCI Development Kit Getting Started User Guide Example 4. Latency Timer Configuration Register & PCI Master Loop (Debug) The operation in example 4 is the same as in example 3. By changing the Latency Timer setting, the PCI master device remains a master of the bus for more clock cycles, improving the throughput as the master device bursts more data. -
Page 22: Example 5. Address Offset & Target Loop (Debug)
APEX PCI Development Kit Getting Started User Guide Getting Started Figure 6. Latency Timer & PCI Master Loop (Debug) Example 5. Address Offset & Target Loop (Debug) In this example, a target loop transaction target write is performed, followed by a target read. The address offset changes the starting address of the transaction. - Page 23 Getting Started APEX PCI Development Kit Getting Started User Guide Figure 7. Address Offset & PCI Target Loop (Debug) Altera Corporation...
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Page 24: Configuring The Apex Device
APEX device configuration files. The number and size of flash memory sections that are available is dependent on the APEX device that is on the board. The kit application detects the APEX device via the PCI subsystem vendor ID configuration register. This subsystem ID register is a read-only register defined via a parameter in the Altera PCI MegaCore function. -
Page 25: Selecting The Flash Section To Configure The Apex Device
After you write a configuration file to the flash memory using the commands in the Flash tab in the kit application, you can click the Configure button to reconfigure the APEX device from the newly written flash memory. Figure 8 on page 25 shows the Flash programming tab. -
Page 26: Flash Programming Walkthrough
APEX PCI Development Kit Getting Started User Guide Getting Started Refer to the APEX PCI Development Board Data Sheet for the location of dip- switch S1. Tables 3 define the dip-switch settings used to access different sections of the flash memory for the development board that has the EP20K400E device or EP20K1000E/EP20K1000C device, respectively. - Page 27 Configure APEX Device (Optional) To configure the APEX device from flash memory, you must use an .rbf. Perform the following steps to write an .rbf to section 1 of the flash memory and configure the APEX device from this section using the kit application.
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Page 28: Jtag Configuration
Click Write. The write progress is displayed next to Status. The Display Window shows the data written into the flash memory. The APEX device can be configured from section 1 of the flash memory in one of the following two ways: –... -
Page 29: Prototyping Overview
JTAG chain, depending on the devices installed on the board. The jumper options allow you to bypass—or include—some of the JTAG components in the chain. Refer to the APEX PCI Development Board Data Sheet for the location of the jumpers and information on the JTAG chain circuit. Table 5 shows the jumper settings that you must use to configure the APEX device via the JTAG interface. -
Page 30: Install Pci Compiler
ModelSim (UNIX) Simulators White Paper Synthesize Your Application Design You can synthesize your design in a third-party synthesis tool; the Altera PCI MegaCore function is treated as a black box. Refer to the following tips as you are building your design:... -
Page 31: Compile In The Quartus Ii Software & Generate Programming Files
APEX PCI Development Kit for your own board design. Write the .rbf of Your Design into Flash You can use the reference design and the APEX PCI Development Kit application to write an .rbf into any available section of the flash memory. -
Page 32: Hardware Test Your Application Design
Getting Started Hardware Test Your Application Design You can use the open source APEX PCI Development Kit application as a starting point to develop your own program. You can also modify the kit application to perform hardware testing of your application design. - Page 33 Table 6 describes the Quartus II files used in the walkthrough. The files are located in the <path>\apex_pci_kit- v<version>\reference_design\quartus_<device> directory (where <device> is the APEX device installed on your board). Table 6. Quartus II Files Used in Walkthrough File Description my_pci.vhd...
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Page 34: Synthesize The Reference Design
(flash controller) information on these modules, refer to FS10: pci_mt64 MegaCore function sdr_inf (SDRAM interface) Reference Design and the APEX PCI Development Kit Configuration sdr_cntrl (SDRAM controller) Controller Circuit White Paper. To execute the walkthrough, perform the steps in the following sections. - Page 35 Getting Started APEX PCI Development Kit Getting Started User Guide Perform steps 6 through 8 for the flash_cntrl, sdr_inf, and sdr_cntrl directories, which are located in the <path>\apex_pci_kit- v<version>\reference_design\synthesis directory. 10. Select the top-level file <path>\apex_pci_kit- v<version>\reference_design\synthesis\apex_brd.vhd and click Open.
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Page 36: Compile The Reference Design In The Quartus Ii Software
APEX PCI Development Kit Getting Started User Guide Getting Started cntr3.vhd ctrl_logic.vhd regs.vhd sdr_inf.vhd tr_mw_sm.vhd addr_cntr.vhd apex_brd.vhd 12. Click the Optimize tab. 13. Turn off the Add I/O pads option. 14. Click the Output tab. 15. Make sure that c:\pci_prototype_example\apex_brd.edf file is listed in the Filename box. -
Page 37: Write The .Rbf Into The Flash Memory
Getting Started APEX PCI Development Kit Getting Started User Guide Click Next. Click No if you receive a message asking if you want to select a different top-level design entity name. Click User Library Pathnames. Type <path>\PCI_Compiler-v2.1.1\lib in the Library name box. -
Page 38: Hardware Test The Reference Design
Hardware Test the Reference Design The following steps describe how to perform hardware testing. Shut down your PC. Remove the APEX PCI development board from your PC. Change the board’s dip-switch settings to configure from section 1 of the flash memory.