Table 8.3. J7 D-Sub 25 Connection - Lattice Semiconductor ASC Bridge Board User Manual

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ASC Bridge Board
Evaluation Board User Guide

Table 8.3. J7 D-SUB 25 Connection

J7 Header
ASC Pin Function
Pin Number
1
GND
2
WDAT
3
RDAT
4
WRCLK
5
MANDATORY_RESET
6
GND
7
I2C_WRITE_EN
8
ASC_CLK
9
3.3 V
10
N.C.
11
12 V
12
5 V
13
GND
14
ASC_12V_OC_SHUTDOWN
15
ASC_12V_OC_SENSE
16
GND
17
ASC_RESET
18
I2C_SCL
19
I2C_SDA
20
ASC_5V_OC_SHUTDOWN
21
ASC_5V_OC_SENSE
22
ASC_BOARD_SENSE
23
12 V
24
5 V
25
5 V
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
10
Header Connection
J2
J2
J2
J2
J2
J3
J2
J2
J2
J2
J2
J2
J2
J2
Header Pin Number
27
31
33
28
32
5
25
29
35
18
16
37
39
36
FPGA-EB-02025-2.0

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