Alternate B Sweep - Tektronix 2215A Instruction Manual

lease U506A from the set condition. The circuit is then en­
abled to generate another sweep once a trigger signal is
again applied to the clock input of U506A.
P-P AUTO and TV FIELD. When P-P Auto or TV Field is
selected, the Auto Baseline configuration is enabled. Pin 12
of U532D is held LO by R569 and the output will follow the
signal provided by the Q output of U502. If trigger signals
are being received by U502, the output of U532D will be HI
and cause the output of U532C to be LO. Flip-flop U506A
will respond to trigger signals as described in the ' NORM'
section. If trigger signals are not being received by U502,
the output of U532D will be LO. The output of U532C will
then be the inverse of the input signal applied to pin 11 so
that U506A will be reset when holdoff ends, causing a
sweep to be generated. With no new trigger pulses being
applied to the circuitry, U506A will be continuously set and
then reset in this manner to generate sweeps.
SGL SWP. In the Sgl Swp mode, both the P-P AUTO and
NORM buttons are out. This results in a LO at the output of
U532C so that U506A is not held reset. A LO is also on
input pin 4 of U532A.
During the previous holdoff period, U532B had reset
U506B to cause the Q output to be LO. The D input of
U506A willjherefore be HI and clock signals to the gate will
keep the Q output LO and the sweep disabled. When the
SGL SWP button is pushed in, the Q output of U504A will
go LO for a time period determined by the time constant of
R504 and C504 and then return HI. This HI will then clock
through the HI on the D input of U506B to the Q output.
Consequently the output of U532A will go LO and CR514
will be reverse biased to bias on Q511 and light the READY
LED. The next trigger pulse applied to the clock input of
U506A will then initiate a sweep as described previously. At
the end of the sweep, U506B will again be reset, causing
the TRIG'D LED to go out and place a HI on the D input of
U506A. A new sweep will not be initiated until the SGL SWP
button is again pushed.
X-Y. In the X-Y mode of operation, the XY line is LO
which holds the input of U532B LO through CR518. The
output of U532B will hold U506A set and no sweeps can be
initiated.

ALTERNATE B SWEEP

The Alternate B Sweep circuitry, shown on Diagram 5,
produces a linear voltage ramp that is amplified by the Hori­
zontal Amplifier to provide the B Sweep horizontal deflec­
tion on the crt. The Alternate B Sweep circuitry also
produces the sweep-switching signals that control the dis­
play of the A and B Sweeps, and the gate signals used by
Theory of Operation— 2215A Service
the Intensity and Z-Axis circuits to establish the crt
unblanking and intensity levels needed for producing both
the A Intensified and B Sweep displays.
The B Sweep ramp is enabled by the B Sweep Logic
circuit either immediately after the end of the established
delay time (Runs After Delay) or upon receipt of the first
trigger signal after the delay time has elapsed. This delay
time is a function of the B Delay Time Position Comparator
circuit and the A sweep.
B Miller Sweep Generator
The B Miller Sweep Generator is composed of Q709,
Q710A, Q710B, Q712, and associated timing components.
This circuit produces the B Sweep and functions in the
same manner as the A Miller Sweep Generator; see the
' A Miller Sweep Generator" section for a description of cir­
cuitry operation. The output at the collector of Q712 drives
the Horizontal Amplifier and Q643.
B Trigger Level Comparator
The B Trigger Level Comparator is composed of transis­
tor array U605, U625C, Q619, and Q620. This circuit deter­
mines both the trigger level and slope at which the
B triggering signal is produced. It functions in the same
manner as the A Trigger Level Comparator with the exclu­
sion of the TV Trigger and Trigger View circuitry. See the ' A
Trigger Level Comparator" section for a description of the
circuit operation. Buffering of the inverting and noninverting
outputs of U625D is provided by U625A and U625B, and
Q630 and Q631 level shift the signals to TTL levels. The
circuit output at the collector of Q630 supplies trigger sig­
nals to clock U670A.
Runs After Delay
The Runs After Delay circuit allows the B Sweep Logic to
generate a B Sweep independently of any B Trigger signals.
In the Runs After Delay mode, B TRIGGER LEVEL control
R602 is rotated fully clockwise. This biases off Q637 and
places a LO on the collector. Inverter U660D will then have
a HI output with resistor R640 providing positive feedback.
The output of U660A will therefore be LO and U670A will be
held set with the Q output LO.
If the B TRIGGER LEVEL control is not fully clockwise,
Q637 is biased on and the B Sweep is in the triggered
mode. The output of U660D will be LO, the output of U660A
will be HI, and U670A will no longer be held set.
Operation of the B Sweep Logic circuitry under both of
these conditions is described in the " B Sweep Logic"
discussion.
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