VersaLogic Lion VL-EPMe-42 Reference Manual page 16

Table 9: TISR – 8254 Timer Interrupt Status Register
Bit Identifier
7 INTRTEST
TMRTEST
6
TMRIN4
5
TMRIN3
4
3 RESERVED
2 ISTAT_TC5
1 ISTAT_TC4
0 ISTAT_TC3
Lion (VL-EPMe-42) Programmer's Reference Manual
Access Default
Debug/Test Only -- 8254 Timer Interrupt Test (test mode only):
0 – No test interrupt
1 – If IRQEN is a 1 then an interrupt will assert in the selected
R/W 0
IRQ in the LPC SERIRQ stream (no timer interrupt mask needs
to be set for this)
R/W 0 Debug/Test Only -- 8254 Timer Test Mode:
0 – Normal operation
1 – Timer test mode. In the mode the OCTC3, OCTC4 (and
OCTC5 is ever implemented) outputs are set to Hi-Z and the
ICTC3, ICTC4 timer inputs are ignored.
R/W 0 Debug/Test Only -- 8254 Timer #4 test signal. When
INTRTEST = 1 this signal is used for the timer input control
instead of the external ICTC4 signal. When INTRTEST = 0 this
is ignored.
0 – deasserted
1 – asserted
R/W 0 Debug/Test Only -- 8254 Timer #3 test signal. When
INTRTEST = 1 this signal is used for the timer input control
instead of the external ICTC3 signal. When INTRTEST = 0 this
is ignored.
0 – deasserted
1 – asserted
RO
0 Reserved. Writes are ignored; reads always return 0.
Status for the 8254 Timer #5 output (terminal count) interrupt
when read. This bit is read-status and a write-1-to-clear.
0 – Timer output (terminal count) has not transitioned from 0 to
RW/C
N/A
a 1 level
1 – Timer output (terminal count) has transitioned from a 0 to a
1 level
Status for the 8254 Timer #4 output (terminal count) interrupt
when read. This bit is read-status and a write-1-to-clear.
0 – Timer output (terminal count) has not transitioned from 0 to
RW/C
N/A
a 1 level
1 – Timer output (terminal count) has transitioned from a 0 to a
1 level
Status for the 8254 Timer #3 output (terminal count) interrupt
when read. This bit is read-status and a write-1-to-clear.
0 – Timer output (terminal count) has not transitioned from 0 to
RW/C
N/A
a 1 level
1 – Timer output (terminal count) has transitioned from a 0 to a
1 level
FPGA Registers
Description
12