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M65881AFP
Digital Amplifier Processor of S-Master* Technology
DESCRIPTION
The M65881AFP is a S-Master technique processor for digital amplifier enable to convert from multi liner-PCM digital input signal
to high precise switching-pulse digital output without analog processing.
The M65881AFP has built-in 24bit sampling rate converter and digital-gain-controller.
The M65881AFP enables to realize high precise ( X`tal oscillation accuracy.) full digital amplifier systems combining with power
driver IC.
FEATURES
•Built-in 24bit Sampling Rate Converter.
Input Signal Sampling Rate from 32KHz to 192KHz (24bit Maximum).
4 kinds of Digital Input Format.
•Built-in L/R Independent Digital Gain Control.
•Built-in Soft Mute Function with Exponential Approximate-Curve.
•Correspondence to Output for Headphone.
MAIN SPECIFICATION
•Master Clock
Primary Clock: 256Fsi/512Fsi
•Input Signal Format:
MSB First Right Justified(16/20/24bit),MSB First Left Justified(24bit)
LSB First Right Justified(24bit),I
•Input Signal Sampling Rate from 32kHz to 192kHz.
•Gain Control Function:
+30dB~- dB (0.1dB Step until -96dB, -138dB Minimum)
•Third Order
(16Fso:6bit/5bit,32Fso:5bit)
APPLICATION
DVD Receiver, AV Amplifier
RECOMMENDED OPERATING CONDITIONS
Logic Block:1.8V±10%,PWM Buffer Block :3.3V±10%
SYSTEM BLOCK DIAGRAM)
LRCK
CD
DVD Audio
BCK
etc.
DATA
256fsi/512fsi
* "S-Master" is the digital amplifier technology developed by Sony Corporation. "S-Master" is a trademark of Sony Corporation.
page 1 of 23
Rev.1.00 2003.05.08
Secondary Clock: 1024Fso/512Fso
2
S(24bit)
M65881AFP
24bit
Sampling
Rate
Converter
32kHz
to
192kHz
Clock
MCU I/F
Level
Control
+30dB
to
-
Clock
1024fso/512fso
REJ03F0004-0100Z
OUTLINE : 42P2R
0.8mm pitch 42pin SSOP
Stream
Power
Driver
PWM
Stream
Power
Driver
Output
for Headphone
Rev.1.00
2003.05.08
LC
Filter
LC
Filter
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Related Manuals for Renesas M65881AFP
Summary of Contents for Renesas M65881AFP
- Page 1 Digital Amplifier Processor of S-Master* Technology DESCRIPTION The M65881AFP is a S-Master technique processor for digital amplifier enable to convert from multi liner-PCM digital input signal to high precise switching-pulse digital output without analog processing. The M65881AFP has built-in 24bit sampling rate converter and digital-gain-controller.
- Page 2 M65881AFP PIN CONFIGURATION VddL OUTL1 VssL 3.3V OUTL2 system XOVdd XfsoOUT XOVss DVdd 1.8V system DVss MCKSEL SCDT SCSHIFT SCLATCH NSPMUTE 3.3V system INIT LRCK DATA BFVdd BFVss XfsiIN page 2 of 23 Rev.1.00 2003.05.08 PWM output for Power Stage...
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Page 3: Block Diagram
M65881AFP BLOCK DIAGRAM page 3 of 23 Rev.1.00 2003.05.08... -
Page 4: Absolute Maximum Ratings
M65881AFP ABSOLUTE MAXIMUM RATINGS Parameter Symbol PWMVdd Supply Voltage BFVdd DVdd Input Voltage Range Power Dissipation Storage Temperature Tstg RECOMMENDED OPERATING CONDITIONS Parameter Symbol PWMVdd Supply Voltage BFVdd DVdd Operating Temperature XfsoIN Operating Frequency XfsiIN ELECTRICAL CHARACTERISTICS Parameter Symbol "H" Level Input Voltage VIH3 "L"... - Page 5 M65881AFP CHARACTERISTICS EVALUATION CIRCUIT OUTL1 OUTL2 OUTR2 LRCK OUTR1 DATA M65881AFP HPOUTL1 HPOUTL2 HPOUTR2 HPOUTR1 Reference characteristic Output for Power Stage THD+N Output for Headphone THD+N page 5 of 23 Rev.1.00 2003.05.08 • Input :1kHz 0dB Full scale sine wave 102dB(typ) •...
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Page 6: Pin Description
M65881AFP PIN DESCRIPTION Pin No. Name VddL Power Supply for Lch PWM Power Stage (3.3V) OUTL1 Lch PWM1 Output for Power Stage VssL GND for Lch PWM Power Stage OUTL2 Lch PWM2 Output for Power Stage XOVdd Power Supply for Secondary Master Clock Buffer ( 3.3V ) - Page 7 M65881AFP EXPLANATION OF OPERATION 1. DATA,BCK,LRCK DATA,BCK, and LRCK are input pins for Digital Audio Signal of CD, MD, DVD etc.. Input formats are supported by 4 ways, and are set by Serial Control, "System1 Mode, bit3 and bit4". Input data length are selectable in a case of "MSB First Right Justified"...
- Page 8 M65881AFP 2. SCDT, SCSHIFT, SCLATCH SCDT, SCSHIFT and SCLATCH are input pins for setting M65881AFP's operation. Input format of SCDT, SCSHIFT and SCLATCH is shown below. Input Format of SCDT, SCSHIFT and SCLATCH SCDT SCSHIFT SCLATCH • Mode Setting The operating mode are classified in four and assigned by bit1 and bit2. These four functions are shown below.
- Page 9 M65881AFP synchronizes in clock input from the external source devices. So it makes synchronized operation between source devices or another M65881AFP ( in case of Multi channel Operation ). The primary side operation ( input side of sampling rate converter ) are synchronized in LRCK, and the secondary side operation ( output side of sampling rate converter ) are synchronized in FsoI.
- Page 10 M65881AFP 7. OUTL1, OUTL2, OUTR1, OUTR2 OUTL1, OUTL2, OUTR1 and OUTR2 are pulse output modulated These pins are connected to external Power Driver ICs.The PWM output can be selected PWM Output Format 1, 2, 3 and 4 by serial control data(System1 mode, bit22,23 ).
- Page 11 *The rise edge from "L" to "H": Re-synchronization are operated, which is same at serial control SYNC function. (system2 mode bit6) 11. TEST1, TEST2 TEST1 and TEST2 pins are test input for factory shipping test of M65881AFP. TEST1 and TEST2 pins must be tied to "L" level on usual operation. 12. Power supply and GND Power supply and GND routes have a following 6 isolated lines.
- Page 12 M65881AFP 13. Power sequences System power-on sequencing Power(Vddxxx, HPVddxxx, XVdd, XOVdd, DVdd, BFVdd) Power OFF Master clock (XfsoIN,XfsiIN) INIT SCDT SCSHIFT SCLATCH *1 After a power supply and Master clock become to stable, INIT pin must be "L" over 5msec.
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Page 13: Serial Control
Gain Data Mantissa (LSB) •Output Limit (bit5,6: NSLMT1,2) The M65881AFP has Over Flow Limit function which detects by input signal level and limit gain control. The limit Value is set by Gain control Mode ( bit5,6 "NSLMT1, 2") and System2 Mode( bit17 "NSOBIT"). - Page 14 M65881AFP The index and Mantissa part of Gain Data (bit12-bit24 :GAIN0-GAIN12) The gain value is set from bit12-bit24. Index part: bit12(MSB) to bit16(LSB) Mantissa part: bit17(MSB) to bit24(LSB) The gain data is assigned 13bits, composed of Index part 5bits and of Mantissa part 8bits.
- Page 15 M65881AFP • Soft Mute The Soft Mute function is executed by setting of Gain Data as 00000/00000000b (" / " means dividing point between index part and mantissa part). The release from Soft Mute Function must be executed by setting the gain data before soft mute.
- Page 16 M65881AFP 2. System1 Mode Flag name Function Explanation Mode Setting 1 1 MODE1 Mode Setting 2 2 MODE2 3 IFMT0 Input Format Selection 4 IFMT1 5 IBIT0 Setting for Input Word Length 6 IBIT1 7 ISF0 Input sampling rate selection...
- Page 17 M65881AFP Fs Selection for De-emphasis filter (De-emphasis is "ON" except for bit9="L" and bit10="L". (bit9, bit10) : ("L", "L") except ("L", "L") … De-emphasis Filter on (Setting fsi) Zero Mute at DATA input ( bit11: DF1IMUTE ) "L" … Mute release "H"...
- Page 18 M65881AFP 3. System2 Mode Flag name Functional Explanation 1 MODE1 Mode settiing1 2 MODE2 Mode setting2 3 IMCKSEL Input master clock Selection 6 SYNC Re-synchronization 7 XFsoOEN XfsoOUT pin output "enable". 8 ASYNCEN2 Asynchronous Detection Flag for secondary Side 9 CHSEL...
- Page 19 "H" … "enable“ Under condition of ASYNCEN2="L", secondary side asynchronous detection is in-effective under asynchronous position, whether Fsol Clock is not inputted, there by M65881AFP does not operate function for instance mute operation. Reverse Lch/Rch for PWM Output pins (bit9: CHSEL) "L"...
- Page 20 M65881AFP AC CHARACTERISTICS (Ta=25ºC, PWMVdd=3.3V, DVdd=1.8V) Item XfsoIN Duty Ratio XfsiIN Duty Ratio SCSHIFT Pulse time SCDT Setup time SCDT Hold time SCLATCH Pulse Width SCLATCH Setup Time SCLATCH Hold time BCK Pulse Width DATA Setup Time DATA Hold time...
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Page 21: Application Example
M65881AFP APPLICATION EXAMPLE LRCK DATA XfsiIN (Primary Clock) SCDT SCSHIFT SCLATCH Initialize Control INIT Mute Control NSPMUTE Input Mode Select1 MODE1 Input Mode Select2 MODE2 page 21 of 23 Rev.1.00 2003.05.08 MCKSEL XFSOIN (Secondary Clock) XFSOOUT FsoCKO FsoI OUTL1 OUTL2... - Page 22 M65881AFP DETAILED DIAGRAM OF PACKAGE OUTLINE page 22 of 23 Rev.1.00 2003.05.08...
- Page 23 5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake.