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M65881AFP
2. System1 Mode
bit
Flag name
Mode Setting 1
1 MODE1
Mode Setting 2
2 MODE2
3 IFMT0
Input Format Selection
4 IFMT1
5 IBIT0
Setting for Input Word Length
6 IBIT1
7 ISF0
Input sampling rate selection
8 ISF1
9 EMPFS1
Fsi selection for De-emphasis Filter
10 EMPFS2
11 DF1IMUTE
Zero Mute at DATA input
12 DF2IMUTE
Zero Mute at sampling rate converter input
13
14
15
16
17
18
19
20
ASYNC1MODE Asynchronous Detection Flag for Primary Side
21
22 PWMMODE0 Selection for PWM Output type
23 PWMMODE1
24 PWMHP
Phase of HPOUTL1/R1 based on PWM output for power
Table 2-1 Selection of input format
bit
Flag Name
3
IFMT0
4
IFMT1
Table 2-2 Setting for Input Data Word Length
bit
Flag Name
5
IBIT0
6
IBIT1
Table 2-3 Selection of Input Sampling Rate (fsi:32k to 48kHz, 2fsi:64k to 96kHz, and 4fsi:128k to 192kHz)
bit
Flag Name
7
ISF0
8
ISF1
Table 2-4 Fs selection for De-emphasis filter (De-emphasis is "ON" except for bit9=L and bit10=L)
bit
Flag Name
9
EMPFS1
10
EMPFS2
Table 2-5 Selection PWM Output
bit
Flag name
22
PWMMODE0
23
PWMMODE1
•PWM Output Form2 enables to operate following conditions.
MCKSEL=L ( Secondary master clock 1024fso )
Serial Control System2 Mode; bit16 ( NSOBIT ) = "H" ( 5bit )
In case of the setting and release for PWM Output Form 2,
Refer to "The NOTE1 at setting PWM output Form 2" on next page.
Selection of Input format ( bit3,4: IFMT0,1)
Refer to Table 2-1.
Input word length (bit5,6: IBIT0,1)
Refer to Table 2-2. This setting is enable the case of MSB First Right justified.
Selection of Input Sampling Rate (bit7,8 : ISF0,1)
Refer to Table 2-3
page 16 of 23
Rev.1.00 2003.05.08
Function Explanation
MSB First Left
MSB First Right
Justified
Justified
L
L
16bit
20bit
24bit
L
L
H
L
H
L
fsi
2fsi
4fsi
L
H
L
L
L
H
32.0k
44.1k
48.0k
H
L
H
H
H
L
PWM Output Form1
PWM Output Form2
L
L
bit 17 ( NSSPEED )="L" (16fso )
H
"H" fixed
Refer to the Table2-1 below
Refer to the Table2-2 below
Refer to the Table2-3 below
Refer to the Table2-4 below
active
active
Zero Mute
Refer to the Table2-5 below
Same Phase
LSB First Right
Justified
H
L
L
H
Don't use
H
H
Don`t use
H
H
OFF
L
L
PWM Output Form3
H
L
No setting bits means "Don't care".
L
"L" fixed
non-active
non-active
PWM:duty50%
Reverse Phase
2
I
S
H
H
PWM Output Form4
L
H
H
H
INIT
–
–
L
L
L
L
L
L
L
L
L
L
–
–
–
–
–
–
–
L
–
L
L
L
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