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M65881AFP
3. System2 Mode
bit
Flag name
1 MODE1
Mode settiing1
2 MODE2
Mode setting2
3 IMCKSEL
Input master clock Selection
4
5
6 SYNC
Re-synchronization
7 XFsoOEN
XfsoOUT pin output "enable".
8 ASYNCEN2
Asynchronous Detection Flag for secondary Side
9 CHSEL
L/R inversion of PWM output pin
10 DRPOL
Block : Rch Input Phase
11 SRCRST
Sampling Rate Converter Reset
12 CHRSEL
L/R inversion of PWM output pin
13 GIMUTE
Zero Mute at Gain Control Input Clock
14 NSPMUTE
Duty 50% Mute for PWM Output
15 PGMUTE
G_MUTE of PWM Output Data
16 NSSPEED
Block : Operating Speed
17 NSOBIT
Block : Setting of Output bit number
18 DCDRPOL
Block : Rch Phase of AC dithering
19 DCDSEL0
20 DCDSEL1
21 ACDRPOL
Block : Rch Phase of AC dithering
22 ACDSEL0
23 ACDSEL1
24 ACDSEL2
Table 3-1 DC dithering selection at
Flag name
bit
19 DCDSEL0
20 DCDSEL1
Table 3-2 AC dithering selection at
Flag name
bit
22 ACDSEL0
23 ACDSEL1
24 ACDSEL2
Table 3-3 Setting of
Flag / Pin code name
bit
16 NSSPEED
17 NSOBIT
Pin MCKSEL
( Secondary master clock
The selection of primary master clock ( bit3: IMCKSEL )
L ... 256fsi
H ... 512fsi
( "512fsi" are divided into half "256fsi" and operate as primary master clock. )
Re-synchronization (bit6: SYNC)
Refer to Page9 in details on re-synchronous operation.
Resynchronization process starts by SYNC rise edge, therefore SYNC level must be fixed to
"L" just before SYNC operation.
"Enable" of a XfsoOUT output (bit7:XfsoOEN)
"L" ...
Clock Output (enable)
"H"...
"L" fixed (disable)
page 18 of 23
Rev.1.00 2003.05.08
Functional Explanation
Block : DC dithering selection
Block : AC dithering selection
block
Non dithering
DC dithering 0.1%
L
L
block
Non dithering
AC dithering A
don't care
L
L
block operating
16fso,6bit
L
L
L
( Secondary master
1024fso)
clock 1024fso)
H
"H" fixed
512fsi
L ->H : Resynchronization
disable
enable
active
Negative phase
active
active
active
active
active
32fso
5bit (31value)
Negative phase
Refer to Table 3-1
Negative phase
Refer to Table 3-2
DC dithering 0.2%
H
L
L
H
AC dithering C
L
L
H
L
L
H
16fso,5bit
16fso, 5bit
L
H
L
( Secondary master clock
512fso)
No setting bits means "Don't care".
L
"L" fixed
256fsi
enable
disable
non-active
Positive phase
non-active
non-active
non-active
non-active
non-active
16fso
6bit (63 value)
Positive phase
Positive phase
DC dithering 0.4%
H
H
AC dithering E
L
H
H
32fso, 5bit
X
H
X
H
H
L
( Secondary master
clock 1024fso)
INIT
-
-
L
-
-
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
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