Event Counter Mode - Philips CEM2100/00 Service Manual

8. 16-Bit TimerCounter 1 (TC1)
8.3 Function

8.3.3 Event Counter Mode

In the event counter mode, the up-counter counts up at the edge of the input pulse to the TC1 pin. Either the
rising or falling edge of the input pulse is selected as the count up edge in TC1CR<TC1S>.
When a match between the up-counter and the TC1DRA value is detected, an INTTC1 interrupt is generated
and the up-counter is cleared. After being cleared, the up-counter restarts counting at each edge of the input
pulse to the TC1 pin. Since a match between the up-counter and the value set to TC1DRA is detected at the
edge opposite to the selected edge, an INTTC1 interrupt request is generated after a match of the value at the
edge opposite to the selected edge.
Two or more machine cycles are required for the low-or high-level pulse input to the TC1 pin.
Setting TC1CR<ACAP1> to "1" captures the up-counter value into TC1DRB with the auto capture function.
Use the auto-capture function in the operative condition of TC1. A captured value may not be fixed if it's read
after the execution of the timer stop or auto-capture disable. Read the capture value in a capture enabled condi-
tion. Since the up-counter value is captured into TC1DRB by the source clock of up-counter after setting
TC1CR<ACAP1> to "1". Therefore, to read the captured value, wait at least one cycle of the internal source
clock before reading TC1DRB for the first time.
TC1 pin Input
Up-counter
TC1DRA
INTTC1
interrput request
Timer start
0
1 2
?
n
Figure 8-4 Event Counter Mode Timing Chart
Table 8-2 Input Pulse Width to TC1 Pin
NORMAL1/2, IDLE1/2 Mode
High-going
Low-going
n − 1
n
Match detect
Minimum Pulse Width [s]
SLOW1/2, SLEEP1/2 Mode
3
2 /fc
3
2 /fc
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T5CL8
At the
rising edge
(TC1S = 10)
0 1 2
Counter clear
3
2 /fs
3
2 /fs