Number Of Transfer Bits; Serial Clock; Clock Synchronization - Philips CEM2100/00 Service Manual

16. Serial Bus Interface(I2C Bus) Ver.-D (SBI)
16.5 I2C Bus Control

16.5.2 Number of transfer bits

The BC (Bits7 to 5 in SBICRA) is used to select a number of bits for next transmitting and receiving data.
Since the BC is cleared to "000" by a start condition, a slave address and direction bit transmissions are
always executed in 8 bits. Other than these, the BC retains a specified value.

16.5.3 Serial clock

16.5.3.1 Clock source
pin in the master mode.
clock which is input from SCL pin.

16.5.3.2 Clock synchronization

pulse to low will, in the first place, invalidate a clock pulse of another master device which generates a
high-level clock pulse.
In the master mode, a clock pulse for an acknowledge signal is not generated.
In the slave mode, a clock for a acknowledge signal is not counted.
The SCK (Bits2 to 0 in SBICRA) is used to select a maximum transfer frequency output from the SCL
Four or more machine cycles are required for both high and low levels of pulse width in the external
Note: Since the serial bus interface can not be used as the fast mode and the high-speed mode, do not set
SCK as the frequency that is over 100 kHz.
t HIGH
n
t LOW = 2 /fc
n
t HIGH = 2 /fc + 8/fc
fscl = 1/( t LOW + t HIGH)
t SCKL t SCKH
t SCKL , t SCKH > 4 tcyc
Note 1: fc = High-frequency clock
Note 2: tcyc = 4/fc (in NORMAL mode, IDLE mode)
Figure 16-3 Clock Source
2
In the I C bus, in order to drive a bus with a wired AND, a master device which pulls down a clock
t LOW 1/fscl
SCK (Bits2 to 0 in the SBICRA)
000
001
010
011
100
101
110
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n
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