Timercounter Control - Philips CEM2100/00 Service Manual

8. 16-Bit TimerCounter 1 (TC1)

8.2 TimerCounter Control

8.2 TimerCounter Control
The TimerCounter 1 is controlled by the TimerCounter 1 control register (TC1CR) and two 16-bit timer registers
(TC1DRA and TC1DRB).
Timer Register
TC1DRA
(0011H, 0010H)
TC1DRB
(0013H, 0012H)
TimerCounter 1 Control Register
TC1CR
(0026H)
TFF1
TFF1 Timer F/F1 control
ACAP1 Auto capture control
Pulse width measure-
MCAP1
ment mode control
External trigger timer
METT1
mode control
MPPG1 PPG output control
TC1S TC1 start control
TC1 source clock select
TC1CK
[Hz]
TC1 operating mode
TC1M
select
Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz]
Note 2: The timer register consists of two shift registers. A value set in the timer register becomes valid at the rising edge of the
first source clock pulse that occurs after the upper byte (TC1DRAH and TC1DRBH) is written. Therefore, write the lower
byte and the upper byte in this order (it is recommended to write the register with a 16-bit access instruction). Writing only
the lower byte (TC1DRAL and TC1DRBL) does not enable the setting of the timer register.
Note 3: To set the mode, source clock, PPG output control and timer F/F control, write to TC1CR during TC1S=00. Set the timer F/
F1 control until the first timer start after setting the PPG mode.
15 14 13 12 11
TC1DRAH (0011H)
(Initial value: 1111 1111 1111 1111)
TC1DRBH (0013H)
(Initial value: 1111 1111 1111 1111)
7 6 5 4
ACAP1
MCAP1
TC1S
METT1
MPPG1
0: Clear
0:Auto-capture disable
0:Double edge capture
0:Trigger start
0:Continuous pulse generation
00: Stop and counter clear
01: Command start
10: Rising edge start
Rising edge count (Event)
Positive logic count (Window)
11: Falling edge start
Falling edge count (Event)
Negative logic count (Window)
00
01
10
11
00: Timer/external trigger timer/event counter mode
01: Window mode
10: Pulse width measurement mode
11: PPG (Programmable pulse generate) output mode
10 9 8 7
Read/Write (Write enabled only in the PPG output mode)
3 2 1
TC1CK TC1M
Timer
O
O
(Ex-trigger/Pulse/PPG)
–
(Ex-trigger/Pulse/PPG)
–
NORMAL1/2, IDLE1/2 mode
DV7CK = 0
11
fc/2
7
fc/2
3
fc/2
External clock (TC1 pin input)
Page 78
T5CL8
6 5 4 3 2
TC1DRAL (0010H)
Read/Write
TC1DRBL (0012H)
0
Read/Write
(Initial value: 0000 0000)
1: Set
1:Auto-capture enable
1:Single edge capture
1:Trigger start and stop
1:One-shot
Extrig- Win-
Event Pulse
ger dow
O O O O
– – – –
O O O O
O O O O
Divider
DV7CK = 1
3
DV9
fs/2
7
DV5
fc/2
3
DV1
fc/2
1 0
R/W
R/W
PPG
O
O
R/W
O
O
SLOW,
SLEEP
mode
3
fs/2
R/W
–
–
R/W