Interrupt Control Circuit; Interrupt Latches (Il23 To Il2) - Philips CEM2100/00 Service Manual

3. Interrupt Control Circuit

The T5CL8 has a total of 24 interrupt sources excluding reset. Interrupts can be nested with priorities.
Four of the internal interrupt sources are non-maskable while the rest are maskable.
Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and independent vectors.
The interrupt latch is set to "1" by the generation of its interrupt request which requests the CPU to accept its inter-
rupts. Interrupts are enabled or disabled by software using the interrupt master enable flag (IMF) and interrupt enable
flag (EF). If more than one interrupts are generated simultaneously, interrupts are accepted in order which is domi-
nated by hardware. However, there are no prioritized interrupt factors among non-maskable interrupts.
Interrupt Factors
Internal/External (Reset)
Internal INTSWI (Software interrupt)
INTUNDEF (Executed the undefined instruction
Internal
interrupt)
Internal INTATRAP (Address trap interrupt)
Internal INTWDT (Watchdog timer interrupt)
External
INT0
Internal INTTC1
External INT1
Internal INTTBT
External INT2
Internal INTTC4
Internal INTTC3
Internal INTSBI
External INT3
Internal INTSIO1
Internal INTSIO2
Internal INTADC
Internal INTRXD1
Internal INTTXD1
Internal INTTC6
Internal INTTC5
Internal INTRXD2
Internal INTTXD2
Internal INTTC2
External
INT5
Note 1: To use the address trap interrupt (INTATRAP), clear WDTCR1<ATOUT> to "0" (It is set for the "reset request" after reset is
cancelled). For details, see "Address Trap".
Note 2: To use the watchdog timer interrupt (INTWDT), clear WDTCR1<WDTOUT> to "0" (It is set for the "Reset request" after
reset is released). For details, see "Watchdog Timer".
Note 3: If an INTADC interrupt request is generated while an interrupt with priority lower than the interrupt latch IL15 (INTADC) is
being accepted, the INTADC interrupt latch may be cleared without the INTADC interrupt being processed. For details,
refer to the corresponding notes in the chapter on the AD converter.

3.1 Interrupt latches (IL23 to IL2)

An interrupt latch is provided for each interrupt source, except for a software interrupt and an executed the unde-
fined instruction interrupt. When interrupt request is generated, the latch is set to "1", and the CPU is requested to
accept the interrupt if its interrupt is enabled. The interrupt latch is cleared to "0" immediately after accepting inter-
rupt. All interrupt latches are initialized to "0" during reset.
Enable Condition
Non-maskable
Non-maskable
Non-maskable
Non-maskable
Non-maskable
IMF• EF4 = 1, INT0EN = 1
IMF• EF5 = 1
IMF• EF6 = 1
IMF• EF7 = 1
IMF• EF8 = 1
IMF• EF9 = 1
IMF• EF10 = 1
IMF• EF11 = 1
IMF• EF12 = 1
IMF• EF13 = 1
IMF• EF14 = 1
IMF• EF15 = 1
IMF• EF16 = 1
IMF• EF17 = 1
IMF• EF18 = 1
IMF• EF19 = 1
IMF• EF20 = 1
IMF• EF21 = 1
IMF• EF22 = 1
IMF• EF23 = 1
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T5CL8
Interrupt Vector
Priority
Latch Address
– FFFE 1
– FFFC 2
– FFFC 2
IL2 FFFA 2
IL3 FFF8 2
IL4 FFF6 5
IL5 FFF4 6
IL6 FFF2 7
IL7 FFF0 8
IL8 FFEE 9
IL9 FFEC 10
IL10 FFEA 11
IL11 FFE8 12
IL12 FFE6 13
IL13 FFE4 14
IL14 FFE2 15
IL15 FFE0 16
IL16 FFBE 17
IL17 FFBC 18
IL18 FFBA 19
IL19 FFB8 20
IL20 FFB6 21
IL21 FFB4 22
IL22 FFB2 23
IL23 FFB0 24