Timing Generator - Philips CEM2100/00 Service Manual

2. Operational Description
2.2 System Clock Controller

2.2.2 Timing Generator

The timing generator generates the various system clocks supplied to the CPU core and peripheral hardware
from the basic clock (fc or fs). The timing generator provides the following functions.
2.2.2.1
and machine cycle counters.
TBTCR<DV7CK>, that is shown in Figure 2-4. As reset and STOP mode started/canceled, the prescaler
and the divider are cleared to "0".
SYSCK
DV7CK
High-frequency
clock fc
Low-frequency
clock fs
1. Generation of main system clock
2. Generation of divider output (
3. Generation of source clocks for time base timer
4. Generation of source clocks for watchdog timer
5. Generation of internal source clocks for timer/counters
6. Generation of warm-up clocks for releasing STOP mode
Configuration of timing generator
The timing generator consists of a 2-stage prescaler, a 21-stage divider, a main system clock generator,
An input clock to the 7th stage of the divider depends on the operating mode, SYSCR2<SYSCK> and
Main system clock generator
fc/4
1 2 1 2 3 4 5 6
Timer counter, Serial interface, Time-base-timer, divider output, etc. (Peripheral functions)
Figure 2-4 Configuration of Timing Generator
) pulses
DVO
fc or fs
S
Divider
A
Y
7 8 9 10 11 12 13
B
Multi-
plexer
Page 12
T5CL8
Machine cycle counters
14 15 16 17 18 19 20 21
S
B0
B1
A0 Y0
A1 Y1
Multiplexer
Warm-up
controller
Watchdog
timer