Beckhoff CB1064 Series Manual page 112

Kapitel: BIOS-Einstellungen
4.4.2.1 PCI Express Configuration
Aptio Setup Utility - Copyright (C) 2017 American Megatrends, Inc.
Chipset
┌─────────────────────────────────────────────────────────────────┬────────────────────────────────┐
│ PCI Express Configuration
│
│ PCI Express Clock Gating
│ Peer Memory Write Enable
│ Compliance Test Mode
│ PCIe-USB Glitch W/A
│► PCI Express Gen3 Eq Lanes
│
│► PCI Express Root Port 1
│ PCIE Port 5 is assigned to LAN
│ PCIE Port 6 is assigned to LAN2
│► PCI Express Root Port 7
│► PCI Express Root Port 8
│► PCI Express Root Port 9
│ PCIE Port 19 is assigned to PCIe
│ to PCI Bridge
│
│
│
│
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│
│
└─────────────────────────────────────────────────────────────────┴────────────────────────────────┘
Version 2.18.1263. Copyright (C) 2017 American Megatrends, Inc.
 PCI Express Clock Gating
Options: Disabled / Enabled
 Peer Memory Write Enable
Options: Disabled / Enabled
 Compliance Test Mode
Options: Disabled / Enabled
 PCIe-USB Glitch W/A
Options: Disabled / Enabled
 PCI Express Gen3 Eq Lanes
Sub menu: see "PCI Express Gen3 Eq Lanes" (page 113)
 PCI Express Root Port X
Sub menu: see "PCI Express Root Port" (page 114)
Seite 112
[Enabled]
[Disabled]
[Disabled]
[Disabled]
Beckhoff New Automation Technology CB1064-xxxx
│PCI Express Clock Gating
│Enabled/Disable for each root
│port.
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│────────────────────────────────│
│→←: Select Screen
│↑↓: Select Item
│Enter: Select
│+/-: Change Opt.
│F1: General Help
│F2: Previous Values
│F3: Optimized Defaults
│F4: Save & Exit
│ESC: Exit
│
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