Idle Command Segments - Keysight M8195A User Manual

3.10

Idle Command Segments

Mode
Sample Clock Divider = 1
Sample Clock Divider = 2
Sample Clock Dividier = 4
Keysight M8195A Revision 2 – Arbitrary Waveform Generator User's Guide
For some waveform types, like e.g. radar pulses, huge pause segments with a static
output are required between the real waveform segments. The gap between the real
segments should be adjustable in a fine granularity
The idle command segment allows setting a pause between segments in a granularity
that is smaller than the sync clock granularity. A minimum length of this pause is
required (see section 6.18.2). The idle command segment is treated as a segment within
sequences or scenarios. There is no segment loop count but a sequence loop counter
value is required for cases where the idle command segment is the first segment of a
sequence.
The granularity of the idle delay is equal to the waveform sample rate. The following
table shows the granularity of the idle delay in DAC samples:
Table 19: Idle delay granularity
Limitations:
The logic that executes idle command segments uses some elements, which are not in
sync clock granularity. To guarantee the trigger to sample output delay or the
advancement event to sample output delay, these elements need to be reset before
accepting new trigger or advancement events. This requires the waveform generation to
be stopped for at least 3 sync clock cycles before being restarted by a trigger or an
advancement event. A violation of this requirement leads to an unexpected output
behavior for some sync clock cycles.
Multiple adjacent idle command segments are not allowed. If the playtime of one idle
command segment is not sufficient, the overall required idle length can be separated
into multiple idle command segments where a normal data segment providing the static
idle value is put in between. Even this wouldn't be really necessary. One idle command
segment (delay of up to 2^24 sync clock cycles) and one additional small segment (e.g.
length: 10 * segment vectors, loop count: up to 2^32) would provide an idle delay of
more than 165 seconds in high speed mode at 64 GSa/s and should be sufficient for
most applications.
Idle Delay Granularity
1 DAC Output Sample
2 DAC Output Samples
4 DAC Output Samples
Sequencing 3
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