Freescale Semiconductor MK22FN256VDC12 Reference Manual

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K22F Sub-Family Reference Manual

Supports: MK22FN256VDC12, MK22FN256VLL12,

MK22FN256VMP12, MK22FN256VLH12

Document Number: K22P121M120SF8RM

Rev. 3, 7/2014

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Page 1 K22F Sub-Family Reference Manual Supports: MK22FN256VDC12, MK22FN256VLL12, MK22FN256VMP12, MK22FN256VLH12 Document Number: K22P121M120SF8RM Rev. 3, 7/2014...
Page 2 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 3: Table Of Contents
Memories and Memory Interfaces.......................52 2.2.4 Clocks................................52 2.2.5 Security and Integrity modules........................52 2.2.6 Analog modules............................53 2.2.7 Timer modules.............................53 2.2.8 Communication interfaces...........................54 2.2.9 Human-machine interfaces..........................55 Orderable part numbers..............................55 Chapter 3 Chip Configuration Introduction...................................57 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 4 DMA request multiplexer configuration......................74 3.3.9 DMA Controller Configuration........................77 3.3.10 External Watchdog Monitor (EWM) Configuration..................78 3.3.11 Watchdog Configuration..........................80 Clock modules................................81 3.4.1 MCG Configuration.............................81 3.4.2 OSC Configuration............................82 3.4.3 RTC OSC configuration..........................83 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 5 Flash Memory Configuration........................84 3.5.2 Flash Memory Controller Configuration.....................87 3.5.3 SRAM Configuration...........................87 3.5.4 System Register File Configuration......................89 3.5.5 VBAT Register File Configuration......................90 3.5.6 EzPort Configuration...........................90 Security..................................91 3.6.1 CRC Configuration............................92 3.6.2 RNG Configuration............................92 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 6 Chapter 4 Memory Map Introduction...................................137 System memory map..............................137 4.2.1 Aliased bit-band regions..........................138 4.2.2 Flash Access Control Introduction.......................140 Flash Memory Map...............................140 4.3.1 Alternate Non-Volatile IRC User Trim Description..................141 SRAM memory map..............................141 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 7 Debug trace clock............................157 5.7.5 PORT digital filter clocking.........................158 5.7.6 LPTMR clocking............................158 5.7.7 RTC_CLKOUT and CLKOUT32K clocking....................159 5.7.8 USB FS OTG Controller clocking.......................160 5.7.9 UART clocking............................161 5.7.10 LPUART0 clocking.............................161 5.7.11 I2S/SAI clocking............................162 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 8 Peripheral Doze............................180 7.2.5 Clock Gating..............................181 Power Modes Description.............................181 Entering and exiting power modes..........................183 Power mode transitions..............................184 Power modes shutdown sequencing..........................185 Flash Program Restrictions............................186 Module Operation in Low Power Modes........................186 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 9 Debug Resets................................202 AHB-AP..................................203 ITM....................................203 Core Trace Connectivity...............................204 9.10 TPIU....................................204 9.11 DWT.....................................204 9.12 Debug in Low Power Modes............................205 9.12.1 Debug Module State in Low Power Modes....................205 9.13 Debug & Security.................................206 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 10 Introduction...................................227 11.2 Overview..................................227 11.2.1 Features................................227 11.2.2 Modes of operation............................228 11.3 External signal description............................229 11.4 Detailed signal description............................229 11.5 Memory map and register definition..........................229 11.5.1 Pin Control Register n (PORTx_PCRn).......................236 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 11 System Clock Gating Control Register 5 (SIM_SCGC5)................266 12.2.11 System Clock Gating Control Register 6 (SIM_SCGC6)................267 12.2.12 System Clock Gating Control Register 7 (SIM_SCGC7)................270 12.2.13 System Clock Divider Register 1 (SIM_CLKDIV1)...................271 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 12 Flashloader Exit state...........................313 13.4 Peripherals Supported..............................315 13.4.1 I2C Peripheral..............................315 13.4.2 SPI Peripheral..............................316 13.4.3 UART Peripheral............................318 13.4.4 USB peripheral.............................321 13.5 Get/SetProperty Command Properties..........................323 13.5.1 Property Definitions.............................324 13.6 Kinetis Flashloader Status Error Codes........................326 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 13 Power mode transitions..........................347 15.4.2 Power mode entry/exit sequencing......................350 15.4.3 Run modes..............................352 15.4.4 Wait modes..............................354 15.4.5 Stop modes..............................355 15.4.6 Debug in low power modes.........................358 Chapter 16 Power Management Controller (PMC) 16.1 Introduction...................................361 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 14 LLWU Flag 1 register (LLWU_F1)......................379 17.3.7 LLWU Flag 2 register (LLWU_F2)......................381 17.3.8 LLWU Flag 3 register (LLWU_F3)......................382 17.3.9 LLWU Pin Filter 1 register (LLWU_FILT1)....................384 17.3.10 LLWU Pin Filter 2 register (LLWU_FILT2)....................385 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 15 19.2 Memory Map / Register Definition..........................398 19.3 Functional Description..............................398 19.3.1 General operation............................398 19.3.2 Arbitration..............................399 19.4 Initialization/application information...........................400 Chapter 20 Peripheral Bridge (AIPS-Lite) 20.1 Introduction...................................403 20.1.1 Features................................403 20.1.2 General operation............................403 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 16 22.1 Introduction...................................417 22.1.1 eDMA system block diagram........................417 22.1.2 Block parts..............................418 22.1.3 Features................................419 22.2 Modes of operation...............................421 22.3 Memory map/register definition...........................421 22.3.1 TCD memory...............................421 22.3.2 TCD initialization............................422 22.3.3 TCD structure...............................422 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 17 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (DMA_TCDn_NBYTES_MLOFFYES).....................466 22.3.24 TCD Last Source Address Adjustment (DMA_TCDn_SLAST)..............467 22.3.25 TCD Destination Address (DMA_TCDn_DADDR)...................468 22.3.26 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)..............468 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 18 Monitoring transfer descriptor status......................493 22.5.6 Channel Linking............................495 22.5.7 Dynamic programming..........................496 Chapter 23 External Watchdog Monitor (EWM) 23.1 Introduction...................................501 23.1.1 Features................................501 23.1.2 Modes of Operation.............................502 23.1.3 Block Diagram.............................503 23.2 EWM Signal Descriptions............................504 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 19 Windowed mode of operation........................516 24.3.5 Watchdog disabled mode of operation......................516 24.3.6 Debug modes of operation...........................517 24.4 Testing the watchdog..............................517 24.4.1 Quick test..............................518 24.4.2 Byte test................................518 24.5 Backup reset generator..............................519 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 20 External Signal Description............................535 25.3 Memory Map/Register Definition..........................535 25.3.1 MCG Control 1 Register (MCG_C1)......................536 25.3.2 MCG Control 2 Register (MCG_C2)......................537 25.3.3 MCG Control 3 Register (MCG_C3)......................538 25.3.4 MCG Control 4 Register (MCG_C4)......................539 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 21 MCG mode switching..........................559 Chapter 26 Oscillator (OSC) 26.1 Introduction...................................569 26.2 Features and Modes..............................569 26.3 Block Diagram................................570 26.4 OSC Signal Descriptions..............................570 26.5 External Crystal / Resonator Connections........................571 26.6 External Clock Connections............................572 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 22 External Crystal Connections............................583 27.4 Memory Map/Register Descriptions..........................583 27.5 Functional Description..............................583 27.6 Reset Overview................................584 27.7 Interrupts..................................584 Chapter 28 Flash Memory Controller (FMC) 28.1 Introduction...................................585 28.1.1 Overview..............................585 28.1.2 Features................................585 28.2 Modes of operation...............................586 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 23 Configuration options..........................608 28.5.3 Speculative reads............................608 28.6 Initialization and application information........................609 Chapter 29 Flash Memory Module (FTFA) 29.1 Introduction...................................611 29.1.1 Features................................612 29.1.2 Block Diagram.............................612 29.1.3 Glossary...............................613 29.2 External Signal Description............................614 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 24 30.1.3 Modes of operation............................658 30.2 External signal descriptions............................659 30.2.1 EzPort Clock (EZP_CK)..........................659 30.2.2 EzPort Chip Select (EZP_CS)........................660 30.2.3 EzPort Serial Data In (EZP_D)........................660 30.2.4 EzPort Serial Data Out (EZP_Q).........................660 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 25 32.2.1 Entering Normal mode..........................682 32.2.2 Entering Sleep mode............................682 32.3 Memory map and register definition..........................683 32.3.1 RNGA Control Register (RNG_CR)......................683 32.3.2 RNGA Status Register (RNG_SR)......................685 32.3.3 RNGA Entropy Register (RNG_ER)......................687 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 26 ADC Offset Correction Register (ADCx_OFS)...................709 33.3.9 ADC Plus-Side Gain Register (ADCx_PG)....................709 33.3.10 ADC Minus-Side Gain Register (ADCx_MG)....................710 33.3.11 ADC Plus-Side General Calibration Value Register (ADCx_CLPD)............710 33.3.12 ADC Plus-Side General Calibration Value Register (ADCx_CLPS)............711 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 27 Automatic compare function........................728 33.4.6 Calibration function.............................729 33.4.7 User-defined offset function........................731 33.4.8 Temperature sensor............................732 33.4.9 MCU wait mode operation...........................733 33.4.10 MCU Normal Stop mode operation......................733 33.4.11 MCU Low-Power Stop mode operation......................734 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 28 Functional description..............................756 34.3.1 CMP functional modes..........................756 34.3.2 Power modes..............................765 34.3.3 Startup and operation...........................766 34.3.4 Low-pass filter.............................767 34.4 CMP interrupts................................769 34.5 DMA support................................769 34.6 CMP Asynchronous DMA support..........................770 34.7 Digital-to-analog converter............................771 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 29 DAC data buffer operation...........................780 35.5.2 DMA operation............................782 35.5.3 Resets................................782 35.5.4 Low-Power mode operation.........................782 Chapter 36 Voltage Reference (VREFV1) 36.1 Introduction...................................785 36.1.1 Overview..............................786 36.1.2 Features................................786 36.1.3 Modes of Operation.............................787 36.1.4 VREF Signal Descriptions...........................787 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 30 Channel n Status register (PDBx_CHnS).....................806 37.3.7 Channel n Delay 0 register (PDBx_CHnDLY0)..................806 37.3.8 Channel n Delay 1 register (PDBx_CHnDLY1)..................807 37.3.9 DAC Interval Trigger n Control register (PDBx_DACINTCn)..............807 37.3.10 DAC Interval n register (PDBx_DACINTn)....................808 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 31 38.3.4 Counter (FTMx_CNT)..........................827 38.3.5 Modulo (FTMx_MOD)..........................828 38.3.6 Channel (n) Status And Control (FTMx_CnSC)..................829 38.3.7 Channel (n) Value (FTMx_CnV).........................832 38.3.8 Counter Initial Value (FTMx_CNTIN)......................832 38.3.9 Capture And Compare Status (FTMx_STATUS)..................833 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 32 Clock source..............................870 38.4.2 Prescaler...............................871 38.4.3 Counter.................................871 38.4.4 Input Capture mode............................877 38.4.5 Output Compare mode..........................880 38.4.6 Edge-Aligned PWM (EPWM) mode......................881 38.4.7 Center-Aligned PWM (CPWM) mode......................883 38.4.8 Combine mode.............................885 38.4.9 Complementary mode..........................892 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 33 Reset overview................................945 38.6 FTM Interrupts................................946 38.6.1 Timer Overflow Interrupt..........................947 38.6.2 Channel (n) Interrupt............................947 38.6.3 Fault Interrupt..............................947 38.7 Initialization Procedure..............................947 Chapter 39 Periodic Interrupt Timer (PIT) 39.1 Introduction...................................949 39.1.1 Block diagram..............................949 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 34 Low Power Timer Prescale Register (LPTMRx_PSR)................964 40.3.3 Low Power Timer Compare Register (LPTMRx_CMR)................966 40.3.4 Low Power Timer Counter Register (LPTMRx_CNR)................966 40.4 Functional description..............................967 40.4.1 LPTMR power and reset..........................967 40.4.2 LPTMR clocking............................967 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 35 RTC Write Access Register (RTC_WAR)....................981 41.2.10 RTC Read Access Register (RTC_RAR)....................982 41.3 Functional description..............................984 41.3.1 Power, clocking, and reset...........................984 41.3.2 Time counter..............................985 41.3.3 Compensation...............................986 41.3.4 Time alarm..............................986 41.3.5 Update mode..............................987 41.3.6 Register lock..............................987 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 36 OTG Status register (USBx_OTGSTAT)....................1005 42.4.8 OTG Control register (USBx_OTGCTL)....................1006 42.4.9 Interrupt Status register (USBx_ISTAT).....................1007 42.4.10 Interrupt Enable register (USBx_INTEN)....................1008 42.4.11 Error Interrupt Status register (USBx_ERRSTAT)..................1009 42.4.12 Error Interrupt Enable register (USBx_ERREN)..................1010 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 37 OTG and Host mode operation.............................1027 42.6 Host Mode Operation Examples...........................1028 42.7 On-The-Go operation..............................1031 42.7.1 OTG dual role A device operation.......................1031 42.7.2 OTG dual role B device operation.......................1033 42.8 Device mode IRC48 operation............................1034 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 38 Clock and Transfer Attributes Register (In Master Mode) (SPIx_CTARn)..........1053 44.3.4 Clock and Transfer Attributes Register (In Slave Mode) (SPIx_CTARn_SLAVE)........1058 44.3.5 Status Register (SPIx_SR)...........................1060 44.3.6 DMA/Interrupt Request Select and Enable Register (SPIx_RSER)............1063 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 39 44.5.5 Delay settings...............................1090 44.5.6 Calculation of FIFO pointer addresses......................1091 Chapter 45 Inter-Integrated Circuit (I2C) 45.1 Introduction...................................1095 45.1.1 Features................................1095 45.1.2 Modes of operation............................1096 45.1.3 Block diagram..............................1096 45.2 I2C signal descriptions..............................1097 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 40 45.4.5 Resets................................1120 45.4.6 Interrupts..............................1120 45.4.7 Programmable input glitch filter........................1123 45.4.8 Address matching wake-up..........................1123 45.4.9 DMA support...............................1124 45.5 Initialization/application information...........................1125 Chapter 46 Universal Asynchronous Receiver/Transmitter (UART) 46.1 Introduction...................................1129 46.1.1 Features................................1129 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 41 UART FIFO Receive Watermark (UARTx_RWFIFO)................1160 46.3.22 UART FIFO Receive Count (UARTx_RCFIFO)..................1161 46.3.23 UART 7816 Control Register (UARTx_C7816)..................1161 46.3.24 UART 7816 Interrupt Enable Register (UARTx_IE7816)................1163 46.3.25 UART 7816 Interrupt Status Register (UARTx_IS7816)................1164 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 42 ISO-7816/smartcard support........................1199 46.4.8 Infrared interface............................1204 46.5 Reset....................................1206 46.6 System level interrupt sources............................1206 46.6.1 RXEDGIF description..........................1206 46.7 DMA operation................................1207 46.8 Application information..............................1208 46.8.1 ISO-7816 initialization sequence.........................1208 46.8.2 Initialization sequence (non ISO-7816).......................1210 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 43 LPUART Modem IrDA Register (LPUARTx_MODIR)................1234 47.3 Functional description..............................1236 47.3.1 Baud rate generation............................1236 47.3.2 Transmitter functional description.......................1237 47.3.3 Receiver functional description........................1240 47.3.4 Additional LPUART functions........................1246 47.3.5 Infrared interface............................1248 47.3.6 Interrupts and status flags..........................1249 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 44 SAI Receive Data Register (I2Sx_RDRn)....................1275 48.3.17 SAI Receive FIFO Register (I2Sx_RFRn)....................1276 48.3.18 SAI Receive Mask Register (I2Sx_RMR)....................1276 48.3.19 SAI MCLK Control Register (I2Sx_MCR)....................1277 48.3.20 SAI MCLK Divide Register (I2Sx_MDR)....................1278 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 45 Port Data Input Register (GPIOx_PDIR).....................1295 49.2.6 Port Data Direction Register (GPIOx_PDDR).....................1296 49.3 Functional description..............................1296 49.3.1 General-purpose input..........................1296 49.3.2 General-purpose output..........................1296 Chapter 50 JTAG Controller (JTAGC) 50.1 Introduction...................................1299 50.1.1 Block diagram..............................1299 50.1.2 Features................................1300 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 46 50.4 Functional description..............................1305 50.4.1 JTAGC reset configuration..........................1305 50.4.2 IEEE 1149.1-2001 (JTAG) Test Access Port....................1305 50.4.3 TAP controller state machine........................1305 50.4.4 JTAGC block instructions..........................1307 50.4.5 Boundary scan..............................1310 50.5 Initialization/Application information..........................1310 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 47: About This Document
Hexadecimal number. For example, the hexadecimal equivalent of the number 60 is written 3Ch. In some cases, hexadecimal numbers are shown with the prefix 0x. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 48: Typographic Notation
Write 1 to clear: Refers to a register bitfield that must be written as 1 to be "cleared." K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 49: Introduction
• Multiple clock generation options available from internally- and externally- generated clocks • System oscillator to provide clock source for the MCU • RTC oscillator to provide clock source for the RTC Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 50: Arm® Cortex®-M4 Core Modules
The address is fetched via the instruction port allowing parallel register stacking and look-up. The first sixteen entries are allocated to ARM internal sources with the others mapping to MCU-defined interrupts. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 51: System Modules
The WDOG monitors internal system operation and forces a reset in case of failure. It can run from an independent 1 KHz low power oscillator with a programmable refresh window to detect deviations in program flow or system frequency. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 52: Memories And Memory Interfaces
The RTC oscillator has an independent power supply and supports a 32 kHz crystal oscillator to feed the RTC clock. Optionally, the RTC oscillator can replace the system oscillator as the main oscillator source. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 53: Security And Integrity Modules
ADC, DAC, or CMP. 2.2.7 Timer modules The following timer modules are available on this device: K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 54: Communication Interfaces
• 32-bit seconds counter with 32-bit Alarm • 16-bit Prescaler with compensation that can correct errors between 0.12 ppm and 3906 ppm 2.2.8 Communication interfaces The following communication interfaces are available on this device: K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 55: Human-Machine Interfaces
XFBGA 256 KB 48 KB MK22FN256VLL12 120 MHz LQFP 256 KB 48 KB MK22FN256VLH12 120 MHz LQFP 256 KB 48 KB MK22FN256VMP12 120 MHz MAPBGA 256 KB 48 KB K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 56 Orderable part numbers 1. This part number is subject to removal. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 57: Chip Configuration
3.2.1 ARM Cortex-M4 Core Configuration This section summarizes how the module has been configured in the chip. Full documentation for this module is provided by ARM and can be found at arm.com. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 58 Data code (DCODE) bus System bus The system bus is connected to a separate master port on the crossbar. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 59: Nested Vectored Interrupt Controller (Nvic) Configuration
3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration This section summarizes how the module has been configured in the chip. Full documentation for this module is provided by ARM and can be found at arm.com. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 60 The pin the NMI signal is multiplexed on, must be configured for the NMI function to generate the non-maskable interrupt request. 3.2.2.3 Interrupt channel assignments The interrupt source assignments are defined in the following table. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 61 DMA channel 8 transfer complete 0x0000_0064 DMA channel 9 transfer complete 0x0000_0068 DMA channel 10 transfer complete 0x0000_006C DMA channel 11 transfer complete Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 62 UART2 Single interrupt vector for UART status sources 0x0000_00D0 UART2 Single interrupt vector for UART error sources 0x0000_00D4 — — 0x0000_00D8 — — Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 63 — 0x0000_014C — — 0x0000_0150 — — 0x0000_0154 — — 0x0000_0158 — — 0x0000_015C — — 0x0000_0160 — — 0x0000_0164 ADC1 — 1. Indicates the NVIC's interrupt source number. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 64 NVICIPR14 bitfield range is 20-23 Therefore, the following bitfield locations are used to configure the LPTMR interrupts: • NVICISER1[26] • NVICICER1[26] • NVICISPR1[26] • NVICICPR1[26] • NVICIABR1[26] • NVICIPR14[23:20] K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 65: Asynchronous Wake-Up Interrupt Controller (Awic) Configuration
Port Control Module - Any enabled pin interrupt is capable of waking the system ADCx The ADC is functional when using internal clock source Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 66: Fpu Configuration
ARM Cortex-M4 Technical Reference Manual System memory map System memory map Clocking Clock Distribution Power Management Power Management Transfers ARM Cortex M4 core ARM Cortex-M4 core Private Peripheral Bus (PPB) K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 67: System Modules
Figure 3-6. SIM configuration Table 3-10. Reference links to related information Topic Related module Reference Full description System memory map System memory map Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 68: System Mode Controller (Smc) Configuration
Full description System Mode Controller (SMC) System memory map System memory map Power management Power management Power management controller (PMC) Low-Leakage Wakeup LLWU Unit (LLWU) Reset Control Module Reset (RCM) K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 69: Pmc Configuration
System memory map System memory map Clocking Clock distribution Power management Power management chapter Power Management Power Management Controller (PMC) Controller (PMC) Mode Controller Wake-up requests LLWU wake-up sources K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 70 2. Requires the peripheral and the peripheral interrupt to be enabled. The LLWU's WUME bit enables the internal module flag as a wakeup input. After wakeup, the flags are cleared based on the peripheral clearing mechanism. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 71: Mcm Configuration
3.3.6 Crossbar-Light Switch Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 72 Crossbar switch master EzPort EzPort Crossbar switch master USB FS/LS USB FS/LS Crossbar switch slave Flash Flash Crossbar switch slave Peripheral bridges Peripheral bridge Crossbar switch slave GPIO controller GPIO controller K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 73: Peripheral Bridge Configuration
3.3.7 Peripheral Bridge Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 74: Dma Request Multiplexer Configuration
3.3.8 DMA request multiplexer configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 75 Source description Async DMA number capable — Channel disabled Reserved Not used UART0 Receive UART0 Transmit UART1 Receive UART1 Transmit UART2 Receive UART2 Transmit Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 76 — Reserved — Reserved — Reserved — Reserved — ADC0 — ADC1 — CMP0 — CMP1 — Reserved — DAC0 — Reserved — Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 77: Dma Controller Configuration
3.3.9 DMA Controller Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 78: External Watchdog Monitor (Ewm) Configuration
3.3.10 External Watchdog Monitor (EWM) Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 79 This table shows the EWM low-power modes and the corresponding chip low-power modes. Table 3-23. EWM low-power modes Module mode Chip mode Wait Wait, VLPW Stop Stop, VLPS, LLS K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 80: Watchdog Configuration
This table shows the WDOG module clocks and the corresponding chip clocks. Table 3-25. WDOG clock connections Module clock Chip clock LPO Oscillator 1 kHz LPO Clock Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 81: Clock Modules
3.4 Clock modules 3.4.1 MCG Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 82 RTC 32kHz oscillator output. RTC clock is derived from external crystal circuit associated with RTC. OSCCLK1 - Oscillator IRC48MCLK. Derived from internal 48 MHz oscillator. Reserved — Clock Distribution for more details on these clocks. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 83: Osc Configuration
3.4.3 RTC OSC configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 84: Memories And Memory Interfaces
Related module Reference Full description Flash memory System memory map System memory map Clocking Clock Distribution Transfers Flash memory Flash memory controller controller Register access Peripheral bridge Peripheral bridge K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 85 The on-chip Flash is implemented in a portion of the allocated Flash range to form a contiguous block in the memory map beginning at address 0x0000_0000. See Flash Memory Sizes for details of supported ranges. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 86 3.5.1.8 FTF_FOPT Register The flash memory's FTF_FOPT register allows the user to customize the operation of the MCU at boot time. See FOPT boot options for details of its definition. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 87: Flash Memory Controller Configuration
See Crossbar-Light Switch Configuration for details on the master port assignments. 3.5.3 SRAM Configuration This section summarizes how the module has been configured in the chip. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 88 The amount of SRAM for the devices covered in this document is shown in the following table. Device SRAM_L size SRAM_U size Total SRAM (KB) Address Range (KB) (KB) MK22FN256VDC12 0x1FFF_C000-0x2000_7FFF MK22FN256VLL12 0x1FFF_C000-0x2000_7FFF MK22FN256VLH12 0x1FFF_C000-0x2000_7FFF MK22FN256VMP12 0x1FFF_C000-0x2000_7FFF K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 89: System Register File Configuration
This device includes a 32-byte register file that is powered in all power modes. The System Register file is made up of eight 4-byte registers RFSYS_REGn, where n ranges from 0 to 7. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 90: Vbat Register File Configuration
It is only reset during VBAT power-on reset. 3.5.6 EzPort Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 91: Security
The FOPT register is loaded from the flash option byte. If the flash option byte is modified the new value takes effect for any subsequent resets, until the value is changed again. 3.6 Security K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 92: Crc Configuration
Power management 3.6.2 RNG Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 93: Analog
3.7.1 16-bit SAR ADC Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 94 CPU load, the ADC supports DMA request functionality for higher performance when the ADC is sampled at a very high rate or cases where PDB is bypassed. The ADC can trigger the DMA (via DMA req) on conversion completion. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 95 ADC0_DM1 10101 AD21 Reserved Reserved 10110 AD22 Reserved Reserved 10111 AD23 Reserved 12-bit DAC0 Output/ADC0_SE23 11000 AD24 Reserved Reserved 11001 AD25 Reserved Reserved Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 96 ADC1_SE4b 00101 AD5b Reserved ADC1_SE5b 00110 AD6b Reserved ADC1_SE6b 00111 AD7b Reserved ADC1_SE7b 01000 Reserved ADC1_SE8 01001 Reserved ADC1_SE9 01010 AD10 Reserved Reserved Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 97 The following figure shows the assignment of ADCx_SEn channels a and b through a MUX selection to ADC. To select between alternate set of channels, refer to ADCx_CFG2[MUXSEL] bit settings for more details. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 98 There are other pins on this device that have a similar interleave configuration, including the plus side of differential pair pins available (for example ADC0_DP0 and ADC1_DP3). Refer to the Signal Multiplexing and Pin Assignments table for this device. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 99 0000 PDB external trigger pin input (PDB0_EXTRG) 0001 CMP0 output 0010 CMP1 output 0011 Reserved 0100 PIT trigger 0 0101 PIT trigger 1 Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 100 1. For ADC operation in Compute only, PSTOP1, Stop and VLPS, ADACK and the alternate clock sources are allowed clock sources. Note however that ALTCLK2 is force disabled and therefore not available in VLPS. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 101: Cmp Configuration
System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.7.2.1 CMP input connections The following table shows the fixed internal connections to the CMP. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 102 LPTMR configuration. In Time Counter mode with prescaler enabled, the delay is 1/2 Prescaler output period. In Time Counter mode with prescaler bypassed, the delay is 1/2 Prescaler clock period. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 103: 12-Bit Dac Configuration
3.7.3.2 12-bit DAC Output The output of the DAC can be placed on an external pin or set as one of the inputs to the analog comparator or ADC. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 104: Vref Configuration
Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.7.4.1 VREF Overview This device includes a voltage reference (VREF) to supply an accurate 1.2 V voltage output. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 105: Timers
Table 3-49. Reference links to related information Topic Related module Reference Full description System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 106 FTM2 initialization trigger and channel triggers, as programmed in the FTM external trigger register (EXTTRIG) 1011 Reserved 1100 RTC Alarm 1101 RTC Seconds 1110 LPTMR Output 1111 Software Trigger K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 107 The application code can set the PDBx_CHnC1[BB] bits to configure the PDB pre- triggers as a single chain or several chains. 3.8.1.4 PDB Interval Trigger Connections to DAC In this MCU, PDB interval trigger connections to DAC are implemented as follows. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 108: Flextimer Configuration
31:2 - Reserved 3.8.2 FlexTimer Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 109 Each module contains a register setting that allows the module to be clocked from an external clock instead. There are two external FTM_CLKINx pins that can be selected by any FTM module via the SIM_SOPT4 register. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 110 • FTM0 hardware trigger 2 = FTM0_FLT0 pin • FTM1 hardware trigger 0 = SIM_SOPT8[FTM1SYNCBIT] or CMP0 Output • FTM1 hardware trigger 1 = CMP1 Output • FTM1 hardware trigger 2 = FTM1_FLT0 pin K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 111 FTM2_CH1 input or the XOR of FTM2_CH0, FTM2_CH1 and FTM1_CH1 pins that will be applied to FTM2_CH1. Note: If the user utilizes FTM1_CH1 to be an input to FTM2_CH1, FTM1_CH0 can still be utilized for other functions. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 112 Also it limits the use of the FTM1_CH0 function, as the FTM1_CH1 will be programmed to provide a 50% duty PWM signal and limit the start and modulus values for the free running counter. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 113 Global time base (GTB)). FTM0 provides the only source for the FTM global time base. The other FTM modules can share the time base as shown in the following figure: K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 114: Pit Configuration
Figure 3-40. PIT configuration Table 3-55. Reference links to related information Topic Related module Reference Full description System memory map System memory map Clocking Clock Distribution Power management Power management K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 115: Low-Power Timer Configuration
Topic Related module Reference Full description Low-power timer Low-power timer System memory map System memory map Clocking Clock Distribution Power management Power management Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 116 The LPTMR_CSR[TPS] bitfield configures the input source used in pulse counter mode. The following table shows the chip-specific input assignments for this bitfield. LPTMR_CSR[TPS] Pulse counter input number Chip input CMP0 output LPTMR_ALT1 pin LPTMR_ALT2 pin Reserved K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 117: Rtc Configuration
RTC_CLKOUT signal outputs a 1 Hz or 32 kHz output derived from RTC oscillator as shown below. RTC_CR[CLKO] RTC 32kHz clock RTC_CLKOUT RTC 1Hz clock SIM_SOPT2[RTCCLKOUTSEL] Figure 3-43. RTC_CLKOUT generation K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 118: Communication Interfaces
1. Select the USB clock source by configuring SIM_SOPT2. 2. Select the desired clock divide ratio by configuring SIM_CLKDIV2. 3. Enable USB clock gate by setting SIM_SCGC4. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 119 The chip can be powered by two AA/AAA cells. In this case, the MCU is powered through VDD which is within the 1.8 to 3.0 V range. After USB cable insertion is detected, the USB regulator is enabled to power the USB transceiver. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 120 Li-ion battery. To PMC and Pads VOUT33 stab Chip TYPE A VREGIN VBUS Si2301 Charger Regulator USB0_DP Controller XCVR USB0_DM Li-Ion Figure 3-46. USB regulator Li-ion usecase K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 121 VBUS. NOTE An appropriately sized resistive voltage divider must be used if the GPIO pin does not directly support a 5V input. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 122 3.9.1.6 USB Voltage Regulator Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 123: Spi Configuration
Figure 3-50. SPI configuration Table 3-61. Reference links to related information Topic Related module Reference Full description System memory map System memory map Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 124 3.9.2.4 TX FIFO size Table 3-62. SPI transmit FIFO size SPI Module Transmit FIFO size SPI0 SPI1 3.9.2.5 RX FIFO Size SPI supports up to 16-bit frame size during reception. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 125 2. Enable the GPIO input to generate an interrupt on either the rising or falling edge (depending on the polarity of the chip select signal). 3. Enter Stop or VLPS mode and Wait for the GPIO interrupt. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 126 An 8-bit or 16-bit write to the command word does not push data onto the FIFO, but that command word is pushed to the TX FIFO on all subsequent 8-bit K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 127: I2C Configuration
The digital glitch filter implemented in the IIC module, controlled by the I2Cx_FLT[FLT] registers, is clocked from the bus clock and thus has filter granularity in bus clock cycle counts. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 128: Uart Configuration
The maximum baud rate is 1/16 of related source clock frequency. 3. IrDA is available on all UARTs 4. UART0 contains the standard features plus ISO7816 5. UART0 contains 8-entry transmit and 8-entry receive FIFOs K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 129 Receiver threshold (ISO7816) x — — Wait timer (ISO7816) — — Character wait timer — — (ISO7816) Block wait timer (ISO7816) — — Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 130: Lpuart Configuration
The LPUART0 module supports basic UART with DMA interface function and x4 to x32 oversampling of baud-rate. The module can remain functional in Stop and VLPS mode provided the clock it is using remains enabled. This module supports LIN slave operation. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 131: I2S Configuration
• TX data lines: 1 • RX data lines: 1 • FIFO size (words): 8 • Maximum words per frame: 16 • Maximum bit clock divider: 512 3.9.6.2 I S/SAI clocking K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 132 MCLK pin. The pin is the input from the pin when MOE is 0, and the pin is the output from the clock divider when MOE is 1. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 133 In VLPW and VLPR modes, the module is limited by the maximum bus clock frequencies. When operating from an internally generated bit clock or Audio Master Clock that is disabled in stop modes: K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 134: Human-Machine Interfaces
Table 3-72. Reference links to related information Topic Related module Reference Full description GPIO GPIO System memory map System memory map Clocking Clock Distribution Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 135 PTD7, PTC3, and PTC4. All other GPIO support normal drive option only. PTA4 includes a passive input filter that is enabled or disabled by PORTA_PCR4[PFE] control. This reset default is to have this function disabled. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 136 Human-machine interfaces K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 137: Memory Map
32-bit word of the aliased address space to a unique bit in the underlying RAM or peripheral address space to support single-bit insert and extract operations from the processor. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 138: Aliased Bit-Band Regions
Access rights to AIPS-Lite peripheral bridge and general purpose input/output (GPIO) module address space is limited to the core, DMA and EzPort. 2. ARM Cortex-M4 core access privileges also includes accesses via the debug interface. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 139 Figure 4-1. Alias bit-band mapping NOTE Each bit in bit-band region has an equivalent bit that can be manipulated through bit 0 in a corresponding long word in the alias bit-band region. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 140: Flash Access Control Introduction
The base address for each is specified in System memory map. Flash memory base address Registers Program flash base address Flash configuration field Program flash Figure 4-2. Flash memory map K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 141: Alternate Non-Volatile Irc User Trim Description
Accesses to the SRAM_L and SRAM_U memory ranges outside the amount of RAM on the device causes the bus cycle to be terminated with an error followed by the appropriate response in the requesting bus master. 4.5 Peripheral bridge (AIPS-Lite) memory map K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 142: Read-After-Write Sequence And Required Serialization Of Memory Operations
4.5.2 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map Table 4-2. Peripheral bridge 0 slot assignments System 32-bit base address Slot Module number 0x4000_0000 — 0x4000_1000 — 0x4000_2000 — Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 143 DMA channel mutiplexer 0x4002_2000 — 0x4002_3000 — 0x4002_4000 — 0x4002_5000 — 0x4002_6000 — 0x4002_7000 Analog-to-digital converter (ADC) 1 0x4002_8000 — 0x4002_9000 Random Number Generator (RNGA) Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 144 Port B multiplexing control 0x4004_B000 Port C multiplexing control 0x4004_C000 Port D multiplexing control 0x4004_D000 Port E multiplexing control 0x4004_E000 — 0x4004_F000 — 0x4005_0000 — Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 145 0x4007_2000 USB OTG FS/LS 0x4007_3000 Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) 0x4007_4000 Voltage reference (VREF) 0x4007_5000 — 0x4007_6000 — 0x4007_7000 — Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 146: Private Peripheral Bus (Ppb) Memory Map
Trace Port Interface Unit (TPIU) 0xE004_1000–0xE004_1FFF Reserved 0xE004_2000–0xE004_2FFF Reserved 0xE004_3000–0xE004_3FFF Reserved 0xE004_4000–0xE007_FFFF Reserved 0xE008_0000–0xE008_0FFF Miscellaneous Control Module (MCM) 0xE008_1000–0xE008_1FFF Reserved 0xE008_2000–0xE00F_EFFF Reserved 0xE00F_F000–0xE00F_FFFF ROM Table - allows auto-detection of debug components K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 147: Clock Distribution
SIM module. Reference those sections for detailed register and bit descriptions. 5.3 High-Level device clocking diagram The following system oscillator, MCG, and module registers control the multiplexers, dividers, and clock gates shown in the below figure: K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 148: Clock Definitions
Note: See subsequent sections for details on where these clocks are used. Figure 5-1. Clocking diagram 5.4 Clock definitions The following table describes the clocks in the previous block diagram. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 149: Device Clock Summary
OSC32KCLK or the RTC clock. RTC clock RTC oscillator output for the RTC module PMC 1kHz output 5.4.1 Device clock summary The following table provides more information regarding the on-chip clocks. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 150 30-40 kHz (low- range crystal) or Stop mode and 3-32 MHz (crystal) 3-32 MHz (crystal) OSC_CR[EREFST Up to 16 MHz EN] cleared (high-range crystal) Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 151 I2S_CLKIN TRACE clock Up to 120 MHz Up to 120 MHz Up to 4 MHz System clock or Trace is disabled MCGOUTCLK Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 152: Internal Clocking Requirements
50 MHz Bus clock 50 MHz Flash clock 25 MHz Option 2: Run Clock Frequency Core clock 80 MHz System clock 80 MHz Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 153: Clock Divider Values After Reset
VLPR mode to guarantee: • the core/system and bus clocks are less than or equal to 4 MHz, and • the flash memory clock is less than or equal to 1 MHz K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 154: Clock Gating
— Crossbar Switch System clock — — Peripheral bridges System clock Bus clock, Flash clock — LLWU, PMC, SIM, RCM Flash clock — Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 155 UART0, UART1 System clock — — UART2 Bus clock — — LPUART0 Bus clock LPUART0 clock — Bus clock S master clock I2S_TX_BCLK, I2S_RX_BCLK Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 156: Pmc 1-Khz Lpo Clock
MCG_C7[OSCSEL]=10) and either MCG is configured in an external clocking mode (PBE, BLPE, PEE, FBE or FEE) or MCG_C5[PLLCLKEN0] = 1. • SIM Control register selects IRC48 MHz clock — enabled when SIM_SOPT2[PLLFLLSEL]=11 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 157: Wdog Clocking
The WDOG may be clocked from two clock sources as shown in the following figure. WDOG clock Bus clock WDOG_STCTRLH[CLKSRC] Figure 5-2. WDOG clock generation 5.7.4 Debug trace clock The debug trace clock source can be clocked as shown in the following figure. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 158: Port Digital Filter Clocking
The prescaler and glitch filters in each of the LPTMRx modules can be clocked as shown in the following figure. NOTE The chosen clock must remain enabled if the LPTMRx is to continue operating in all required low-power modes. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 159: Rtc_Clkout And Clkout32K Clocking
In VLLS0 mode only the RTC oscillator is available. PTE0 is available in all packages for this device. PTE26 is not available in 64-pin packages for this device. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 160: Usb Fs Otg Controller Clocking
For the USB FS OTG controller to operate, the minimum system clock frequency is 20 MHz. The USB OTG controller also requires a 48 MHz clock. The clock source options are shown below. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 161: Uart Clocking
The LPUART0 module has a selectable clock as shown in the following figure. NOTE The chosen clock must remain enabled if the LPUART0 is to continue operating in all required low-power modes. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 162: I2S/Sai Clocking
The transmitter and receiver can independently select between the bus clock and the audio master clock to generate the bit clock. The MCLK and BCLK source options appear in the following figure. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 163 Clock System Clock Divider BCLK Divider Bus Clock BCLK_IN [MSEL] [DIV] [BCD] SIM_SOPT2[PLLFLLSEL] I2Sx_MCR[MOE] I2Sx_MDR[FRACT,DIVIDE] I2Sx_MCR[MICS] MCLK_IN MCLK_OUT Direction Control Pad Interface Logic Figure 5-9. I S/SAI clock generation K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 164 Module clocks K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 165: Reset And Boot
The MCU exits reset in functional mode that is controlled by EZP_CS pin to select between the single chip (default) or serial flash programming (EzPort) modes. See Boot options for more details. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 166: Reset
During and following a reset, the JTAG pins have their associated input pins configured • TDI in pull-up (PU) • TCK in pull-down (PD) • TMS in PU and associated output pin configured as: • TDO with no pull-down or pull-up K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 167 The LVD can be configured to generate a reset upon detection of a low voltage condition by setting the PMC's LVDSC1[LVDRE] bit to 1. The low voltage detection threshold is determined by the PMC's LVDSC1[LVDV] field. After an LVD reset has occurred, the K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 168 , as controlled by the C2[RANGE] field loc_low loc_high in the MCG module, the MCU resets. The RCM's SRS0[LOC] bit is set to indicate this reset source. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 169 The LOCKUP gives immediate indication of seriously errant kernel software. This is the result of the core being locked because of an unrecoverable exception following the activation of the processor’s built in system state protection hardware. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 170: Mcu Resets
The POR Only reset asserts on the POR reset source only. It resets the PMC and System Register File. The POR Only reset also causes all other reset types (except VBAT POR) to occur. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 171: Reset Pin
Chip Reset asserts on all reset sources and only negates after flash initialization has completed and the RESET_b pin has also negated. It resets the remaining modules (the modules not reset by other reset types). K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 172: Debug Resets
Use the CDBGRSTREQ bit within the SWJ-DP CTRL/STAT register to reset the debug modules. However, as explained below, using the CDBGRSTREQ bit does not reset all debug-related registers. CDBGRSTREQ resets the debug-related registers within the following modules: • SWJ-DP • AHB-AP K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 173: Boot
Serial flash programming mode (EzPort) Single chip (default) 1. CDBGRSTREQ does not affect AHB resources so that debug resources on the private peripheral bus are available during System Reset. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 174: Fopt Boot Options
EzPort mode if the EZP_CS/NMI pin is used for its NMI function. EzPort operation is enabled. The state of EZP_CS pin during reset determines if device enters EzPort mode. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 175: Boot Sequence
Core clock is enabled and the system is released from reset. EzPort mode is selected instead of the normal CPU execution if EZP_CS is low when the internal K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 176 NMI interrupt. The processor executes an Exception Entry and reads the NMI interrupt handler address from vector-table offset 8. The CPU begins execution at the NMI interrupt handler. Subsequent system resets follow this same reset flow. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 177: Power Management
If configured, a DMA request (using the asynchronous DMA wakeup) can also be used to exit Partial Stop for the duration of a DMA transfer before the device is transitioned back into PSTOP2. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 178: Dma Wakeup
Stop mode and then requesting bus slaves to enter Stop mode. In STOP and VLPS modes the MCG and PMC would then also enter their appropriate modes. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 179: Compute Operation
VLPS mode. The MCG, PMC, SRAM and Flash read port are not affected by Compute Operation, although the Flash register interface is disabled. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 180: Peripheral Doze
• The CPU is in Stop mode, including the entry sequence and for the duration of a DMA wakeup. • The CPU is in Compute Operation, including the entry sequence and for the duration of a DMA wakeup. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 181: Clock Gating
Stop mode entry is not supported directly from HSRUN and requires transition to Run prior to an attempt to enter a stop mode. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 182 LLS recovery. A portion of SRAM_U remains powered on (content retained and I/O states held). Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 183: Entering And Exiting Power Modes
The WFE instruction can have the side effect of entering a low- power mode, but that is not its intended usage. See ARM documentation for more on the WFE instruction. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 184: Power Mode Transitions
VLPR and VLPW are limited in frequency. The LLS and VLLSx mode(s) are the lowest power stop modes based on amount of logic or memory that is required to be retained by the application. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 185: Power Modes Shutdown Sequencing
• System level wait and VLPW modes equate to: SLEEPING & SLEEPDEEP • All other low power modes equate to: SLEEPING & SLEEPDEEP When entering the non-wait modes, the chip performs the following sequence: K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 186: Flash Program Restrictions
• static = Module register states and associated memories are retained. • powered = Memory is powered to retain contents. • low power = Memory is powered to retain contents in a lower power state K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 187 Core clock 4 MHz max Platform clock 4 MHz max 4 MHz max System clock 4 MHz max 4 MHz max OFF in CPO Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 188 CPO 200 kbit/s 200 kbit/s static, address static, address static match wakeup match wakeup static, address match wakeup FF in PSTOP2 in CPO Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 189 1. Using the LLWU module, the external pins available for this chip do not require the associated peripheral function to be enabled. It only requires the function controlling the pin (GPIO or peripheral) to be configured as an input to allow a transition to occur to the LLWU. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 190 VLLSx only supports low speed external pin to pin or external pin to DAC compares. Windowed, sampled & filtered modes of operation are not available while in stop, VLPS, LLSx, or VLLSx modes. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 191: Security
Further information regarding the flash security options and enabling/disabling flash security is available in the Flash Memory Module. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 192: Security Interactions With Other Modules
Blocks) command. A mass erase via the debugger is allowed even when some memory locations are protected. When mass erase is disabled, mass erase via the debugger is blocked. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 193: Debug
• ARM Real-Time Trace Interface(1-pin asynchronous mode only) The basic Cortex-M4 debug architecture is very flexible. The following diagram shows the topology of the core debug architecture and its components. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 194 Singlestep, Register Access, Run, Core Status S/W Instrumentation Messaging + Simple Data Trace Messaging + Watchpoint Messaging DWT (Data and Address Watchpoints) 4 data and address watchpoints Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 195: References
• ARM Debug Interface v5.1 • ARM CoreSight Architecture Specification 9.2 The Debug Port The configuration of the cJTAG module, JTAG controller, and debug port is illustrated in the following figure: K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 196: Jtag-To-Swd Change Sequence
3. Send more than 50 TCK cycles with TMS (SWDIO) =1 NOTE See the ARM documentation for the CoreSight DAP Lite for restrictions. 9.2.2 JTAG-to-cJTAG change sequence 1. Reset the debug port K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 197: Debug Port Pin Descriptions
TAPs (TDO) are muxed based on the IR code which is selected. This design is fully JTAG compliant and appears to the JTAG chain as a single TAP. At power on reset, ARM's IDCODE (IR=4'b1110) is selected. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 198: Ir Codes
JTAG, cJTAG, or SWD. The MDM-AP is accessible as Debug Access Port 1 with the available registers shown in the table below. Table 9-4. MDM-AP Register Summary Address Register Description Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 199: Mdm-Ap Control Register
SELECT[7:4] = 0xF selects the bank with IDR Bus Matrix A[3:2] = 2’b11 selects the IDR Register See Control and Status Register (IDR register reads 0x001C_0000) Descriptions Figure 9-3. MDM AP Addressing K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 200 This bit is used by the debugger to clear the sticky LLS and VLLSx mode entry status bits. This bit is asserted and cleared by the debugger. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 201: Mdm-Ap Status Register
1 Mass erase is enabled Backdoor Access Key Enable Indicates if the MCU has the backdoor access key enabled. 0 Disabled 1 Enabled Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 202: Debug Resets
9.6 Debug Resets The debug system receives the following sources of reset: • JTAG_TRST_b from an external signal. This signal is optional and may not be available in all packages. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 203: Ahb-Ap
The ITM is an application-driven trace source that supports printf style debugging to trace Operating System (OS) and application events, and emits diagnostic system information. The ITM emits trace information as packets. There are four sources that can K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 204: Core Trace Connectivity
DWT_COMP1, can also be used as a data comparator. • The DWT contains counters for: • Clock cycles (CYCCNT) • Folded instructions • Load store unit (LSU) operations • Sleep cycles K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 205: Debug In Low Power Modes
HW, the MDM-AP Control register can be configured hold the system in reset on recovery so that the debugger can regain control and reconfigure debug logic prior to the system exiting reset and resuming operation. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 206: Debug & Security
MDM-AP Control Register. In the case of a secure device that has mass erase disabled (FSEC[MEEN] = 10), attempts to mass erase via the debug interface are blocked. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 207: Signal Multiplexing And Signal Descriptions
Table 10-1. Reference links to related information Topic Related module Reference Full description Port control Port control System memory map System memory map Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 208: Port Control And Interrupt Module Features
Drive strength PTB0/PTB1 only PTC3/PTC4 only PTD4/PTD5/PTD6/ enable control PTD7 only Drive strength Disabled Disabled Disabled Disabled Disabled enable at reset Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 209: Clock Gating
The Port Control Module is responsible for selecting which ALT functionality is available on each pin. NOTE The 64-pin MAPBGA package offering is subject to removal. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 210 VREFH VREFH VREFL VREFL VREFL VSSA VSSA VSSA VREF_OUT/ VREF_OUT/ VREF_OUT/ CMP1_IN5/ CMP1_IN5/ CMP1_IN5/ CMP0_IN5/ CMP0_IN5/ CMP0_IN5/ ADC1_SE18 ADC1_SE18 ADC1_SE18 DAC0_OUT/ DAC0_OUT/ DAC0_OUT/ CMP1_IN3/ CMP1_IN3/ CMP1_IN3/ ADC0_SE23 ADC0_SE23 ADC0_SE23 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 211 SPI0_SOUT UART0_ I2S0_RX_FS CTS_b — — PTA17 ADC1_SE17 ADC1_SE17 PTA17 SPI0_SIN UART0_ I2S0_MCLK RTS_b PTA18 EXTAL0 EXTAL0 PTA18 FTM0_FLT2 FTM_ CLKIN0 PTA19 XTAL0 XTAL0 PTA19 FTM1_FLT0 FTM_ LPTMR0_ CLKIN1 ALT1 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 212 CMP1_IN0 CMP1_IN0 CTS_b CTS_b PTC3/ CMP1_IN1 CMP1_IN1 PTC3/ SPI0_PCS1 UART1_RX FTM0_CH2 CLKOUT I2S0_TX_ LPUART0_ LLWU_P7 LLWU_P7 BCLK — — PTC4/ DISABLED PTC4/ SPI0_PCS0 UART1_TX FTM0_CH3 CMP1_OUT LPUART0_ LLWU_P8 LLWU_P8 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 213 SPI1_SCK CTS_b — — — — — — PTD6/ ADC0_SE7b ADC0_SE7b PTD6/ SPI0_PCS3 UART0_RX FTM0_CH6 FTM0_FLT0 SPI1_SOUT LLWU_P15 LLWU_P15 PTD7 DISABLED PTD7 UART0_TX FTM0_CH7 FTM0_FLT1 SPI1_SIN — — — K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 214: K22F Pinouts
The following figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 215 USB0_DM PTC0 VOUT33 PTB19 VREGIN PTB18 ADC0_DP0/ADC1_DP3 PTB17 ADC0_DM0/ADC1_DM3 PTB16 ADC1_DP0/ADC0_DP3 PTB3 ADC1_DM0/ADC0_DM3 PTB2 VDDA PTB1 VREFH PTB0/LLWU_P5 VREFL RESET_b VSSA PTA19 Figure 10-2. K22F 64 LQFP Pinout Diagram K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 216 ADC1_DP0/ PTA4/ PTA13/ VREFL VREFH PTA19 ADC1_DP3 ADC0_DP3 LLWU_P3 LLWU_P4 VREF_OUT/ DAC0_OUT/ CMP1_IN5/ XTAL32 EXTAL32 VBAT PTA12 PTA18 CMP1_IN3/ CMP0_IN5/ ADC0_SE23 ADC1_SE18 Figure 10-3. K22F 64 MAPBGA Pinout Diagram K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 217 ADC0_DP1 PTB16 ADC0_DM1 ADC1_DP1/ADC0_DP2 ADC1_DM1/ADC0_DM2 PTB11 PTB10 ADC0_DP0/ADC1_DP3 ADC0_DM0/ADC1_DM3 PTB9 ADC1_DP0/ADC0_DP3 PTB3 PTB2 ADC1_DM0/ADC0_DM3 VDDA PTB1 PTB0/LLWU_P5 VREFH RESET_b VREFL VSSA PTA19 Figure 10-4. K22F 100 LQFP Pinout Diagram K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 218: Module Signal Description Tables
10.4 Module Signal Description Tables The following sections correlate the chip-level signal name with the signal name used in the module's chapter. They also briefly describe the signal function and direction. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 219: Core Modules
EWM input for safety status of external safety circuits. The polarity of EWM_in is programmable using the EWM_CTRL[ASSIN] bit. The default polarity is active-low. EWM_OUT EWM_out EWM reset out signal K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 220: Clock Modules
DADM3–DADM0 Differential Analog Channel Inputs ADC0_SEn Single-Ended Analog Channel Inputs VREFH Voltage Reference Select High REFSH VREFL Voltage Reference Select Low REFSL VDDA Analog Power Supply VSSA Analog Ground K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 221 Chip signal name Module signal Description name DAC0_OUT — DAC output Table 10-15. VREF Signal Descriptions Chip signal name Module signal Description name VREF_OUT VREF_OUT Internally-generated Voltage Reference output K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 222: Timer Modules
EXTRG External Trigger Input Source If the PDB is enabled and external trigger input source is selected, a positive edge on the EXTRG signal resets and starts the counter. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 223: Communication Interfaces
PCS4 Peripheral Chip Select 4 SPI0_PCS5 PCS5/ PCSS Peripheral Chip Select 5 /Peripheral Chip Select Strobe SPI0_SIN Serial Data In SPI0_SOUT SOUT Serial Data Out SPI0_SCK Serial Clock (O) K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 224 Receive Data Table 10-29. UART 0 Signal Descriptions Chip signal name Module signal Description name UART0_CTS Clear to send UART0_RTS Request to send UART0_TX Transmit data UART0_RX Receive data K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 225 I2S0_TXD SAI_TX_DATA Transmit Data. The transmit data is generated synchronously by the bit clock and is tristated whenever not transmitting a word. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 226: Human-Machine Interfaces (Hmi)
PORTD31–PORTD0 General-purpose input/output PTE[31:0] PORTE31–PORTE0 General-purpose input/output 1. The available GPIO pins depends on the specific package. See the signal multiplexing section for which exact GPIO signals are available. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 227: Port Control And Interrupts (Port)
• Support for interrupt or DMA request configured per pin • Asynchronous wake-up in low-power modes • Pin interrupt is functional in all digital pin muxing modes • Digital input filter on selected pins K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 228: Modes Of Operation
In Stop mode, the digital input filters are bypassed unless they are configured to run from the 1-kHz LPO clock source. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 229: External Signal Description
Any read or write access to the PORT memory space that is outside the valid memory map results in a bus error. All register accesses complete with zero wait states. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 230 11.5.2/238 reads 0) 4004_9084 Global Pin Control High Register (PORTA_GPCHR) (always 0000_0000h 11.5.3/239 reads 0) 4004_90A0 Interrupt Status Flag Register (PORTA_ISFR) 0000_0000h 11.5.4/240 Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 231 See section 11.5.1/236 4004_A07C Pin Control Register n (PORTB_PCR31) See section 11.5.1/236 4004_A080 Global Pin Control Low Register (PORTB_GPCLR) (always 0000_0000h 11.5.2/238 reads 0) Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 232 Pin Control Register n (PORTC_PCR28) See section 11.5.1/236 4004_B074 Pin Control Register n (PORTC_PCR29) See section 11.5.1/236 4004_B078 Pin Control Register n (PORTC_PCR30) See section 11.5.1/236 Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 233 4004_C064 Pin Control Register n (PORTD_PCR25) See section 11.5.1/236 4004_C068 Pin Control Register n (PORTD_PCR26) See section 11.5.1/236 4004_C06C Pin Control Register n (PORTD_PCR27) See section 11.5.1/236 Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 234 4004_D058 Pin Control Register n (PORTE_PCR22) See section 11.5.1/236 4004_D05C Pin Control Register n (PORTE_PCR23) See section 11.5.1/236 4004_D060 Pin Control Register n (PORTE_PCR24) See section 11.5.1/236 Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 235 4004_D0A0 Interrupt Status Flag Register (PORTE_ISFR) 0000_0000h 11.5.4/240 4004_D0C0 Digital Filter Enable Register (PORTE_DFER) 0000_0000h 11.5.5/240 4004_D0C4 Digital Filter Clock Register (PORTE_DFCR) 0000_0000h 11.5.6/241 4004_D0C8 Digital Filter Width Register (PORTE_DFWR) 0000_0000h 11.5.7/241 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 236: Pin Control Register N (Portx_Pcrn)
This read-only field is reserved and always has the value 0. Interrupt Status Flag The pin interrupt configuration is valid in all digital pin muxing modes. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 237 This read-only field is reserved and always has the value 0. Drive Strength Enable Drive strength configuration is valid in all digital pin muxing modes. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 238: Global Pin Control Low Register (Portx_Gpclr)
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 11.5.2 Global Pin Control Low Register (PORTx_GPCLR) Only 32-bit writes are supported to this register. Address: Base address + 80h offset GPWE GPWD Reset K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 239: Global Pin Control High Register (Portx_Gpchr)
Corresponding Pin Control Register is updated with the value in GPWD. 15–0 Global Pin Write Data GPWD Write value that is written to all Pin Control Registers bits [15:0] that are selected by GPWE. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 240: Interrupt Status Flag Register (Portx_Isfr)
The digital filter configuration is valid in all digital pin muxing modes. Address: Base address + C0h offset Reset PORTx_DFER field descriptions Field Description 31–0 Digital Filter Enable K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 241: Digital Filter Clock Register (Portx_Dfcr)
11.5.7 Digital Filter Width Register (PORTx_DFWR) This register is read only for ports that do not support a digital filter. The digital filter configuration is valid in all digital pin muxing modes. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 242: Functional Description
Pin Control register. For example, if an I C function is enabled on a pin, that does not override the pullup or open drain configuration for that pin. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 243: Global Pin Control
The external interrupt capability of the PORT module is available in all digital pin muxing modes provided the PORT module is enabled. Each pin can be individually configured for any of the following external interrupt modes: K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 244: Digital Filter
K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 245 The minimum latency through a digital filter equals two or three filter clock cycles plus the filter width configuration register. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 246 Functional description K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 247: System Integration Module (Sim)
• USB clock selection and divide values • Flash and system RAM size configuration • USB regulator configuration • FlexTimer external clock, hardware trigger, and fault source selection • UART0 and UART1 receive/transmit source selection/configuration K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 248: Memory Map And Register Definition
12.2.17/277 4004_8058 Unique Identification Register Mid-High (SIM_UIDMH) See section 12.2.18/277 4004_805C Unique Identification Register Mid Low (SIM_UIDML) See section 12.2.19/278 4004_8060 Unique Identification Register Low (SIM_UIDL) See section 12.2.20/278 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 249: System Options Register 1 (Sim_Sopt1)
USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes. USBSSTBY Controls whether the USB voltage regulator is placed in standby mode during Stop, VLPS, LLS and VLLS modes. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 250 1001 128 KB 1011 256 KB 11–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 5–0 This field is reserved. Reserved K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 251: Sopt1 Configuration Register (Sim_Sopt1Cfg)
Writing one to the URWE bit allows the SOPT1 USBREGEN bit to be written. This register bit clears after a write to USBREGEN. SOPT1 USBREGEN cannot be written. SOPT1 USBREGEN can be written. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 252: System Options Register 2 (Sim_Sopt2)
This read-only field is reserved and always has the value 0. 27–26 LPUART clock source select LPUARTSRC Selects the clock source for the LPUART transmit and receive clock. Clock disabled Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 253 CLKOUT select CLKOUTSEL Selects the clock to output on the CLKOUT pin. Reserved Reserved Flash clock LPO clock (1 kHz) MCGIRCLK RTC 32.768kHz clock Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 254: System Options Register 4 (Sim_Sopt4)
FTM2 channel match drives FTM0 hardware trigger 1 FlexTimer 0 Hardware Trigger 0 Source Select FTM0TRG0SRC Selects the source of FTM0 hardware trigger 0. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 255 FTM1CH0SRC Selects the source for FTM1 channel 0 input capture. NOTE: When the FTM is not in input capture mode, clear this field. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 256 NOTE: The pin source for fault 0 must be configured for the FTM module fault function through the appropriate pin control register in the port control module. FTM0_FLT0 pin CMP0 out K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 257: System Options Register 5 (Sim_Sopt5)
UART1_TX pin modulated with FTM2 channel 0 output Reserved 3–2 UART 0 receive data source select UART0RXSRC Selects the source for the UART 0 receive data. UART0_RX pin CMP0 Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 258: System Options Register 7 (Sim_Sopt7)
Alternate trigger selected for ADC1 as defined by ADC1TRGSEL. 14–13 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 259 PDB external trigger pin input (PDB0_EXTRG) 0001 High speed comparator 0 output 0010 High speed comparator 1 output 0011 Reserved 0100 PIT trigger 0 0101 PIT trigger 1 Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 260: System Options Register 8 (Sim_Sopt8)
FTM0_CH6 pin is output of FTM0 channel 6 output FTM0_CH6 pin is output of FTM0 channel 6 output, modulated by FTM1 channel 1 output Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 261 FTM0 Hardware Trigger 0 Software Synchronization FTM0SYNCBIT No effect Write 1 to assert the TRIG0 input to FTM0, software must clear this bit to allow other trigger sources to assert. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 262: System Device Identification Register (Sim_Sdid)
This read-only field is reserved and always has the value 0. 15–12 Device revision number REVID Specifies the silicon implementation number for the device. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 263 Reserved 0100 48-pin 0101 64-pin 0110 80-pin 0111 81-pin or 121-pin 1000 100-pin 1001 121-pin 1010 144-pin 1011 Custom pinout (WLCSP) 1100 169-pin 1101 Reserved 1110 256-pin 1111 Reserved K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 264: System Clock Gating Control Register 4 (Sim_Scgc4)
This read-only field is reserved and always has the value 0. UART2 Clock Gate Control UART2 This bit controls the clock gate to the UART2 module. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 265 This bit controls the clock gate to the EWM module. Clock disabled Clock enabled This field is reserved. Reserved This read-only field is reserved and always has the value 0. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 266: System Clock Gating Control Register 5 (Sim_Scgc5)
This bit controls the clock gate to the Port C module. Clock disabled Clock enabled Port B Clock Gate Control PORTB This bit controls the clock gate to the Port B module. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 267: System Clock Gating Control Register 6 (Sim_Scgc6)
This bit controls software access to the Low Power Timer module. Access disabled Access enabled 12.2.11 System Clock Gating Control Register 6 (SIM_SCGC6) Address: 4004_7000h base + 103Ch offset = 4004_803Ch Reset SPI1 SPI0 Reset K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 268 This bit controls the clock gate to the PIT module. Clock disabled Clock enabled PDB Clock Gate Control This bit controls the clock gate to the PDB module. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 269 This read-only field is reserved and always has the value 0. ADC1 Clock Gate Control ADC1 This bit controls the clock gate to the ADC1 module. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 270: System Clock Gating Control Register 7 (Sim_Scgc7)
This read-only field is reserved and always has the value 0. This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 271: System Clock Divider Register 1 (Sim_Clkdiv1)
0000 or 0111 depending on FTF_FOPT[LPBOOT]. 0000 Divide-by-1. 0001 Divide-by-2. 0010 Divide-by-3. 0011 Divide-by-4. 0100 Divide-by-5. 0101 Divide-by-6. 0110 Divide-by-7. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 272 0000 Divide-by-1. 0001 Divide-by-2. 0010 Divide-by-3. 0011 Divide-by-4. 0100 Divide-by-5. 0101 Divide-by-6. 0110 Divide-by-7. 0111 Divide-by-8. 1000 Divide-by-9. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 273: System Clock Divider Register 2 (Sim_Clkdiv2)
This field sets the fraction multiply value for the fractional clock divider when the MCGFLLCLK, or MCGPLLCLK, or IRC48M clock is the USB clock source (SOPT2[USBSRC] = 1). Divider output clock = Divider input clock × [ (USBFRAC+1) / (USBDIV+1) ] K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 274: Flash Configuration Register 1 (Sim_Fcfg1)
32 KB of program flash memory 0101 64 KB of program flash memory 0111 128 KB of program flash memory 1001 256 KB of program flash memory Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 275 Flash accesses are disabled (and generate a bus error) and the Flash memory is placed in a low power state. This bit should not be changed during VLP modes. Relocate the interrupt vectors out of Flash memory before disabling the Flash. Flash is enabled Flash is disabled K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 276: Flash Configuration Register 2 (Sim_Fcfg2)
+ 0x4_0000. This would be the MAXADDR1 value for a device with 512 KB program flash memory across two flash blocks and no FlexNVM. 15–0 This field is reserved. Reserved This read-only field is reserved and always has the value 0. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 277: Unique Identification Register High (Sim_Uidh)
0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* Reset * Notes: • Reset value loaded during System Reset from Flash IFR. SIM_UIDMH field descriptions Field Description 31–0 Unique Identification Unique identification for the device. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 278: Unique Identification Register Mid Low (Sim_Uidml)
Reset value loaded during System Reset from Flash IFR. SIM_UIDL field descriptions Field Description 31–0 Unique Identification Unique identification for the device. 12.3 Functional description For more information about the functions of SIM, see the Introduction section. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 279: Kinetis Flashloader
The flashloader_loader program copies the contents of flashloader image from the flash to the on-chip RAM; the device then switches execution to the flashloader program to execute from RAM. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 280 Returns the contents of the IFR field or Flash firmware ID, by given offset, byte count and option WriteMemory Write data to memory ReadMemory Read data from memory Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 281: Functional Description
The following sub-sections describe the Kinetis Flashloader functionality. 13.3.1 Memory Maps While executing, the Kinetis Flashloader uses RAM memory. Available 0x2000_8000 Flashloader use 0x1FFF_C000 Figure 13-1. Kinetis Flashloader RAM Memory Map 13.3.2 Kinetis Flashloader K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 282: Start-Up Process
• There is no timeout for the active peripheral detection process. • If communication is detected, then all inactive peripherals are shut down, and the command phase is entered. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 283: Clock Configuration
Figure 13-2. Kinetis Flashloader Start-up Flowchart 13.3.4 Clock Configuration The Kinetis Flashloader uses the clock configuration of the chip out of reset. The flashloader does not modify any clocks. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 284: Flashloader Protocol
Figure 13-3. Command with No Data Phase 13.3.5.2 Command with incoming data phase The protocol for a command with an incoming data phase contains: • Command packet (from host) K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 285 Figure 13-4. Command with incoming data phase NOTE • The host may not send any further packets while it (the host) is waiting for the response to a command. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 286 The protocol for a command with an outgoing data phase contains: • Command packet (from host) • ReadMemory Response command packet (to host) (kCommandFlag_HasDataPhase set) • Outgoing data packets (to host) • Generic response command packet (to host) K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 287 • If the ReadMemory Response command packet prior to the start of the data phase does not contain the kCommandFlag_HasDataPhase flag, then the data phase is aborted. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 288: Flashloader Packet Types
A Ping packet must be sent before any other communications. In response to a Ping packet, the target sends a Ping Response packet. Table 13-3. Ping Packet Format Byte # Value Name 0x5A start byte 0xA6 ping K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 289 Ping response code Protocol bugfix Protocol minor Protocol major Protocol name = 'P' (0x50) Options low Options high CRC16 low CRC16 high The Serial Protocol Version number returned is 1.1.0. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 290 = src[j]; crc ^= byte << 8; for (i = 0; i < 8; ++i) uint32_t temp = crc << 1; if (crc & 0x8000) temp ^= 0x1021; K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 291 The command packet carries a 32-bit command header and a list of 32-bit parameters. Table 13-8. Command Packet Format Command Packet Format (32 bytes) Command Header (4 bytes) 28 bytes for Parameters (Max 7 parameters) Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 292 FlashEraseRegion Flashloader. The valid command tags for the 0x03 ReadMemory Kinetis Flashloader are listed here. 0x04 WriteMemory 0x06 FlashSecurityDisable 0x07 GetProperty 0x09 Execute 0x0B Reset 0x0C SetProperty 0x0D Reserved K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 293 13.3.6.6 Response packet The responses are carried using the same command packet format wrapped with framing packet data. There are 3 types of responses: • GenericResponse K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 294 ReadMemory command. The ReadMemoryResponse packet contains the framing packet data and the command packet data, with the command/response tag set to a ReadMemoryResponse tag value (0xA3), the flags field set to kCommandFlag_HasDataPhase (1). K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 295: Flashloader Command Api
For a list of properties and their associated 32-bit property tags supported by the Kinetis Flashloader, see Table 13-43. The 32-bit property tag is the only parameter required for GetProperty command. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 296 0, followed by the property value(s). The next table shows an example of a GetPropertyResponse packet. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 297 The property tag and the new value to set are the 2 parameters required for the SetProperty command. Table 13-19. Parameters for SetProperty Command Byte # Command 0 - 3 Property tag 4 - 7 Property value K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 298 The SetProperty command has no data phase. Response: The target (Kinetis Flashloader) will return a GenericResponse packet with one of following status codes: Table 13-21. SetProperty Response Status Codes Status Code kStatus_Success kStatus_ReadOnly kStatus_UnknownProperty kStatus_InvalidArgument K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 299 0x5A packetType 0xA4, kFramingPacketType_Command length 0x04 0x00 crc16 0xC4 0x2E Command packet commandTag 0x01 - FlashEraseAll flags 0x00 reserved 0x00 parameterCount 0x00 The FlashEraseAll command has no data phase. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 300 Response: The target (Kinetis Flashloader ) will return a GenericResponse packet with one of following error status codes. Table 13-24. FlashEraseRegion Response Status Codes Status Code kStatus_Success (0) kStatus_MemoryRangeInvalid (10200) kStatus_FlashAlignmentError (101) kStatus_FlashAddressError (102) kStatus_FlashAccessError (103) kStatus_FlashProtectionViolation (104) kStatus_FlashCommandFailure (105) K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 301 Generic Response: 0x5a a4 0c 00 97 04 a0 00 00 02 00 00 00 00 05 00 00 00 ACK: 0x5a a1 Figure 13-10. Protocol Sequence for FillMemory Command K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 302 Table 13-27. Parameters for FlashProgramOnce Command Byte # Command 0 - 3 Index of program once field 4 - 7 Byte count 8 - 11 Data 12 - 16 Data K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 303 13.3.7.7 FlashReadOnce command The FlashReadOnce command returns the contents of the program once field by given index and byte count. The FlashReadOnce command uses 2 parameters: index and byteCount. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 304 Value Framing packet start byte 0x5A packetType 0xA4 length 0x0C 0x00 0xC1 0xA5 Command packet commandTag 0x0F – FlashReadOnce flags 0x00 reserved 0x00 parameterCount 0x02 index 0x0000_0000 byteCount 0x0000_0004 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 305 Start address of specific non-volatile memory to be read 4 - 7 byteCount Byte count to be read 8 - 11 option 0: IFR 1: Flash firmware ID K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 306 Framing packet start byte 0x5A packetType 0xA4 length 0x10 0x00 0xB3 0xCC Command packet commandTag 0x10 – FlashReadResource flags 0x00 reserved 0x00 parameterCount 0x03 startAddress 0x0000_0000 byteCount 0x0000_0008 option 0x0000_0001 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 307 When writing to RAM, the start address need not be aligned, and the data will not be padded. The start address and number of bytes are the 2 parameters required for WriteMemory command. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 308 Generic Response 0x5a a4 0c 00 23 72 a0 00 00 02 00 00 00 00 04 00 00 00 ACK: 0x5a a1 Figure 13-14. Protocol Sequence for WriteMemory Command K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 309 Table 13-37. Parameters for read memory command Byte Parameter Description Start address Start address of memory to read from Byte count Number of bytes to read and return to caller K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 310 Flashloader) works in slave mode, the host need pull data packets until the number of bytes of data specified in the byteCount parameter of ReadMemory command are received by host. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 311 Table 13-40. FlashSecurityDisable Command Packet Format (Example) FlashSecurityDisable Parameter Value Framing packet start byte 0x5A packetType 0xA4, kFramingPacketType_Command length 0x0C 0x00 crc16 0x43 0x7B Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 312 Response: The target (Kinetis Flashloader) will return a GenericResponse packet with status code either set to kStatus_Success for successful execution of the command, or set to an appropriate error status code. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 313 Response: The target (Kinetis Flashloader) will return a GenericResponse packet with a status code either set to kStatus_Success upon successful execution of the command, or set to an appropriate error status code. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 314: Flashloader Exit State
• UART and UART clock source (SIM_SOPT2_PLLFLLSEL = 3) • SPI • I2C You must re-configure the corresponding register to the expected value, instead of relying on the default value. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 315: Peripherals Supported
Read 1 byte of ping response packet from target Read 1 byte 0x5A 0x7A Report Error received? received? from target Figure 13-18. Host reads ping response from target via I2C K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 316: Spi Peripheral
Figure 13-20. Host reads response from target via I2C 13.4.2 SPI Peripheral The Kinetis Flashloader supports loading data into flash via the SPI peripheral, where the SPI peripheral serves as a SPI slave. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 317 Send 0x00 to 0x5A 0xA7 Report Error shift out 1 byte received? received? from target Figure 13-21. Host reads ping packet from target via SPI K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 318: Uart Peripheral
Figure 13-23. Host reads response from target via SPI 13.4.3 UART Peripheral The Kinetis Flashloader integrates an autobaud detection algorithm for the UART peripheral, thereby providing flexible baud rate choices. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 319 • How the host detects an ACK from the target • How the host detects a ping response from the target • How the host detects a command response from the target K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 320 0x5A 0xA7 Wait for 1 byte Report Error received? received? from target Figure 13-25. Host reads a ping response from target via UART K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 321: Usb Peripheral
The flashloader also enables the USB clock recovery feature (by setting USB_CLK_RECOVER_CTRL bit 7 (CLOCK_RECOVER_EN) to 1 and USB_CLK_RECOVER_IRC_EN bit 1 (IRC_EN) to 1). 13.4.4.2 Device descriptor The Kinetis flashloader configures the default USB VID/PID/Strings as below: K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 322 Peripherals Supported Default VID/PID: • VID = 0x15A2 • PID = 0x0073 Default Strings: • Manufacturer [1] = "Freescale Semiconductor Inc." • Product [2] = "Kinetis Bootloader" 13.4.4.3 Endpoints The HID peripheral uses 3 endpoints: • Control (0) • Interrupt IN (1) •...
Page 323: Get/Setproperty Command Properties
The size in bytes of one sector of program flash. This is the minimum erase size. FlashBlockCount Number of blocks in the flash array. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 324: Property Definitions
0 - FAC not supported 1 - FAC supported FlashAcessSegmentSiz The size in bytes of 1 segment size FlashAcessSegmentCo FAC segment count 13.5.1 Property Definitions Get/Set property definitions are provided in this section. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 325 0x01. To get the bit mask for a given command, use this expression: mask = 1 << (tag - 1) Table 13-46. Command bits: [31:11] [10] Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 326: Kinetis Flashloader Status Error Codes
Attempt to abort a transfer when no transfer was in progress. kStatus_ UnknownCommand 10000 The requested command value is undefined. kStatus_ SecurityViolation 10001 Command is disallowed because flash security is enabled. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 327 Memory range conflicts with a protected region. kStatus_UnknownProperty 10300 The requested property value is undefined. kStatus_ReadOnlyProperty 10301 The requested property value cannot be written. kStatus_InvalidPropertyValue 10302 The specified property value is invalid. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 328 Kinetis Flashloader Status Error Codes K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 329: Reset Control Module (Rcm)
System Reset Status Register 1 (RCM_SRS1) 14.2.2/331 4007_F004 Reset Pin Filter Control register (RCM_RPFC) 14.2.3/333 4007_F005 Reset Pin Filter Width register (RCM_RPFW) 14.2.4/334 Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 330: System Reset Status Register 0 (Rcm_Srs0)
Indicates a reset has been caused by an active-low level on the external RESET pin. Reset not caused by external reset pin Reset caused by external reset pin Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 331: System Reset Status Register 1 (Rcm_Srs1)
The reset state of these bits depends on what caused the MCU to reset. NOTE The reset value of this register depends on the reset source: • POR (including LVD) — 0x00 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 332 Indicates a reset has been caused by the ARM core indication of a LOCKUP event. Reset not caused by core LOCKUP event Reset caused by core LOCKUP event Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 333: Reset Pin Filter Control Register (Rcm_Rpfc)
Selects how the reset pin filter is enabled in run and wait modes. All filtering disabled Bus clock filter enabled for normal operation LPO clock filter enabled for normal operation Reserved K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 334: Reset Pin Filter Width Register (Rcm_Rpfw)
Bus clock filter count is 22 10110 Bus clock filter count is 23 10111 Bus clock filter count is 24 11000 Bus clock filter count is 25 Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 335: Mode Register (Rcm_Mr)
Reflects the state of the EZP_MS pin during the last Chip Reset Pin deasserted (logic 1) Pin asserted (logic 0) This field is reserved. Reserved This read-only field is reserved and always has the value 0. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 336: Sticky System Reset Status Register 0 (Rcm_Ssrs0)
Reset not caused by a loss of lock in the PLL Reset caused by a loss of lock in the PLL Sticky Loss-of-Clock Reset SLOC Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 337: Sticky System Reset Status Register 1 (Rcm_Ssrs1)
This field is reserved. Reserved This read-only field is reserved and always has the value 0. Sticky Stop Mode Acknowledge Error Reset SSACKERR Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 338 Sticky JTAG Generated Reset SJTAG Indicates a reset has been caused by JTAG selection of certain IR codes: EZPORT, EXTEST, HIGHZ, and CLAMP. Reset not caused by JTAG Reset caused by JTAG K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 339: System Mode Controller (Smc)
The WFI or WFE instruction is used to invoke Sleep and Deep Sleep modes. Run, Wait, and Stop are the common terms used for the primary operating modes of Freescale microcontrollers. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 340 The core, system, bus, and flash clock maximum frequencies are restricted in this mode. See the Power Management chapter for details about the maximum allowable frequencies. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 341: Memory Map And Register Descriptions
For more information about the types of reset on this chip, refer to the Reset section details. NOTE The SMC registers can be written only in supervisor mode. Write accesses in user mode are blocked and will result in a bus error. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 342: Power Mode Protection Register (Smc_Pmprot)
Chip Reset not VLLS. See the Reset section details for more information. Address: 4007_E000h base + 0h offset = 4007_E000h Read AHSRUN AVLP ALLS AVLLS Write Reset K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 343: Power Mode Control Register (Smc_Pmctrl)
(PMPROT) register. NOTE This register is reset on Chip POR not VLLS and by reset types that trigger Chip POR not VLLS. It is unaffected by reset types K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 344 NOTE: When set to STOP, the PSTOPO bits in the STOPCTRL register can be used to select a Partial Stop mode if desired. Normal Stop (STOP) Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 345: Stop Control Register (Smc_Stopctrl)
PSTOP2 - Partial Stop with system clock disabled and bus clock enabled Reserved POR Power Option PORPO This bit controls whether the POR detect circuit is enabled in VLLS0 mode. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 346: Power Mode Status Register (Smc_Pmstat)
Address: 4007_E000h base + 3h offset = 4007_E003h Read PMSTAT Write Reset SMC_PMSTAT field descriptions Field Description 7–0 Power Mode Status PMSTAT NOTE: When debug is enabled, the PMSTAT will not update to STOP or VLPS K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 347: Functional Description
15.4.1 Power mode transitions The following figure shows the power mode state transitions available on the chip. Any reset always brings the MCU back to the normal RUN state. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 348 WAIT Sleep-now or sleep-on-exit modes entered with SLEEPDEEP clear, controlled in System Control Register in ARM core. See note. WAIT Interrupt or Reset Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 349 VLLSx PMPROT[AVLLS]=1, PMCTRL[STOPM]=100, STOPCTRL[VLLSM]=x (VLLSx), Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 350: Power Mode Entry/Exit Sequencing
WFI instruction. After the instruction is executed, the following sequence occurs: 1. The CPU clock is gated off immediately. 2. Requests are made to all non-CPU bus masters to enter Stop mode. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 351 For wait modes (WAIT and VLPW), the CPU clock is gated off while all other clocking continues, as in RUN and VLPR mode operation. Some modules that support stop-in- wait functionality have their clocks disabled in these configurations. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 352: Run Modes
• The MCG must be configured in a mode which is supported during VLPR. See the Power Management details for information about these MCG modes. • All clock monitors in the MCG must be disabled. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 353 RUN mode. • Stop mode entry is not supported from HSRUN. • Modifications to clock gating control bits are prohibited. • Flash programming/erasing is not allowed. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 354: Wait Modes
SIM. VLPR mode restrictions also apply to VLPW. When an interrupt from VLPW occurs, the device returns to VLPR mode to execute the interrupt service routine. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 355: Stop Modes
STOP mode is entered via the sleep-now or sleep-on-exit with the SLEEPDEEP bit set in the System Control Register in the ARM core. The MCG module can be configured to leave the reference clocks running. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 356 In LLS, the on-chip voltage regulator is in stop regulation. Most of the peripherals are put in a state-retention mode that does not allow them to operate while in LLS. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 357 Before entering VLLS mode, the user should configure the Low-Leakage Wake-up (LLWU) module to enable the desired wakeup sources. The available wake-up sources in VLLS are detailed in the chip configuration details for this device. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 358: Debug In Low Power Modes
Reset Controller logic to hold the system in reset after the next recovery from a VLLS mode. This bit allows the debugger time to reinitialize the debug module before the debug session continues. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 359 The VLLDBGACK bit is cleared by the debugger (or can be left set as is) or clears automatically due to the reset generated as part of the next VLLS recovery. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 360 Functional description K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 361: Power Management Controller (Pmc)
(V ) or low (V ). The trip voltage is selected by LVDH LVDL LVDSC1[LVDV]. The LVD is disabled upon entering VLPx, LLS, and VLLSx modes. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 362: Lvd Reset Operation
LVD voltage. The LVW also has an interrupt, which is enabled by setting LVDSC2[LVWIE]. If enabled, an LVW interrupt request occurs when LVDSC2[LVWF] is set. LVDSC2[LVWF] is cleared by writing 1 to LVDSC2[LVWACK]. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 363: I/O Retention
Width Section/ address Register name Access Reset value (in bits) page (hex) Low Voltage Detect Status And Control 1 register 4007_D000 16.5.1/364 (PMC_LVDSC1) Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 364: Low Voltage Detect Status And Control 1 Register (Pmc_Lvdsc1)
PMC_LVDSC1 field descriptions Field Description Low-Voltage Detect Flag LVDF This read-only status field indicates a low-voltage detect event. Low-voltage event not detected Low-voltage event detected Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 365: Low Voltage Detect Status And Control 2 Register (Pmc_Lvdsc2)
LVWV is reset solely on a POR Only event. The other fields of the register are reset on Chip Reset Not VLLS. For more information about these reset types, refer to the Reset section details. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 366: Regulator Status And Control Register (Pmc_Regsc)
CMP and ADC. The internal regulator provides a status bit (REGONS) indicating the regulator is in run regulation. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 367 Regulator is in stop regulation or in transition to/from it Regulator is in run regulation This field is reserved. Reserved NOTE: This reserved bit must remain cleared (set to 0). Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 368 Memory map and register descriptions PMC_REGSC field descriptions (continued) Field Description Bandgap Buffer Enable BGBE Enables the bandgap buffer. Bandgap buffer not enabled Bandgap buffer enabled K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 369: Low-Leakage Wakeup Unit (Llwu)
LLS or VLLS. See the chip configuration information for wakeup input sources for this device. • External pin wake-up inputs, each of which is programmable as falling-edge, rising- edge, or any change K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 370: Modes Of Operation
When the wake-up pin filters are enabled, filter operation begins immediately. If a low leakage mode is entered within five LPO clock cycles of an active edge, the edge event will be detected by the LLWU. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 371: Block Diagram
Pin filter 2 Synchronizer detect reset flow WUPE15 FILT2[FILTSEL] LLWU_P15 wakeup occurred Edge detect External pin sources LLWU_P0 wakeup occurred Edge detect WUPE0 Figure 17-1. LLWU block diagram K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 372: Llwu Signal Descriptions
LLWU registers are unaffected by reset types that do not trigger Chip Reset not VLLS. For more information about the types of reset on this chip, refer to the Introduction details. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 373: Llwu Pin Enable 1 Register (Llwu_Pe1)
External input pin enabled with any change detection 5–4 Wakeup Pin Enable For LLWU_P2 WUPE2 Enables and configures the edge detection for the wakeup pin. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 374: Llwu Pin Enable 2 Register (Llwu_Pe2)
Enables and configures the edge detection for the wakeup pin. External input pin disabled as wakeup input External input pin enabled with rising edge detection Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 375: Llwu Pin Enable 3 Register (Llwu_Pe3)
Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 2h offset = 4007_C002h Read WUPE11 WUPE10 WUPE9 WUPE8 Write Reset K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 376: Llwu Pin Enable 4 Register (Llwu_Pe4)
This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 377: Llwu Module Enable Register (Llwu_Me)
LLWU_ME contains the bits to enable the internal module flag as a wakeup input source for inputs MWUF7–MWUF0. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 378 Enables an internal module as a wakeup source input. Internal module flag not used as wakeup source Internal module flag used as wakeup source Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 379: Llwu Flag 1 Register (Llwu_F1)
Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF6. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 380 Indicates that an enabled external wake-up pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF0. LLWU_P0 input was not a wakeup source LLWU_P0 input was a wakeup source K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 381: Llwu Flag 2 Register (Llwu_F2)
Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF13. LLWU_P13 input was not a wakeup source LLWU_P13 input was a wakeup source Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 382: Llwu Flag 3 Register (Llwu_F3)
CMP module, the flag from the associated peripheral is accessible as the MWUFx bit. The flag will need to be cleared in the peripheral instead of writing a 1 to the MWUFx bit. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 383 Module 3 input was not a wakeup source Module 3 input was a wakeup source Wakeup flag For module 2 MWUF2 Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 384: Llwu Pin Filter 1 Register (Llwu_Filt1)
Indicates that the filtered external wakeup pin, selected by FILTSEL, was a source of exiting a low-leakage power mode. To clear the flag write a one to FILTF. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 385: Llwu Pin Filter 2 Register (Llwu_Filt2)
Indicates that the filtered external wakeup pin, selected by FILTSEL, was a source of exiting a low-leakage power mode. To clear the flag write a one to FILTF. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 386: Functional Description
5 cycles of delay before the detect circuit alerts the system to the wakeup or reset event when the filter function is enabled. Two wakeup detect filters are available for selected external pins. Glitch filtering is not provided on the internal modules. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 387: Lls Mode
LLWU flag from being falsely set when PMC_REGSC[ACKISO] is cleared. The signal selected as a wake-up source pin must be a digital pin, as selected in the pin mux control. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 388 Functional description K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 389: Miscellaneous Control Module (Mcm)
Crossbar Switch (AXBS) Slave Configuration E008_0008 000Fh 18.2.1/390 (MCM_PLASC) Crossbar Switch (AXBS) Master Configuration E008_000A 0017h 18.2.2/390 (MCM_PLAMC) E008_000C Crossbar Switch (AXBS) Control Register (MCM_PLACR) 0000_0000h 18.2.3/391 Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 390: Crossbar Switch (Axbs) Slave Configuration (Mcm_Plasc)
PLAMC is a 16-bit read-only register identifying the presence/absence of bus master connections to the device's crossbar switch. Address: E008_0000h base + Ah offset = E008_000Ah Read Write Reset K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 391: Crossbar Switch (Axbs) Control Register (Mcm_Placr)
This read-only field is reserved and always has the value 0. Arbitration select Fixed-priority arbitration for the crossbar masters Round-robin arbitration for the crossbar masters 8–0 This field is reserved. Reserved K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 392: Interrupt Status And Control Register (Mcm_Iscr)
Address: E008_0000h base + 10h offset = E008_0010h Reserved Reset Reset MCM_ISCR field descriptions Field Description FPU input denormal interrupt enable FIDCE Disable interrupt Enable interrupt Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 393 FPU. Once set, this bit remains set until software clears the FPSCR[UFC] bit. No interrupt Interrupt occurred FPU overflow interrupt status FOFC Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 394 FPU. Once set, this bit remains set until software clears the FPSCR[IOC] bit. No interrupt Interrupt occurred 7–0 This field is reserved. Reserved This read-only field is reserved and always has the value 0. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 395: Compute Operation Control Register (Mcm_Cpo)
Compute operation entry has completed or compute operation exit has not completed. Compute Operation request CPOREQ This bit is auto-cleared by vector fetching if CPOWOI = 1. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 396: Functional Description
To determine the exact source of the interrupt qualify the interrupt status flags with the corresponding interrupt enable bits. 1. Form MCM_ISCR[31:16] && MCM_ISCR[15:0] 2. Search the result for asserted flags, which indicate the exact interrupt sources K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 397: Crossbar Switch Lite (Axbs-Lite)
• Allows concurrent accesses from different masters to different slaves • 32-bit data bus • Operation at a 1-to-1 clock frequency with the bus masters • Programmable configuration for fixed-priority or round-robin slave port arbitration K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 398: Memory Map / Register Definition
The master can also lose control of the slave port if another higher-priority master makes a request to the slave port. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 399: Arbitration
The following table describes possible scenarios based on the requesting master port: K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 400: Initialization/Application Information
(compared to fixed priority) as the fixed master priority does not affect the master selection. 19.4 Initialization/application information No initialization is required for the crossbar switch. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 401 Chapter 19 Crossbar Switch Lite (AXBS-Lite) See the AXBS section of the configuration chapter for the reset state of the arbitration scheme. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 402 Initialization/application information K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 403: Peripheral Bridge (Aips-Lite)
The peripheral bridge performs a bus protocol conversion of the master transactions and generates the following as inputs to the peripherals: • Module enables • Module addresses K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 404: Functional Description
All accesses to the peripheral slots must be sized less than or equal to the designated peripheral slot size. If an access is attempted that is larger than the targeted port, an error response is generated. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 405: Direct Memory Access Multiplexer (Dmamux)
21.1.1 Overview The Direct Memory Access Multiplexer (DMAMUX) routes DMA sources, called slots, to any of the 16 DMA channels. This process is illustrated in the following figure. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 406: Features
• Each channel router can be assigned to one of the possible peripheral DMA slots or to one of the always-on slots. 21.1.3 Modes of operation The following operating modes are available: • Disabled mode K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 407: External Signal Description
Channel Configuration register (DMAMUX_CHCFG5) 21.3.1/408 4002_1006 Channel Configuration register (DMAMUX_CHCFG6) 21.3.1/408 4002_1007 Channel Configuration register (DMAMUX_CHCFG7) 21.3.1/408 4002_1008 Channel Configuration register (DMAMUX_CHCFG8) 21.3.1/408 Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 408: Channel Configuration Register (Dmamux_Chcfgn)
DMA channel. DMA channel is enabled DMA Channel Trigger Enable TRIG Enables the periodic trigger capability for the triggered DMA channel. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 409: Functional Description
Because of the dynamic nature of the system (due to DMA channel priorities, bus arbitration, interrupt service routine lengths, etc.), the number of clock cycles between a trigger and the actual DMA transfer cannot be guaranteed. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 410 This means that if a trigger is seen, but the peripheral is not requesting a transfer, then that trigger will be ignored. This situation is illustrated in the following figure. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 411: Dma Channels With No Triggering Capability
21.4.2 DMA channels with no triggering capability The other channels of the DMAMUX provide the normal routing functionality as described in Modes of operation. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 412: Always-Enabled Dma Sources
DMA registers after every minor loop. For this option, the DMA channel must be disabled in the DMA channel MUX. • Use an always-enabled DMA source. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 413: Initialization/Application Information
DMA channels that have triggering capability. To configure source #5 transmit for use with DMA channel 1, with periodic triggering capability: 1. Write 0x00 to CHCFG1 (base address + 0x01). K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 414 *CHCFG10= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000A); volatile unsigned char *CHCFG11= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000B); volatile unsigned char *CHCFG12= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000C); volatile unsigned char *CHCFG13= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000D); K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 415 *CHCFG12= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000C); volatile unsigned char *CHCFG13= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000D); volatile unsigned char *CHCFG14= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000E); volatile unsigned char *CHCFG15= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000F); K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 416 Initialization/application information In File main.c: #include "registers.h" *CHCFG8 = 0x00; *CHCFG8 = 0x87; K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 417: Enhanced Direct Memory Access (Edma)
• Local memory containing transfer control descriptors for each of the 16 channels 22.1.1 eDMA system block diagram Figure 22-1 illustrates the components of the eDMA system, including the eDMA module ("engine"). K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 418: Block Parts
22.1.2 Block parts The eDMA module is partitioned into two major modules: the eDMA engine and the transfer-control descriptor local memory. The eDMA engine is further partitioned into four submodules: K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 419 As noted earlier, in the event of simultaneous accesses, the eDMA engine is given priority and the peripheral transaction is stalled. Memory array TCD storage for each channel's transfer profile. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 420: Features
• Optional error terminations per channel and logically summed together to form one error interrupt to the interrupt controller • Optional support for scatter/gather DMA processing • Support for complex data structures K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 421: Modes Of Operation
The channel descriptors are stored in the local memory in sequential order: channel 0, channel 1, ... channel 15. Each TCDn definition is presented as 11 registers of 16 or 32 bits. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 422: Tcd Initialization
Memory map/register definition 22.3.2 TCD initialization Prior to activating a channel, you must initialize its TCD with the appropriate transfer profile. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 423: Tcd Structure
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 The fields implemented in Word 2 depend on whether DMA_CR[EMLM] is 0 or 1. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 424: Reserved Memory And Bit Fields
Channel n Priority Register (DMA_DCHPRI3) See section 22.3.17/461 4000_8101 Channel n Priority Register (DMA_DCHPRI2) See section 22.3.17/461 4000_8102 Channel n Priority Register (DMA_DCHPRI1) See section 22.3.17/461 Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 425 4000_9020 TCD Source Address (DMA_TCD1_SADDR) Undefined 22.3.18/462 4000_9024 TCD Signed Source Address Offset (DMA_TCD1_SOFF) Undefined 22.3.19/462 4000_9026 TCD Transfer Attributes (DMA_TCD1_ATTR) Undefined 22.3.20/463 Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 426 4000_9056 DMA_TCD2_CITER_ELINKNO Undefined 22.3.28/470 TCD Last Destination Address Adjustment/Scatter Gather 4000_9058 Undefined 22.3.29/471 Address (DMA_TCD2_DLASTSGA) 4000_905C TCD Control and Status (DMA_TCD2_CSR) Undefined 22.3.30/472 Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 427 TCD Signed Minor Loop Offset (Minor Loop and Offset 4000_9088 Undefined 22.3.23/466 Enabled) (DMA_TCD4_NBYTES_MLOFFYES) TCD Last Source Address Adjustment 4000_908C Undefined 22.3.24/467 (DMA_TCD4_SLAST) 4000_9090 TCD Destination Address (DMA_TCD4_DADDR) Undefined 22.3.25/468 Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 428 4000_90C4 TCD Signed Source Address Offset (DMA_TCD6_SOFF) Undefined 22.3.19/462 4000_90C6 TCD Transfer Attributes (DMA_TCD6_ATTR) Undefined 22.3.20/463 TCD Minor Byte Count (Minor Loop Disabled) 4000_90C8 Undefined 22.3.21/464 (DMA_TCD6_NBYTES_MLNO) Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 429 4000_90FC TCD Control and Status (DMA_TCD7_CSR) Undefined 22.3.30/472 TCD Beginning Minor Loop Link, Major Loop Count 4000_90FE (Channel Linking Enabled) Undefined 22.3.31/474 (DMA_TCD7_BITER_ELINKYES) Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 430 TCD Signed Destination Address Offset 4000_9134 Undefined 22.3.26/468 (DMA_TCD9_DOFF) TCD Current Minor Loop Link, Major Loop Count (Channel 4000_9136 Undefined 22.3.27/469 Linking Enabled) (DMA_TCD9_CITER_ELINKYES) Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 431 TCD Minor Byte Count (Minor Loop Disabled) 4000_9168 Undefined 22.3.21/464 (DMA_TCD11_NBYTES_MLNO) TCD Signed Minor Loop Offset (Minor Loop Enabled and 4000_9168 Undefined 22.3.22/465 Offset Disabled) (DMA_TCD11_NBYTES_MLOFFNO) Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 432 4000_919C TCD Control and Status (DMA_TCD12_CSR) Undefined 22.3.30/472 TCD Beginning Minor Loop Link, Major Loop Count 4000_919E (Channel Linking Enabled) Undefined 22.3.31/474 (DMA_TCD12_BITER_ELINKYES) Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 433 TCD Last Source Address Adjustment 4000_91CC Undefined 22.3.24/467 (DMA_TCD14_SLAST) 4000_91D0 TCD Destination Address (DMA_TCD14_DADDR) Undefined 22.3.25/468 TCD Signed Destination Address Offset 4000_91D4 Undefined 22.3.26/468 (DMA_TCD14_DOFF) Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 434: Control Register (Dma_Cr)
TCD Beginning Minor Loop Link, Major Loop Count 4000_91FE (Channel Linking Disabled) Undefined 22.3.32/475 (DMA_TCD15_BITER_ELINKNO) 22.3.1 Control Register (DMA_CR) The CR defines the basic operating configuration of the DMA. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 435 When minor loop mapping is disabled (EMLM is 0), all 32 bits of TCDn word2 are assigned to the NBYTES field. Address: 4000_8000h base + 0h offset = 4000_8000h Reset K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 436 Halt On Error Normal operation Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 437: Error Status Register (Dma_Es)
Address: 4000_8000h base + 4h offset = 4000_8004h Reset ERRCHN Reset DMA_ES field descriptions Field Description Logical OR of all ERR status bits Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 438 • TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or • TCDn_CITER[CITER] is equal to zero, or • TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 439: Enable Request Register (Dma_Erq)
Address: 4000_8000h base + Ch offset = 4000_800Ch Reset ERQ9 ERQ8 ERQ7 ERQ6 ERQ5 ERQ4 ERQ3 ERQ2 ERQ1 ERQ0 Reset K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 440 The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled Enable DMA Request 4 ERQ4 Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 441: Enable Error Interrupt Register (Dma_Eei)
The DMA error indicator and the error interrupt enable flag must be asserted before an error interrupt request for a given channel is asserted to the interrupt controller. Address: 4000_8000h base + 14h offset = 4000_8014h Reset K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 442 The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error interrupt request Enable Error Interrupt 6 EEI6 Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 443: Clear Enable Error Interrupt Register (Dma_Ceei)
If the NOP bit is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. Address: 4000_8000h base + 18h offset = 4000_8018h Read Write CAEE CEEI Reset K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 444: Set Enable Error Interrupt Register (Dma_Seei)
Sets All Enable Error Interrupts SAEE Set only the EEI bit specified in the SEEI field. Sets all bits in EEI 5–4 This field is reserved. Reserved Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 445: Clear Enable Request Register (Dma_Cerq)
Clear only the ERQ bit specified in the CERQ field Clear all bits in ERQ 5–4 This field is reserved. Reserved 3–0 Clear Enable Request CERQ Clears the corresponding bit in ERQ. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 446: Set Enable Request Register (Dma_Serq)
Set only the ERQ bit specified in the SERQ field Set all bits in ERQ 5–4 This field is reserved. Reserved 3–0 Set Enable Request SERQ Sets the corresponding bit in ERQ. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 447: Clear Done Status Bit Register (Dma_Cdne)
Clears only the TCDn_CSR[DONE] bit specified in the CDNE field Clears all bits in TCDn_CSR[DONE] 5–4 This field is reserved. Reserved 3–0 Clear DONE Bit CDNE Clears the corresponding bit in TCDn_CSR[DONE] K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 448: Set Start Bit Register (Dma_Ssrt)
Set only the TCDn_CSR[START] bit specified in the SSRT field Set all bits in TCDn_CSR[START] 5–4 This field is reserved. Reserved 3–0 Set START Bit SSRT Sets the corresponding bit in TCDn_CSR[START] K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 449: Clear Error Register (Dma_Cerr)
Clear only the ERR bit specified in the CERR field Clear all bits in ERR 5–4 This field is reserved. Reserved 3–0 Clear Error Indicator CERR Clears the corresponding bit in ERR K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 450: Clear Interrupt Request Register (Dma_Cint)
Clear only the INT bit specified in the CINT field Clear all bits in INT 5–4 This field is reserved. Reserved 3–0 Clear Interrupt Request CINT Clears the corresponding bit in INT K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 451: Interrupt Request Register (Dma_Int)
Reset DMA_INT field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 452 The interrupt request for corresponding channel is active Interrupt Request 4 INT4 The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 453: Error Register (Dma_Err)
A zero in any bit position has no affect on the corresponding channel’s current error status. The CERR is provided so the error indicator for a single channel can easily be cleared. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 454 An error in this channel has occurred Error In Channel 10 ERR10 An error in this channel has not occurred An error in this channel has occurred Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 455 An error in this channel has not occurred An error in this channel has occurred Error In Channel 0 ERR0 An error in this channel has not occurred An error in this channel has occurred K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 456: Hardware Request Status Register (Dma_Hrs)
31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Hardware Request Status Channel 15 HRS15 Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 457 The HRS bit for its respective channel remains asserted for the period when a Hardware Request is Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically cleared by hardware. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 458 A hardware service request for channel 3 is not present A hardware service request for channel 3 is present Hardware Request Status Channel 2 HRS2 Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 459: Enable Asynchronous Request In Stop Register (Dma_Ears)
Reset DMA_EARS field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 460 Enable asynchronous DMA request in stop mode for channel 4 EDREQ_4 Disable asynchronous DMA request for channel 4. Enable asynchronous DMA request for channel 4. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 461: Channel N Priority Register (Dma_Dchprin)
Channel n cannot be suspended by a higher priority channel’s service request. Channel n can be temporarily suspended by the service request of a higher priority channel. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 462: Tcd Source Address (Dma_Tcdn_Saddr)
22.3.19 TCD Signed Source Address Offset (DMA_TCDn_SOFF) Address: 4000_8000h base + 1004h offset + (32d × i), where i=0d to 15d Read SOFF Write Reset * Notes: • x = Undefined at reset. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 463: Tcd Transfer Attributes (Dma_Tcdn_Attr)
8-bit 16-bit 32-bit Reserved 16-byte 32-byte burst (4 beats of 64 bits) Reserved Reserved 7–3 Destination Address Modulo DMOD See the SMOD definition Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 464: Tcd Minor Byte Count (Minor Loop Disabled) (Dma_Tcdn_Nbytes_Mlno)
TCD memory. If the major iteration count is completed, additional processing is performed. NOTE: An NBYTES value of 0x0000_0000 is interpreted as a 4 GB transfer. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 465: Tcd Signed Minor Loop Offset (Minor Loop Enabled And Offset Disabled)
The minor loop offset is applied to the SADDR Destination Minor Loop Offset enable DMLOE Selects whether the minor loop offset is applied to the destination address upon minor loop completion. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 466: Tcd Signed Minor Loop Offset (Minor Loop And Offset Enabled)
TCD_NBYTES_MLOFFNO register description. If minor loop mapping is disabled, then refer to the TCD_NBYTES_MLNO register description. Address: 4000_8000h base + 1008h offset + (32d × i), where i=0d to 15d MLOFF Reset MLOFF NBYTES Reset * Notes: K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 467: Tcd Last Source Address Adjustment (Dma_Tcdn_Slast)
This register uses two's complement notation; the overflow bit is discarded. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 468: Tcd Destination Address (Dma_Tcdn_Daddr)
DMA_TCDn_DOFF field descriptions Field Description 15–0 Destination Address Signed Offset DOFF Sign-extended offset applied to the current destination address to form the next-state value as each destination write is completed. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 469: Tcd Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (Dma_Tcdn_Citer_Elinkyes)
CITER field from the Beginning Iteration Count (BITER) field. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 470: Tcd Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
It is decremented each time the minor loop is completed and updated in the transfer control descriptor memory. After the major iteration count is exhausted, the channel performs a number of operations, for Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 471: Tcd Last Destination Address Adjustment/Scatter Gather Address (Dma_Tcdn_Dlastsga)
This channel reload is performed as the major iteration count completes. The scatter/gather address must be 0-modulo-32-byte, otherwise a configuration error is reported. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 472: Tcd Control And Status (Dma_Tcdn_Csr)
The software clears it, or the hardware when the channel is activated. NOTE: This bit must be cleared to write the MAJORELINK or ESG bits. Channel Active ACTIVE Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 473 If this flag is set, the channel generates an interrupt request by setting the appropriate bit in the INT when the current major iteration count reaches zero. The end-of-major loop interrupt is disabled. The end-of-major loop interrupt is enabled. Channel Start START Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 474: Tcd Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
If channel-to-channel linking is enabled (ELINK = 1), then after the minor loop is exhausted, the eDMA engine initiates a channel service request at the channel defined by this field by setting that channel’s TCDn_CSR[START] bit. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 475: Tcd Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
As the major iteration count is exhausted, the contents of this field are reloaded into the CITER field. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 476: Functional Description
22.4.1 eDMA basic data flow The basic flow of a data transfer can be partitioned into three segments. As shown in the following diagram, the first segment involves the channel activation: K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 477 The following diagram illustrates the second part of the basic data flow: K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 478 (if scatter/ gather is enabled). The updates to the TCD memory and the assertion of an interrupt request are shown in the following diagram. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 479: Fault Reporting And Handling
Each of these possible causes are detailed below: • The addresses and offsets must be aligned on 0-modulo-transfer-size boundaries. • The minor loop byte count must be a multiple of the source and destination transfer sizes. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 480 DMA_ES[ERRCHN] and ECX and VLD are set. In addition, an error interrupt may be generated if enabled. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 481: Channel Preemption
22.4.4 Performance This section addresses the performance of the eDMA module, focusing on two separate metrics: K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 482 32-bit transfer sizes are used. In all cases, the transfer rate includes the time to read the source plus the time to write the destination. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 483 The TCDn word 7 is read and checked for channel linking or scatter/gather requests. The appropriate fields in the first part of the TCDn are written back into the local memory. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 484 Channel startup (4 cycles) read_ws Wait states seen during the system bus read data phase write_ws Wait states seen during the system bus write data phase exit Channel shutdown (3 cycles) K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 485 This allows the link channel or the scatter/gather channel to be eligible and considered in the arbitration pool for next channel selection. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 486: Initialization/Application Information
If the major loop is exhausted, further post processing executes, such as interrupts, major loop channel linking, and scatter/gather operations, if enabled. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 487 (CITER) DMA request DMA request DMA request Figure 22-293. Example of multiple loop iterations The following figure lists the memory array terms and how the TCD settings interrelate. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 488: Programming Errors
The hardware service request handshake signals, error interrupts, and error reporting is associated with the selected channel. 22.5.3 Arbitration mode considerations This section discusses arbitration considerations for the eDMA. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 489: Performing Dma Transfers
TCDn_CSR[INT_MAJ] = 1 TCDn_CSR[START] = 1 (Should be written last after all other fields have been initialized) All other TCDn fields = 0 This generates the following event sequence: K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 490 The eDMA is programmed for two iterations of the major loop transferring 16 bytes per iteration. After the channel's hardware requests are enabled in the ERQ register, the slave device initiates channel service requests. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 491 9. Second hardware, that is, eDMA peripheral, requests channel service. 10. The channel is selected by arbitration for servicing. 11. eDMA engine writes: TCDn_CSR[DONE] = 0, TCDn_CSR[START] = 0, TCDn_CSR[ACTIVE] = 1. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 492 All upper address bits remain the same as in the original value. A setting of 0 for this field disables the modulo feature. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 493: Monitoring Transfer Descriptor Status
START ACTIVE DONE Channel service request via software Channel is executing Channel has completed the minor loop and is idle Channel has completed the major loop and is idle K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 494 Channel priorities are treated as equal, that is, constantly rotating, when Round-Robin Arbitration mode is selected. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 495: Channel Linking
TCDn_CITER[CITER] field uses a 15-bit vector to form the current iteration count. The bits associated with the TCDn_CITER[LINKCH] field are concatenated onto the CITER value to increase the range of the CITER. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 496: Dynamic Programming
Dynamic channel linking is the process of setting the TCD.major.e_link bit during channel execution. This bit is read from the TCD local memory at the end of channel execution, thus allowing the user to enable the feature during channel execution. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 497 The TCD.e_sg would be set in the programmer’s model, but it would be unclear whether the actual scatter/gather request was honored before the channel retired. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 498 If e_sg = 1b, the dynamic link attempt was successful. If e_sg = 0b and the major.linkch (ID) did not change, the attempted dynamic link did not succeed (the channel was already retiring). K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 499 (the channel was already retiring). If e_sg = 0b and the dlast_sga changed, the dynamic link attempt was successful (the new TCD’s e_sg value cleared the e_sg bit). K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 500 Initialization/application information K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 501: External Watchdog Monitor (Ewm)
23.1.1 Features Features of EWM module include: • Independent LPO clock source • Programmable time-out period specified in terms of number of EWM LPO clock cycles. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 502: Modes Of Operation
15 (EWM_service_time) peripheral bus clocks after exiting from stop mode. User must mask all interrupts prior to executing EWM service instructions. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 503: Block Diagram
EWM enable Counter >Compare High EWM Out Counter < Compare Low Logic EWM_out ((EWM_in ^ assert_in) || ~EWM_in_enable) Compare High > Counter > Compare Low Figure 23-1. EWM Block Diagram K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 504: Ewm Signal Descriptions
INEN, ASSIN and EWMEN bits can be written once after a CPU reset. Modifying these bits more than once, generates a bus transfer error. Address: 4006_1000h base + 0h offset = 4006_1000h Read INTEN INEN ASSIN EWMEN Write Reset K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 505: Service Register (Ewm_Serv)
23.3.3 Compare Low Register (EWM_CMPL) The CMPL register is reset to zero after a CPU reset. This provides no minimum time for the CPU to service the EWM counter. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 506: Compare High Register (Ewm_Cmph)
7–0 To prevent runaway code from changing this field, software should write to this field after a CPU reset COMPAREH even if the (default) maximum service time is required. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 507: Clock Prescaler Register (Ewm_Clkprescaler)
The EWM_out signal remains deasserted when the EWM is being regularly serviced by the CPU within the programmable service window, indicating that the application code is executed as expected. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 508: The Ewm_In Signal
(setting the CTRL[INEN] bit), the EWM_in signal must be in the deasserted state prior to the CPU servicing the EWM. This ensures that the EWM_out stays in the deasserted state; otherwise, the EWM_out pin is asserted. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 509: Ewm Counter
EWM Service Register. The CPU must access the EWM service register with correct write of unique data within the windowed time frame as determined by the CMPL and CMPH registers. Therefore, three possible conditions can occur: K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 510: Ewm Interrupt
CLKPRESCALER[CLK_DIV]. This divided clock is used to run the EWM counter. NOTE The divided clock used to run the EWM counter must be no more than half the frequency of the bus clock. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 511: Watchdog Timer (Wdog)
• External system clock • Unlock sequence for allowing updates to write-once WDOG control/configuration bits. • All WDOG control/configuration bits are writable once only within 256 bus clock cycles of being unlocked. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 512 • Count of WDOG resets as they occur. • Configurable interrupt on time-out to provide debug breadcrumbs. This is followed by a reset after 256 bus clock cycles. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 513: Functional Overview
CPU clock stopping or a run-away condition in code execution. In its simplest form, the watchdog timer runs continuously off a clock source and expects K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 514: Unlocking And Updating The Watchdog
After the update window closes, the watchdog timer restarts and the watchdog functions according to the new configuration. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 515: Watchdog Configuration Time (Wct)
2xWCT + 20 bus clock cycles. Therefore, it must be ensured that the time-out value for the watchdog is always greater than 2xWCT time + 20 bus clock cycles. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 516: Refreshing The Watchdog
In this mode, the watchdog timer cannot be refreshed–there is no requirement to do so while the timer is disabled. However, the watchdog still generates a reset, or interrupt-then-reset if enabled, on a non- K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 517: Debug Modes Of Operation
After it is set, this test-disable bit can only be cleared by a reset. These two tests achieve the overall aim of testing the counter functioning and the compare and reset logic. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 518: Quick Test
The following figure explains the splitting concept: K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 519: Backup Reset Generator
Two successive timer time-outs without an intervening system reset result in the backup reset generator routing out the time-out signal as a reset to the system. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 520: Generated Resets And Interrupts
Also, jobs such as counting the number of watchdog resets would not be done. 24.7 Memory map and register definition This section consists of the memory map and register descriptions. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 521: Watchdog Status And Control Register High (Wdog_Stctrlh)
WDOG functional test mode is disabled permanently until reset. 13–12 This 2-bit field selects the byte to be tested when the watchdog is in the byte test mode. BYTESEL[1:0] Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 522 Selects clock source for the WDOG timer and other internal timing operations. CLKSRC WDOG clock sourced from LPO . WDOG clock sourced from alternate clock source. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 523: Watchdog Status And Control Register Low (Wdog_Stctrll)
Field Description 15–0 Defines the upper 16 bits of the 32-bit time-out value for the watchdog timer. It is defined in terms of cycles TOVALHIGH of the watchdog clock. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 524: Watchdog Time-Out Value Register Low (Wdog_Tovall)
A refresh outside this window resets the system or if IRQRSTEN is set, it interrupts and then resets the system. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 525: Watchdog Window Register Low (Wdog_Winl)
20 bus cycles, resets the system, or if IRQRSTEN is set, it interrupts and then resets the system. 24.7.8 Watchdog Unlock register (WDOG_UNLOCK) Address: 4005_2000h base + Eh offset = 4005_200Eh Read WDOGUNLOCK Write Reset K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 526: Watchdog Timer Output Register High (Wdog_Tmrouth)
Address: 4005_2000h base + 12h offset = 4005_2012h Read TIMEROUTLOW Write Reset WDOG_TMROUTL field descriptions Field Description 15–0 Shows the value of the lower 16 bits of the watchdog timer. TIMEROUTLOW K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 527: Watchdog Reset Count Register (Wdog_Rstcnt)
When performing 8-bit accesses to the watchdog's 16-bit registers where the intention is to access both the bytes of a register, place the two 8-bit accesses one after the other in your code. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 528: Refresh And Unlock Operations With 8-Bit Access
16-bit value is correctly written, write4. Hence, the requirement of writing value2 of the sequence within 20 bus clock cycles of value1 is checked by measuring the gap between write2 and write4. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 529: Restrictions On Watchdog Operation
• The time-out value of the watchdog should be set to a minimum of four watchdog clock cycles. This is to take into account the delay in new settings taking effect in the watchdog clock domain. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 530 If the second refresh value is not written within 20 bus cycles of the first value, the system is reset, or interrupt-then- reset if enabled. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 531: Multipurpose Clock Generator (Mcg)
• Option to program and maximize DCO output frequency for a low frequency external reference clock source. • Option to prevent FLL from resetting its current locked frequency when switching clock modes if FLL reference frequency is not changed. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 532 • External clock monitor with reset and interrupt request capability to check for external clock failure when running in FBE, PEE, BLPE, or FEE modes • Lock detector with interrupt request capability for use with the PLL K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 533 • MCG Fixed Frequency Clock (MCGFFCLK) is provided as a clock source for other on-chip peripherals • MCG Internal Reference Clock (MCGIRCLK) is provided as a clock source for other on-chip peripherals This figure presents the block diagram of the MCG module. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 534 Filter /(24,25,26..55) Multipurpose Clock Generator (MCG) Figure 25-1. Multipurpose Clock Generator (MCG) block diagram NOTE Refer to the chip configuration chapter to identify the oscillator used in this MCU. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 535: Modes Of Operation
MCG Auto Trim Compare Value High Register 4006_400A 25.3.9/546 (MCG_ATCVH) MCG Auto Trim Compare Value Low Register 25.3.10/ 4006_400B (MCG_ATCVL) 25.3.11/ 4006_400C MCG Control 7 Register (MCG_C7) 25.3.12/ 4006_400D MCG Control 8 Register (MCG_C8) K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 536: Mcg Control 1 Register (Mcg_C1)
MCGIRCLK active. Internal Reference Stop Enable IREFSTEN Controls whether or not the internal reference clock remains enabled when the MCG enters Stop mode. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 537: Mcg Control 2 Register (Mcg_C2)
EREFS Selects the source for the external reference clock. See the Oscillator (OSC) chapter for more details. External reference clock requested. Oscillator requested. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 538: Mcg Control 3 Register (Mcg_C3)
If an SCTRIM value stored in nonvolatile memory is to be used, it is your responsibility to copy that value from the nonvolatile memory location to this register. 1. A value for SCTRIM is loaded during reset from a factory programmed location. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 539: Mcg Control 4 Register (Mcg_C4)
DRST field does not update immediately after a write to the DRS field due to internal synchronization between clock domains. See the DCO Frequency Range table for more details. Encoding 0 — Low range (reset default). Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 540: Mcg Control 5 Register (Mcg_C5)
OSCINIT 0 bit should be checked to make sure it is set. MCGPLLCLK is inactive. MCGPLLCLK is active. PLL Stop Enable PLLSTEN0 Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 541: Mcg Control 6 Register (Mcg_C6)
Address: 4006_4000h base + 5h offset = 4006_4005h Read LOLIE0 PLLS CME0 VDIV0 Write Reset MCG_C6 field descriptions Field Description Loss of Lock Interrrupt Enable LOLIE0 Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 542 11000 00001 01001 10001 11001 00010 01010 10010 11010 00011 01011 10011 11011 00100 01100 10100 11100 00101 01101 10101 11101 00110 01110 10110 11110 00111 01111 10111 11111 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 543: Mcg Status Register (Mcg_S)
IREFS bit due to internal synchronization between clock domains. Source of FLL reference clock is the external reference clock. Source of FLL reference clock is the internal reference clock. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 544: Mcg Status And Control Register (Mcg_Sc)
Writing to C1, C3, C4, and SC registers or entering Stop mode aborts the auto trim operation and clears this bit. Auto Trim Machine disabled. Auto Trim Machine enabled. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 545 CME0 is set. This bit is cleared by writing a logic 1 to it when set. Loss of OSC0 has not occurred. Loss of OSC0 has occurred. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 546: Mcg Auto Trim Compare Value High Register (Mcg_Atcvh)
Values are used by Auto Trim Machine to compare and adjust Internal Reference trim values during ATM SAR conversion. 25.3.11 MCG Control 7 Register (MCG_C7) Address: 4006_4000h base + Ch offset = 4006_400Ch Read OSCSEL Write Reset K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 547: Mcg Control 8 Register (Mcg_C8)
Enables the loss of clock monitoring circuit for the output of the RTC external reference clock. The LOCRE1 bit will determine whether an interrupt or a reset request is generated following a loss of RTC Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 548: Functional Description
25.4.1 MCG mode state diagram The nine states of the MCG are shown in the following figure and are described in Table 25-16. The arrows indicate the permitted MCG mode transitions. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 549 2’b10. 25.4.1.1 MCG modes of operation The MCG operates in one of the following modes. Note The MCG restricts transitions between modes. For the permitted transitions, see Figure 25-14. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 550 C4[DRST_DRS] and C4[DMX32] bits, times the internal reference frequency. See the C4[DMX32] bit description for more details. In FBI mode, the PLL is disabled in a low-power state unless C5[PLLCLKEN] is set . Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 551 [PRDIV]. In preparation for transition to PEE, the PLL's programmable reference divider must be configured to produce a valid PLL reference clock. The FLL is disabled in a low- power state. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 552 (C2[IRCS]=1). After it enters VLPR mode, writes to any of the MCG control registers that can cause an MCG clock mode switch to a non low power clock mode must be avoided. NOTE For the chip-specific modes of operation, see the power management chapter of this MCU. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 553: Low-Power Bit Usage
FRDIV factors) or the slow internal reference clock (32 kHz IRC). The IRCS clock frequency can be re-targeted by trimming the period of its IRCS selected internal reference clock. This can be done by writing a new trim value to the K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 554: External Reference Clock
Crystal Oscillator, divided by the FLL reference clock divider. The source of MCGFFCLK is selected by C1[IREFS]. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 555: Mcg Pll Clock
ATM uses a pulse that is generated by the ATM selected IRC clock to enable a counter that counts number of ATM external clocks. At end of each trim bit, K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 556: Initialization / Application Information
The internal reference will stabilize in t microseconds before the FLL can acquire irefsts lock. As soon as the internal reference is stable, the FLL will acquire lock in t fll_acquire milliseconds. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 557 2'b10 indicating the external reference clock has been appropriately selected. Although the FLL is bypassed, it is still on in FBE mode. 4. Write to the C4 register to determine the DCO output (MCGFLLCLK) frequency range. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 558 2. Wait for S[CLKST] bits in the MCG status register to change to 2'b01, indicating that the internal reference clock has been appropriately selected. 3. Write to the C2 register to determine the IRCS output (IRCSCLK) frequency range. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 559: Using A 32.768 Khz Reference
In FBE, FEE, FBI, and FEI modes, at any time, the application can switch the FLL multiplication factor between 640, 1280, 1920, and 2560 with C4[DRST_DRS] bits. Writes to C4[DRST_DRS] bits will be ignored if C2[LP]=1. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 560 1. First, FEI must transition to FBE mode: a. C2 = 0x2C • C2[RANGE] set to 2'b01 because the frequency of 4 MHz is within the high frequency range. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 561 = 48 MHz. In BLPE mode, the configuration of the VDIV bits does not matter because the PLL is disabled. Changing them only sets up the multiply value for PLL usage in PBE mode. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 562 Loop until S[CLKST] are 2'b11, indicating that the PLL output is selected to feed MCGOUTCLK in the current clock mode. • Now, with PRDIV of divide-by-2, and C6[VDIV] of multiply-by-24, MCGOUTCLK = [(4 MHz / 2) * 24] = 48 MHz. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 563 Chapter 25 Multipurpose Clock Generator (MCG) Figure 25-15. Flowchart of FEI to PEE mode transition using an 4 MHz crystal K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 564 PLLS clock is the FLL. 3. Next, FBE mode transitions into FBI mode: a. C1 = 0x54 • C1[CLKS] set to 2'b01 to switch the system clock to the internal reference clock. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 565 • C2[LP] is 1 • C2[RANGE], C2[HGO], C2[EREFS], C1[IRCLKEN], and C1[IREFSTEN] bits are ignored when the C1[IREFS] bit is set. They can remain set, or be cleared at this point. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 566 BLPE MODE ? BLPE MODE ? (C2[LP]=1) CONTINUE IN BLPI MODE C2 = 0x1C (C2[LP] = 0) Figure 25-16. Flowchart of PEE to BLPI mode transition using an 4 MHz crystal K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 567 At this point, by default, the C4[DRST_DRS] bits are set to 2'b00 and C4[DMX32] is cleared to 0. If the MCGOUTCLK frequency of 40 MHz is desired instead, set the C4[DRST_DRS] bits to 0x01 to switch the FLL K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 568 S[CLKST] = %00? C1 = 0x10 CONTINUE IN FEE MODE CHECK S[OSCINIT] = 1 ? Figure 25-17. Flowchart of BLPI to FEE mode transition using an 4 MHz crystal K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 569: Oscillator (Osc)
• Optionally external input bypass clock from EXTAL signal directly • One clock for MCU clock system • Two clocks for on-chip peripherals that can work in Stop modes Functional Description describes the module's operation in more detail. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 570: Block Diagram
OSCCLK OSC clock selection logic STOP Figure 26-1. OSC Module Block Diagram 26.4 OSC Signal Descriptions The table found here shows the user-accessible signals available for the OSC module. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 571: External Crystal / Resonator Connections
2. With the low-power mode, the oscillator has the internal feedback resistor R . Therefore, the feedback resistor must not be externally with the Connection 3. XTAL EXTAL Crystal or Resonator Figure 26-2. Crystal/Ceramic Resonator Connections - Connection 1 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 572: External Clock Connections
In external clock mode, the pins can be connected as shown in the figure found here. NOTE XTAL can be used as a GPIO when the GPIO alternate function is configured for it. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 573: Memory Map/Register Definitions
Address: 4006_5000h base + 0h offset = 4006_5000h Read ERCLKEN EREFSTEN SC2P SC4P SC8P SC16P Write Reset K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 574 Add 8 pF capacitor to the oscillator load. Oscillator 16 pF Capacitor Load Configure SC16P Configures the oscillator load. Disable the selection. Add 16 pF capacitor to the oscillator load. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 575: Functional Description
26.8.1 OSC module states The states of the OSC module are shown in the following figure. The states and their transitions between each other are described in this section. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 576 MCU, refer to the chip configuration details. The EXTAL and XTAL pins are also decoupled from all other oscillator circuitry in this state. The OSC module circuitry is configured to draw minimal current. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 577: Osc Module Modes
(MCG, Timer, and so on) is configured to use the oscillator output clock (OSC_CLK_OUT). Table 26-6. Oscillator modes Mode Frequency Range Low-frequency, high-gain (32.768 kHz) up to f (39.0625 kHz) osc_lo osc_lo Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 578 (not sensitive to the DC level of EXTAL). Also in this mode, all external components except for the resonator itself are integrated, which includes the load capacitors and feeback resistor that biases EXTAL. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 579: Counter
There is no reset state associated with the OSC module. The counter logic is reset when the OSC is not configured to generate clocks. There are no sources of reset requests for the OSC module. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 580: Low Power Modes Operation
OSC is still functional in these modes. After waking up from Very Low Leakage Stop (VLLSx) modes, all OSC register bits are reset and initialization is required through software. 26.11 Interrupts The OSC module does not generate any interrupts. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 581: Rtc Oscillator (Osc32K)
• Automatic Gain Control (AGC) to optimize power consumption The RTC oscillator operations are described in detail in Functional Description 27.1.2 Block Diagram The following is the block diagram of the RTC oscillator. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 582: Rtc Signal Descriptions
27.2.1 EXTAL32 — Oscillator Input This signal is the analog input of the RTC oscillator. 27.2.2 XTAL32 — Oscillator Output This signal is the analog output of the RTC oscillator module. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 583: External Crystal Connections
EXTAL32 and XTAL32. In addition, there are two programmable capacitors with this oscillator, which can be used as the Cload of the oscillator. The programmable range is from 0pF to 30pF. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 584: Reset Overview
Reset Overview 27.6 Reset Overview There is no reset state associated with the RTC oscillator. 27.7 Interrupts The RTC oscillator does not generate any interrupts. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 585: Flash Memory Controller (Fmc)
64-bit flash memory location, and both a 4-way, 8-set cache and a single-entry 64-bit buffer can store previously accessed flash memory data for quick access times. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 586: Features
The programming model consists of the FMC control registers and the program visible cache (data and tag/valid entries). NOTE Program the registers only while the flash controller is idle (for example, execute from RAM). Changing configuration settings K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 587 [63:32] of data entry way 1, and U and L represent upper and set 0, and DATAW1S0L lower word, respectively. represents bits [31:0] of data entry way 1, set 0. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 588 Cache Data Storage (upper word) (FMC_DATAW0S0U) 0000_0000h 28.4.8/603 4001_F204 Cache Data Storage (lower word) (FMC_DATAW0S0L) 0000_0000h 28.4.9/604 4001_F208 Cache Data Storage (upper word) (FMC_DATAW0S1U) 0000_0000h 28.4.8/603 Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 589 4001_F26C Cache Data Storage (lower word) (FMC_DATAW1S5L) 0000_0000h 28.4.10/ 4001_F270 Cache Data Storage (upper word) (FMC_DATAW1S6U) 0000_0000h 28.4.11/ 4001_F274 Cache Data Storage (lower word) (FMC_DATAW1S6L) 0000_0000h Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 590 4001_F2C4 Cache Data Storage (lower word) (FMC_DATAW3S0L) 0000_0000h 28.4.14/ 4001_F2C8 Cache Data Storage (upper word) (FMC_DATAW3S1U) 0000_0000h 28.4.15/ 4001_F2CC Cache Data Storage (lower word) (FMC_DATAW3S1L) 0000_0000h Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 591: Flash Access Protection Register (Fmc_Pfapr)
4001_F2FC Cache Data Storage (lower word) (FMC_DATAW3S7L) 0000_0000h 28.4.1 Flash Access Protection Register (FMC_PFAPR) Address: 4001_F000h base + 0h offset = 4001_F000h Reserved Reset M7AP[1:0] M6AP[1:0] M5AP[1:0] M4AP[1:0] M3AP[1:0] M2AP[1:0] M1AP[1:0] M0AP[1:0] Reset K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 592 This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits. Prefetching for this master is enabled. Prefetching for this master is disabled. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 593 No access may be performed by this master Only read accesses may be performed by this master Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 594 Only read accesses may be performed by this master Only write accesses may be performed by this master Both read and write accesses may be performed by this master K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 595: Flash Bank 0 Control Register (Fmc_Pfb0Cr)
Cache way is unlocked and may be displaced Cache way is locked and its contents are not displaced 23–20 Cache Invalidate Way x CINV_WAY[3:0] Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 596 Do not cache data references. Cache data references. Bank 0 Instruction Cache Enable B0ICE This bit controls whether instruction fetches are loaded into the cache. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 597 1's cache. A high-to-low transition of this enable forces the page buffer to be invalidated. Single entry buffer is disabled. Single entry buffer is enabled. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 598: Flash Bank 1 Control Register (Fmc_Pfb1Cr)
This read-only field is reserved and always has the value 0. 18–17 Bank 1 Memory Width B1MW[1:0] This read-only field defines the width of the bank 1 memory. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 599 0's cache. A high-to-low transition of this enable forces the page buffer to be invalidated. Single entry buffer is disabled. Single entry buffer is enabled. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 600: Cache Tag Storage (Fmc_Tagvdw0Sn)
14-bit tag for cache entry tag[18:5] 4–1 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 1-bit valid for cache entry valid K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 601: Cache Tag Storage (Fmc_Tagvdw1Sn)
14-bit tag for cache entry tag[18:5] 4–1 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 1-bit valid for cache entry valid K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 602: Cache Tag Storage (Fmc_Tagvdw2Sn)
14-bit tag for cache entry tag[18:5] 4–1 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 1-bit valid for cache entry valid K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 603: Cache Tag Storage (Fmc_Tagvdw3Sn)
This section represents data for the upper word (bits [63:32]) of all sets in the indicated way. Address: 4001_F000h base + 200h offset + (8d × i), where i=0d to 7d data[63:32] Reset K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 604: Cache Data Storage (Lower Word) (Fmc_Dataw0Snl)
This section represents data for the upper word (bits [63:32]) of all sets in the indicated way. Address: 4001_F000h base + 240h offset + (8d × i), where i=0d to 7d data[63:32] Reset K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 605: Cache Data Storage (Lower Word) (Fmc_Dataw1Snl)
This section represents data for the upper word (bits [63:32]) of all sets in the indicated way. Address: 4001_F000h base + 280h offset + (8d × i), where i=0d to 7d data[63:32] Reset K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 606: Cache Data Storage (Lower Word) (Fmc_Dataw2Snl)
This section represents data for the upper word (bits [63:32]) of all sets in the indicated way. Address: 4001_F000h base + 2C0h offset + (8d × i), where i=0d to 7d data[63:32] Reset K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 607: Cache Data Storage (Lower Word) (Fmc_Dataw3Snl)
28.5.1 Default configuration Upon system reset, the FMC is configured to provide a significant level of buffering for transfers from the flash memory: K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 608: Configuration Options
0, while the single-entry buffer can be enabled for bank 1 only. This configuration is ideal for applications that use bank 0 for program space and bank 1 for data space. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 609: Speculative Reads
4. Reading the fourth longword, like the second longword, takes only 1 clock due to the 64-bit flash memory data bus. 28.6 Initialization and application information The FMC does not require user initialization. Flash acceleration features are enabled by default. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 610 FMC's cache might need to be disabled and/or flushed to prevent the possibility of returning stale data. Use the PFB0CR[CINV_WAY] field to invalidate the cache in this manner. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 611: Flash Memory Module (Ftfa)
('1') states and/or programmed ('0') states. Therefore, it is recommended that each flash block or sector be re-erased immediately prior to factory programming to ensure that the full data retention capability is achieved. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 612: Features
• Supports MCU security mechanisms which prevent unauthorized access to the flash memory contents 29.1.2 Block Diagram The block diagram of the flash memory module is shown in the following figure. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 613: Glossary
Longword — 32 bits of data with an aligned longword having byte-address[1:0] = 00. NVM — Nonvolatile memory. A memory technology that maintains stored data during power-off. The flash array is an NVM using NOR-type flash memory technology. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 614: External Signal Description
This section describes the memory map and registers for the flash memory module. Data read from unimplemented memory space in the flash memory module is undefined. Writes to unimplemented or reserved memory space (registers) in the flash memory module are ignored. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 615: Flash Configuration Field Description
0x00 – 0x9F Reserved 0xA0 – 0xA3 Program Once XACCH-1 Field (index = 0x10) 0xA4 – 0xA7 Program Once XACCL-1 Field (index = 0x10) Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 616: Register Descriptions
CCIF. During this initialization period the user may write any register. All register writes are also disabled (except for registers FCNFG and FSTAT) whenever an erase suspend request is active (FCNFG[ERSSUSP]=1). K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 617 Undefined 29.33.6/ 4002_0013 Program Flash Protection Registers (FTFA_FPROT0) Undefined 29.33.7/ 4002_0018 Execute-only Access Registers (FTFA_XACCH3) Undefined 29.33.7/ 4002_0019 Execute-only Access Registers (FTFA_XACCH2) Undefined Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 618 MGSTAT0 bit is read only. The unassigned bits read 0 and are not writable. NOTE When set, the Access Error (ACCERR) and Flash Protection Violation (FPVIOL) bits in this register prevent the launch of K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 619 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Memory Controller Command Completion Status Flag MGSTAT0 Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 620 ERSAREQ sets when an erase all request is triggered external to the flash memory module and CCIF is set (no command is currently being executed). ERSAREQ is cleared by the flash memory module when the operation completes. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 621 = Undefined at reset. FTFA_FSEC field descriptions Field Description 7–6 Backdoor Key Security Enable KEYEN Enables or disables backdoor key access to the flash memory module. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 622 NVM at reset. The function of the bits is defined in the device's Chip Configuration details. All bits in the register are read-only . K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 623 FCCOB parameter fields and they cannot be changed by the user until the command completes (CCIF returns to 1). No command buffering or queueing is provided; the next command can be loaded only after the current command completes. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 624 KB of program flash where each assigned bit protects 1 KB . For configurations with 24 KB of program flash memory or less, FPROT0 is not used. For configurations with 16 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 625 1 and protected regions use a 0, only writes changing 1s to 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with 0-to-1 transitions are ignored. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 626 Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 627 SACCL3 SA[7:0] During the reset sequence, the SACC registers are loaded with the logical AND of Program Flash IFR addresses A and B as indicated in the following table. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 628 All bits in the register are read-only. The contents of this register are loaded during the reset sequence. Address: 4002_0000h base + 28h offset = 4002_0028h Read SGSIZE Write Reset K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 629 Number of Segments Indicator NUMSG The NUMSG field indicates the number of equal-sized segments in the program flash. 0x20 Program flash memory is divided into 32 segments (64 Kbytes, 128 Kbytes) K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 630: Functional Description
FPROT0[PROT31] Last program flash address Figure 29-44. Program flash protection NOTE Flash protection features are discussed further in AN4507: Using the Kinetis Security and Flash Protection Features . Not K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 631: Flash Access Protection
Figure 29-45. Program flash access control (256KB or 512KB of program flash) • FSACC — • For 2 program flash sizes greater than 128KB, eight registers control 64 segments of the program flash memory as shown in the following figure K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 632: Interrupts
Some devices also generate a bus error response as a result of a Read Collision Error event. See the chip configuration information to determine if a bus error response is also supported. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 633: Flash Operation In Low-Power Modes
Chip Configuration details of this device for how to activate each mode. 29.4.6 Flash Reads and Ignored Writes The flash memory module requires only the flash address to execute a flash memory read. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 634: Read While Write (Rww)
Flash commands are specified using a command write sequence illustrated in Figure 29-47. The flash memory module performs various checks on the command (FCCOB) content and continues with command execution if all requirements are fulfilled. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 635 Program and erase commands also check the address to determine if the operation is requested to execute on protected areas. If the protection check fails, FSTAT[FPVIOL] (protection error) flag is set. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 636 More Parameters? Clear the CCIF to launch the command Write 0x80 to FSTAT register EXIT Figure 29-47. Generic flash command write sequence flowchart K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 637 29.4.9.3 Flash Commands by Mode The following table shows the flash commands that can be executed in each flash operating mode. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 638: Margin Read Commands
The 'user' and 'factory' levels become, in effect, a minimum safety margin; i.e. if the reads pass at the tighter tolerances of the 'user' and 'factory' margins, then the 'normal' reads have at least this much safety margin before they experience data loss. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 639: Flash Command Description
MCU with the collision error flag (FSTAT[RDCOLERR]) set. CAUTION Flash data must be in the erased state before being programmed. Cumulative programming of bits (adding more zeros) is not allowed. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 640 An invalid flash address is supplied. FSTAT[ACCERR] Flash address is not phrase aligned. FSTAT[ACCERR] The requested section crosses a Flash block boundary. FSTAT[ACCERR] The requested number of phrases is 0. FSTAT[ACCERR] Read-1s fails. FSTAT[MGSTAT0] K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 641 Table 29-50. Margin Level Choices for Program Check Read Margin Choice Margin Level Description 0x01 Read at 'User' margin-1 and 'User' margin-0 0x02 Read at 'Factory' margin-1 and 'Factory' margin-0 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 642 Resource Size Local Address Range Select Code 0x00 Program Flash 0 IFR 256 Bytes 0x00_0000–0x00_00FF 0x01 Version ID 8 Bytes 0x00_0000–0x00_0007 1. Located in program flash 0 reserved space. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 643 Flash address [7:0] Byte 0 program value Byte 1 program value Byte 2 program value Byte 3 program value 1. Must be longword aligned (Flash address [1:0] = 00). K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 644 Flash address [15:8] in the flash sector to be erased Flash address [7:0] in the flash sector to be erased 1. Must be phrase aligned (flash address [2:0] = 000). K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 645 CCIF and leaves the ERSSUSP bit set. While CCIF is set, the ERSSUSP bit can only be cleared to prevent the withdrawal of a suspend request before the flash memory module has acknowledged it. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 646 Data in this sector is not reliable until a new erase command fully completes. The following figure shows how to suspend and resume the Erase Flash Sector operation. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 647 ERSSCR Suspended Resume Erase? ERSSUSP: Bit in FCNFG register No, Abort SUSPACK: Internal Suspend Acknowledge Clear ERSSUSP User Cmd Interrupt/Suspend Figure 29-48. Suspend and Resume of Erase Flash Sector Operation K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 648 Apply the 'Factory' margin to the normal read-1 level Table 29-61. Read 1s All Blocks Command Error Handling Error Condition Error Bit An invalid margin choice is specified FSTAT[ACCERR] Read-1s fails FSTAT[MGSTAT0] K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 649 The Read Once command can be executed any number of times. Table 29-63. Read Once Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid record index is supplied FSTAT[ACCERR] K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 650 Command not available in current mode/security FSTAT[ACCERR] An invalid record index is supplied FSTAT[ACCERR] The requested record has already been programmed to a non-FFFF value FSTAT[ACCERR] Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 651 Error Bit Command not available in current mode/security FSTAT[ACCERR] Any region of the program flash memory is protected FSTAT[FPVIOL] Any errors have been encountered during the verify operation FSTAT[MGSTAT0] K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 652 Key Byte 1 0x0_0002 Key Byte 2 0x0_0001 Key Byte 3 0x0_0000 Key Byte 4 0x0_0007 Key Byte 5 0x0_0006 Key Byte 6 0x0_0005 Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 653: Security
Flash Configuration Field (see Flash Configuration Field Description). The following fields are available in the FSEC register. The settings are described in the Flash Security Register (FTFA_FSEC) details. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 654 8-byte backdoor key value stored in the Flash Configuration Field (see Flash Configuration Field Description). If the FSEC[KEYEN] bits are in the enabled state, the Verify Backdoor Access Key command (see Verify K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 655: Reset Sequence
29.4.13 Reset Sequence On each system reset the flash memory module executes a sequence which establishes initial values for the flash block configuration parameters, FPROT, FOPT, and FSEC registers. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 656 If a reset occurs while any flash command is in progress, that command is immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. Commands and operations do not automatically resume after exiting reset. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 657: Overview
Memory contents can be read/erased/programmed from an external source, in a format that is compatible with many standalone flash memory chips, without requiring the removal of the microcontroller from the system board. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 658: Block Diagram
• Ability to reset the microcontroller, allowing it to boot from the flash memory after the memory has been configured. 30.1.3 Modes of operation The EzPort can operate in one of two modes, enabled or disabled. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 659: External Signal Descriptions
EZP_CK is the serial clock for data transfers. The serial data in (EZP_D) and chip select (EZP_CS) are registered on the rising edge of EZP_CK, while serial data out (EZP_Q) is driven on the falling edge of EZP_CK. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 660: Ezport Chip Select (Ezp_Cs)
Address Accepted when Command Description Code Data Bytes Bytes secure? WREN Write Enable 0x06 WRDI Write Disable 0x04 RDSR Read Status Register 0x05 Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 661: Command Descriptions
WRFCCOB) to be accepted. The write enable register field clears on reset, on a Write Disable command, and at the completion of write command. This command must not be used if a write is already in progress. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 662 Table 30-3. EzPort status register BEDIS Reset: 1. Reset value reflects the status of flash security out of reset. 2. Reset value reflects whether bulk erase is enabled or disabled out of reset. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 663 Flash security can be disabled by performing a BE command. 0 = Flash is not secure. 1 = Flash is secure. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 664 The Read Data at High Speed (FAST_READ) command is identical to the READ command, except for the inclusion of a dummy byte following the address bytes and before the first data byte is returned. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 665 Flash memory map for EzPort access. This command is not accepted if the WEF, WIP, or FS field is set or if the WEN field is not set in the EzPort status register. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 666 WEF flag being set in the EzPort status register. Also, this command is not accepted if the WEF or WIP field is set or if the WEN field is not set in the EzPort status register. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 667 NOTE When security is enabled, the flash is configured in NVM Special mode, restricting the commands that can be executed by the flash. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 668: Flash Memory Map For Ezport Access
The flash block address map for access through EzPort may not conform to the system memory map. Changes are made to allow the EzPort address width to remain 24 bits. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 669 Chapter 30 EzPort Table 30-5. Flash Memory Map for EzPort Access Valid start address Size Flash block Valid commands See device's chip 0x0000_0000 Flash READ, FAST_READ, SP, SE, BE configuration details K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 670 Flash memory map for EzPort access K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 671: Cyclic Redundancy Check (Crc)
• Option for inversion of final CRC result • 32-bit CPU register programming interface 31.1.2 Block diagram The following is a block diagram of the CRC. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 672: Modes Of Operation
Register name Access Reset value (in bits) page (hex) 4003_2000 CRC Data register (CRC_DATA) FFFF_FFFFh 31.2.1/673 4003_2004 CRC Polynomial register (CRC_GPOLY) 0000_1021h 31.2.2/674 4003_2008 CRC Control register (CRC_CTRL) 0000_0000h 31.2.3/674 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 673: Crc Data Register (Crc_Data)
When CTRL[WAS] is 1, values written to this field are part of the seed value. When CTRL[WAS] is 0, data written to this field is used for CRC checksum generation. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 674: Crc Polynomial Register (Crc_Gpoly)
CRC calculation. A new CRC calculation is initialized by asserting CTRL[WAS] and then writing the seed into the CRC data register. Address: 4003_2000h base + 8h offset = 4003_2008h TOTR FXOR WAS Reset Reset K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 675: Functional Description
Width of CRC protocol. TCRC 16-bit CRC protocol. 32-bit CRC protocol. 23–0 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 31.3 Functional description K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 676: Crc Calculations
8. When all values have been written, read the final CRC result from CRC_DATA[LU:LL]. Transpose and complement operations are performed on the fly while reading or writing values. See Transpose feature CRC result complement for details. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 677: Transpose Feature
CTRL[TOT] or CTRL[TOTR] fields, according to the CRC calculation being used. The following types of transpose functions are available for writing to and reading from the CRC data register: 1. CTRL[TOT] or CTRL[TOTR] is 00. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 678 = {reg[0:7], reg[8:15],reg[16:23], reg[24:31]} Figure 31-6. Transpose type 10 4. CTRL[TOT] or CTRL[TOTR] is 11. Bytes are transposed, but bits are not transposed. reg[31:0] becomes {reg[7:0], reg[15:8], reg[23:16], reg[31:24]} K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 679: Crc Result Complement
CRC data register every time the CRC data register is read. When CTRL[FXOR] is cleared, reading the CRC data register accesses the raw checksum value. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 680 Functional description K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 681: Random Number Generator Accelerator (Rnga)
NIST-approved pseudo-random-number generator based on DES or SHA-1 and defined in NIST FIPS PUB 186-2 Appendix 3 and NIST FIPS PUB SP 800-90. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 682: Modes Of Operation
(randomness) from the clocks and stores it in shift registers. Sleep The ring-oscillator clocks are inactive; RNGA does not generate entropy. 32.2.1 Entering Normal mode To enter Normal mode, write 0 to CR[SLP]. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 683: Memory Map And Register Definition
4002_900C RNGA Output Register (RNG_OR) 0000_0000h 32.3.4/687 32.3.1 RNGA Control Register (RNG_CR) Controls the operation of RNGA. Address: 4002_9000h base + 0h offset = 4002_9000h Reset INTM CLRI Reset K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 684 Specifies whether random-data generation and loading (into OR[RANDOUT]) is enabled. NOTE: This field is sticky. You must reset RNGA to stop RNGA from loading OR[RANDOUT] with data. Disabled Enabled K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 685: Rnga Status Register (Rng_Sr)
NOTE: If you read OR[RANDOUT] when SR[OREG_LVL] is not 0, then the contents of a random number contained in OR[RANDOUT] are returned, and RNGA writes 0 to both OR[RANDOUT] and SR[OREG_LVL]. No words (empty) One word (valid) Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 686 Used only when high assurance is enabled (CR[HA]). Indicates that a security violation has occurred. NOTE: This field is sticky. To clear SR[SECV], you must reset RNGA. No security violation Security violation K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 687: Rnga Entropy Register (Rng_Er)
RNG_OR field descriptions Field Description 31–0 Random Output RANDOUT Stores a random-data word generated by RNGA. This is a read-only field. NOTE: Before reading RANDOUT, be sure it is valid (SR[OREG_LVL]=1). K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 688: Functional Description
OR when it is empty, RNGA returns all zeros and, if the interrupt is enabled, RNGA drives a request to the interrupt controller. Polling SR[OREG_LVL] is very important to make sure random values are present before reading from OR. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 689: Initialization/Application Information
3. Poll SR[OREG_LVL] until it is not 0. 4. When SR[OREG_LVL] is not 0, read the available random data from OR[RANDOUT]. 5. Repeat steps 3 and 4 as needed. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 690 Initialization/application information For application information, see Overview. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 691: Analog-To-Digital Converter (Adc)
• Output format in 2's complement 16-bit sign extended for differential modes • Output in right-justified unsigned format for single-ended • Single or continuous conversion, that is, automatic return to idle after single conversion K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 692: Block Diagram
• Temperature sensor • Hardware average function • Selectable voltage reference: external or alternate • Self-Calibration mode 33.1.2 Block diagram The following figure is the ADC module block diagram. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 693: Adc Signal Descriptions
Each differential pair requires two inputs, DADPx and DADMx. The ADC also requires four supply/reference/ground connections. NOTE Refer to ADC configuration section in chip configuration chapter for the number of channels supported on this device. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 694: Analog Power (Vdda)
ALTL depending on MCU configuration. See the chip configuration information on the Voltage References specific to this MCU. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 695: Analog Channel Inputs (Adx)
33.3.4/703 4002_7014 ADC Data Result Register (ADC1_RB) 0000_0000h 33.3.4/703 4002_7018 Compare Value Registers (ADC1_CV1) 0000_0000h 33.3.5/704 4002_701C Compare Value Registers (ADC1_CV2) 0000_0000h 33.3.5/704 Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 696 33.3.4/703 4003_B014 ADC Data Result Register (ADC0_RB) 0000_0000h 33.3.4/703 4003_B018 Compare Value Registers (ADC0_CV1) 0000_0000h 33.3.5/704 4003_B01C Compare Value Registers (ADC0_CV2) 0000_0000h 33.3.5/704 Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 697: Adc Status And Control Registers 1 (Adcx_Sc1N)
To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC can have more than one status and control register: one for each conversion. The SC1B–SC1n registers indicate potentially multiple SC1 registers for use only in hardware K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 698 Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Conversion Complete Flag COCO Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 699 When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved. 01011 When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 700: Adc Configuration Register 1 (Adcx_Cfg1)
The configuration Register 1 (CFG1) selects the mode of operation, clock source, clock divide, and configuration for low power or long sample time. Address: Base address + 8h offset Reset ADIV MODE ADICLK Reset K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 701 In this case, there is an associated clock startup delay each time the clock source is re-activated. Bus clock Alternate clock 2 (ALTCLK2) Alternate clock (ALTCLK) Asynchronous clock (ADACK) K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 702: Adc Configuration Register 2 (Adcx_Cfg2)
Configures the ADC for very high-speed operation. The conversion sequence is altered with 2 ADCK cycles added to the conversion time to allow higher speed conversion clocks. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 703: Adc Data Result Register (Adcx_Rn)
13-bit differential S Sign-extended 2's complement 12-bit single- Unsigned right- ended justified 11-bit differential S Sign-extended 2's complement 10-bit single- Unsigned right- ended justified Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 704: Compare Value Registers (Adcx_Cvn)
The compare value 2 register (CV2) is used only when the compare range function is enabled, that is, SC2[ACREN]=1. Address: Base address + 18h offset + (4d × i), where i=0d to 1d Reset K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 705: Status And Control Register 2 (Adcx_Sc2)
ADCx_SC2 field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Conversion Active ADACT Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 706 . This pair may be additional external pins or ALTH ALTL internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 707: Status And Control Register 3 (Adcx_Sc3)
Begins the calibration sequence when set. This field stays set while the calibration is in progress and is cleared when the calibration sequence is completed. CALF must be checked to determine the result of the Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 708 Hardware Average Select AVGS Determines how many ADC conversions will be averaged to create the ADC average result. 4 samples averaged. 8 samples averaged. 16 samples averaged. 32 samples averaged. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 709: Adc Offset Correction Register (Adcx_Ofs)
ADPG15 and ADPG14. This register must be written by the user with the value described in the calibration procedure. Otherwise, the gain error specifications may not be met. Address: Base address + 2Ch offset Reset K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 710: Adc Minus-Side Gain Register (Adcx_Mg)
CLP4[9:0], CLPS[5:0], and CLPD[5:0]. CLPx are automatically set when the self- calibration sequence is done, that is, CAL is cleared. If these registers are written by the user after calibration, the linearity error specifications may not be met. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 711: Adc Plus-Side General Calibration Value Register (Adcx_Clps)
5–0 Calibration Value CLPS Calibration Value 33.3.13 ADC Plus-Side General Calibration Value Register (ADCx_CLP4) For more information, see CLPD register description. Address: Base address + 3Ch offset CLP4 Reset K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 712: Adc Plus-Side General Calibration Value Register (Adcx_Clp3)
Reset ADCx_CLP2 field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 713: Adc Plus-Side General Calibration Value Register (Adcx_Clp1)
Reset ADCx_CLP0 field descriptions Field Description 31–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 5–0 Calibration Value CLP0 Calibration Value K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 714: Adc Minus-Side General Calibration Value Register (Adcx_Clmd)
Reset ADCx_CLMS field descriptions Field Description 31–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 5–0 Calibration Value CLMS Calibration Value K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 715: Adc Minus-Side General Calibration Value Register (Adcx_Clm4)
Reset ADCx_CLM3 field descriptions Field Description 31–9 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 8–0 Calibration Value CLM3 Calibration Value K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 716: Adc Minus-Side General Calibration Value Register (Adcx_Clm2)
Reset ADCx_CLM1 field descriptions Field Description 31–7 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 6–0 Calibration Value CLM1 Calibration Value K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 717: Adc Minus-Side General Calibration Value Register (Adcx_Clm0)
The ADC module has the capability of automatically comparing the result of a conversion with the contents of the CV1 and CV2 registers. The compare function is enabled by setting SC2[ACFE] and operates in any of the conversion modes and configurations. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 718: Clock Select And Divide Control
If the available clocks are too fast, the clock must be divided to the appropriate frequency. This divider is specified by CFG1[ADIV] and can be divide-by 1, 2, 4, or 8. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 719: Voltage Reference Selection
ADHWT signal to trigger a new conversion. The channel and status fields selected for the conversion depend on the active trigger select signal: • ADHWTSA active selects SC1A. • ADHWTSn active selects SC1n. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 720: Conversion Control
SC2[ADTRG]=1, and a hardware trigger select event, ADHWTSn, has occurred. The channel and status fields selected depend on the active trigger select signal: • ADHWTSA active selects SC1A. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 721 SC1n[COCO] sets only if the last of the selected number of conversions is completed and the compare condition is true. An interrupt is generated if the respective SC1n[AIEN] is high at the time that the respective SC1n[COCO] is set. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 722 CFG2[ADACKEN]=1, it remains active regardless of the state of the ADC or the MCU power mode. Power consumption when the ADC is active can be reduced by setting CFG1[ADLPC]. This results in a lower maximum value for f ADCK K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 723 3. The result of the conversion is transferred to Rn upon completion of the conversion algorithm. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 724 27 ADCK cycles 10b single-ended 20 ADCK cycles 11b differential 30 ADCK cycles 12b single-ended 20 ADCK cycles 13b differential 30 ADCK cycles Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 725 • 10-bit mode, with the bus clock selected as the input clock source • The input clock divide-by-1 ratio selected • Bus frequency of 8 MHz • Long sample time disabled • High-speed conversion disabled K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 726 Figure 33-92. Table 33-110. Typical conversion time Variable Time SFCAdder 3 ADCK cycles + 5 bus clock cycles AverageNum 34 ADCK cycles LSTAdder 20 ADCK cycles HSCAdder K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 727 When hardware averaging is selected, the completion of a single conversion will not set SC1n[COCO]. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 728: Automatic Compare Function
CV2. Greater than Outside range, inclusive Compare true if the result is greater than or equal to CV1 Or the result is less than or equal to CV2. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 729: Calibration Function
Prior to calibration, the user must configure the ADC's clock source and frequency, low power configuration, voltage reference selection, sample time, and high speed configuration according to the application's clock source availability and needs. If the K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 730 When calibration is complete, the user may reconfigure and use the ADC as desired. A second calibration may also be performed, if desired, by clearing and again setting SC3[CAL]. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 731: User-Defined Offset Function
ADC error specifications may not be met. Storing the value generated by the calibration function in memory before overwriting with a user- specified value is recommended. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 732: Temperature Sensor
• m is referred as temperature sensor slope in the device data sheet. It is the hot or cold voltage versus temperature slope in V/°C. For temperature calculations, use the V and temperature sensor slope values from TEMP25 the ADC Electricals table. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 733: Mcu Wait Mode Operation
33.4.10 MCU Normal Stop mode operation Stop mode is a low-power consumption Standby mode during which most or all clock sources on the MCU are disabled. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 734: Mcu Low-Power Stop Mode Operation
Therefore, the module must be re-enabled and re-configured following exit from Low-Power Stop mode. NOTE For the chip specific modes of operation, see the power management information for the device. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 735: Initialization Information
5. Update SC1:SC1n registers to select whether conversions will be single-ended or differential and to enable or disable conversion complete interrupts. Also, select the input channel which can be used to perform conversions. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 736 Bit 4:0 ADCH 00001 Input channel 1 selected as ADC input channel. RA = 0xxx Holds results of conversion. CV = 0xxx Holds compare value when compare function enabled. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 737: Application Information
33.6.1 External pins and routing 33.6.1.1 Analog supply pins Depending on the device, the analog power and ground supplies, V and V , of the ADC module are available as: K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 738 V and V loop. The REFH REFL best external component to meet this current demand is a 0.1 μF capacitor with good K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 739: Sources Of Error
RAS + RADIN =SC / (FMAX * NUMTAU * CADIN) Figure 33-95. Sampling equation Where: RAS = External analog source resistance SC = Number of ADCK cycles used during sample window K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 740 REFL plane. • Operate the MCU in Wait or Normal Stop mode before initiating (hardware-triggered conversions) or immediately after initiating (hardware- or software-triggered conversions) the ADC conversion. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 741 12-bit modes. As a consequence, however, the code width of the first (0x000) conversion is only 1/2 LSB and the code width of the last (0xFF or 0x3FF) is 1.5 LSB. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 742 However, even small amounts of system noise can cause the converter to be indeterminate, between two codes, for a range of input voltages around the transition voltage. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 743 • Missing codes: Missing codes are those values never converted for any input value. In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and have no missing codes. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 744 Application information K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 745: Comparator (Cmp)
34.1.1 CMP features The CMP has the following features: • Operational over the entire supply range • Inputs may range from rail to rail • Programmable hysteresis control K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 746: 6-Bit Dac Key Features
• 6-bit resolution • Selectable supply reference source • Power Down mode to conserve power when not in use • Option to route the output to internal comparator input K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 747: Cmp, Dac And Anmux Diagram
• Two 8-to-1 channel mux • Operational over the entire supply range 34.1.4 CMP, DAC and ANMUX diagram The following figure shows the block diagram for the High-Speed Comparator, DAC, and ANMUX modules. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 748: Cmp Block Diagram
ANMUX and filter control CMPO MSEL[2:0] Figure 34-1. CMP, DAC and ANMUX block diagram 34.1.5 CMP block diagram The following figure shows the block diagram for the CMP module. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 749 CR0[FILTER_CNT] is set greater than 0x01. • If CR1[SE] = 1, the external SAMPLE input is used as sampling clock • If CR1[SE] = 0, the divided bus clock is used as sampling clock K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 750: Memory Map/Register Definitions
Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. 6–4 Filter Sample Count FILTER_CNT Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 751: Cmp Control Register 1 (Cmpx_Cr1)
WE is cleared. However, avoid writing 1s to both field locations because this "11" case is reserved and may change in future implementations. Sampling mode is not selected. Sampling mode is selected. Windowing Enable Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 752 When the user selects the same input from analog mux to the positive and negative port, the comparator is disabled automatically. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 753: Cmp Filter Period Register (Cmpx_Fpr)
Enables the DMA transfer triggered from the CMP module. When this field is set, a DMA request is asserted when CFR or CFF is set. DMA is disabled. DMA is enabled. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 754: Dac Control Register (Cmpx_Daccr)
CMPx_DACCR field descriptions Field Description DAC Enable DACEN Enables the DAC. When the DAC is disabled, it is powered down to conserve power. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 755: Mux Control Register (Cmpx_Muxcr)
MSEL Determines which input is selected for the minus input of the comparator. For INx inputs, see CMP, DAC, and ANMUX block diagrams. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 756: Functional Description
The external sample input is enabled using CR1[SE]. When set, the output of the comparator is sampled only on rising edges of the sample input. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 757 SAMPLE=1 to generate COUTA, which is then resampled and filtered to generate COUT. See the Windowed/Filtered mode (#7). All other combinations of CR1[EN], CR1[WE], CR1[SE], CR0[FILTER_CNT], and FPR[FILT_PER] are illegal. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 758 CMPO COUT To other system functions WINDOW/SAMPLE bus clock Clock COUTA CMPO to prescaler divided FILT_PER CGMUX clock Figure 34-21. Comparator operation in Continuous mode K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 759 In Sampled, Non-Filtered mode, the analog comparator block is powered and active. The path from analog inputs to COUTA is combinational unclocked. Windowing control is completely bypassed. COUTA is sampled whenever a rising-edge is detected on the filter block clock input. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 760 COUTA is sampled whenever a rising edge is detected on the filter block clock input. The only difference in operation between Sampled, Non-Filtered (# 3A) and Sampled, Filtered (# 4A) is that, now, CR0[FILTER_CNT]>1, which activates filter operation. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 761 CMPO COUT To other SOC functions WINDOW/SAMPLE bus clock Clock COUTA CMPO to prescaler divided FILT_PER CGMUX clock SE=1 Figure 34-24. Sampled, Filtered (# 4A): sampling point externally driven K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 762 WINDOW signal is high. In actual operation, COUTA may lag the analog inputs by up to one bus clock cycle plus the combinational path delay through the comparator and polarity select logic. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 763 COUTA CMPO to divided prescaler FILT_PER CGMUX clock SE=0 Figure 34-27. Windowed mode For control configurations which result in disabling the filter block, see Filter Block Bypass Logic diagram. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 764 Configuration for this mode is virtually identical to that for the Windowed/Filtered Mode shown in the next section. The only difference is that the value of CR0[FILTER_CNT] must be 1. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 765: Power Modes
Figure 34-29. Windowed/Filtered mode 34.3.2 Power modes 34.3.2.1 Wait mode operation During Wait and VLPW modes, the CMP, if enabled, continues to operate normally and a CMP interrupt can wake the MCU. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 766: Startup And Operation
The filter delay is specified in the Low-pass filter. • During operation, the propagation delay of the selected data paths must always be considered. It may take many bus clock cycles for COUT and SCR[CFR]/SCR[CFF] K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 767: Low-Pass Filter
In other words, SCR[COUT] will be 0 for some initial period, even when COUTA is at logic 1. Setting both CR1[SE] and FPR[FILT_PER] to 0 disables the filter and eliminates switching current associated with the filtering process. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 768 Sampled, Filtered mode + (CR0[FILTER_CNT] * ) + T SAMPLE > 0x01 > 0x00 + (CR0[FILTER_CNT] * FPR[FILT_PER] x T ) + T Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 769: Cmp Interrupts
DMA transfer request and clears the flag to allow a subsequent change on comparator output to occur and force another DMA request. The comparator can remain functional in STOP modes. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 770: Cmp Asynchronous Dma Support
STOP modes. After the data transfer has finished, system will go back to STOP modes. Refer to DMA chapters in the device reference manual for the asynchronous DMA function for details. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 771: Digital-To-Analog Converter
34.8.1 Voltage reference source select • V connects to the primary voltage source as supply reference of 64 tap resistor ladder • V connects to an alternate voltage source K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 772: Dac Resets
This module has a single reset input, corresponding to the chip-wide peripheral reset. 34.10 DAC clocks This module has a single clock input, the bus clock. 34.11 DAC interrupts This module has no interrupts. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 773: 12-Bit Digital-To-Analog Converter (Dac)
• Static operation in Normal Stop mode • 16-word data buffer supported with configurable watermark and multiple operation modes • DMA support 35.3 Block diagram The block diagram of the DAC module is as follows: K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 774: Memory Map/Register Definition
DACBBIEN DACBFMD DACTRGSE Figure 35-1. DAC block diagram 35.4 Memory map/register definition The DAC has registers to control analog comparator and programmable voltage divider to perform the digital-to-analog functions. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 775 DAC Data High Register (DAC0_DAT15H) 35.4.2/776 4003_F020 DAC Status Register (DAC0_SR) 35.4.3/777 4003_F021 DAC Control Register (DAC0_C0) 35.4.4/778 4003_F022 DAC Control Register 1 (DAC0_C1) 35.4.5/779 4003_F023 DAC Control Register 2 (DAC0_C2) 35.4.6/780 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 776: Dac Data Low Register (Dacx_Datnl)
When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage based on the following formula. V * (1 + DACDAT0[11:0])/4096 When the DAC buffer is enabled, DATA[11:0] is mapped to the 16-word buffer. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 777: Dac Status Register (Dacx_Sr)
DAC trigger making the DAC read pointer increase. Write to this bit is ignored in FIFO mode. The DAC buffer read pointer is not equal to C2[DACBFUP]. The DAC buffer read pointer is equal to C2[DACBFUP]. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 778: Dac Control Register (Dacx_C0)
The DAC buffer read pointer top flag interrupt is disabled. The DAC buffer read pointer top flag interrupt is enabled. DAC Buffer Read Pointer Bottom Flag Interrupt Enable DACBBIEN Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 779: Dac Control Register 1 (Dacx_C1)
Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 780: Dac Control Register 2 (Dacx_C2)
When both the DAC and the buffer are enabled, the DAC converts the data in the data buffer to analog output voltage. The data buffer read pointer advances to the next word whenever any hardware or software trigger event occurs. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 781 NOTE: If the software set the read pointer to the upper limit, the read pointer will not advance in this mode. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 782: Dma Operation
The status register flags are still set and are cleared automatically when the DMA completes. 35.5.3 Resets During reset, the DAC is configured in the default mode and is disabled. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 783 In low-power stop modes, the DAC is fully shut down. NOTE The assignment of module modes to core modes is chip- specific. For module-to-core mode assignments, see the chapter that describes how modules are configured. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 784 Functional description K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 785: Voltage Reference (Vrefv1)
ADC, DAC, or CMP. The voltage reference has three operating modes that provide different levels of supply rejection and power consumption.. The following figure is a block diagram of the Voltage Reference. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 786: Overview
The Voltage Reference has the following features: • Programmable trim register with 0.5 mV steps, automatically loaded with factory trimmed value upon reset • Programmable buffer mode selection: • Off K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 787: Modes Of Operation
The following table shows the Voltage Reference signals properties. Table 36-1. VREF Signal Descriptions Signal Description VREF_OUT Internally-generated Voltage Reference output NOTE When the VREF output buffer is disabled, the status of the VREF_OUT signal is high-impedence. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 788: Memory Map And Register Definition
NOTE: Min = minimum and max = maximum voltage reference output. For minimum and maximum voltage reference output values, refer to the Data Sheet for this chip. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 789: Vref Status And Control Register (Vref_Sc)
Internal 1.75 V regulator is enabled. Second order curvature compensation enable ICOMPEN This bit should be written to 1 to achieve the performance stated in the data sheet. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 790: Functional Description
100 nF capacitor is required. Voltage Reference enabled, VREF_OUT available for low power buffer on internal and external use. 100 nF capacitor is required. Reserved Reserved K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 791: Voltage Reference Disabled, Sc[Vrefen] = 0
(Tstup) and the value is specified in the appropriate device data sheet. If this mode is entered when the VREF module is enabled then you must wait the longer of K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 792: Internal Voltage Regulator
1. Enable the chop oscillator (VREF_TRM[CHOPEN] = 1) 2. Configure the VREF_SC register to the desired settings with the internal regulator disabled, VREF_SC[REGEN] = 0 3. Wait > 300ns K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 793: Initialization/Application Information
The TRM[CHOPEN], SC[REGEN] and SC[ICOMPEN] bits must be written to 1 to achieve the performance stated in the device data sheet. NOTE See section "Internal voltage regulator" for details on the required sequence to enable the internal regulator. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 794 Initialization/Application Information K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 795: Introduction
• Trigger outputs can be enabled or disabled independently • One 16-bit delay register per pre-trigger output • Optional bypass of the delay registers of the pre-trigger outputs • Operation in One-Shot or Continuous modes K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 796: Implementation
• y—Pulse-Out number, valid value is from 0 to Y-1. NOTE The number of module output triggers to core is chip-specific. For module to core output triggers implementation, see the chip configuration information. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 797: Programmable Delay Block (Pdb)
37.1.4 DAC External Trigger Input Connections The implementation of DAC external trigger inputs is chip-specific. See the chip configuration information for details. 37.1.5 Block diagram This diagram illustrates the major components of the PDB. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 798 In this diagram, only one PDB channel n, one DAC interval trigger x, and one Pulse-Out y are shown. The PDB-enabled control logic and the sequence error interrupt logic are not shown. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 799: Modes Of Operation
If the PDB is enabled and external trigger input source is selected, a positive edge on the EXTRG signal resets and starts the counter. 37.3 Memory map and register definition K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 800 DAC Interval n register (PDB0_DACINT0) 0000_0000h 37.3.11/ 4003_6190 Pulse-Out n Enable register (PDB0_POEN) 0000_0000h 37.3.12/ 4003_6194 Pulse-Out n Delay register (PDB0_PO0DLY) 0000_0000h 37.3.12/ 4003_6198 Pulse-Out n Delay register (PDB0_PO1DLY) 0000_0000h K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 801: Status And Control Register (Pdbx_Sc)
Enables the PDB sequence error interrupt. When this field is set, any of the PDB channel sequence error flags generates a PDB sequence error interrupt. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 802 Trigger-In 11 is selected. 1100 Trigger-In 12 is selected. 1101 Trigger-In 13 is selected. 1110 Trigger-In 14 is selected. 1111 Software trigger is selected. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 803: Modulus Register (Pdbx_Mod)
1. It is automatically cleared when the values in buffers are loaded into the internal registers or the PDBEN is cleared. Writing 0 to it has no effect. 37.3.2 Modulus register (PDBx_MOD) Address: 4003_6000h base + 4h offset = 4003_6004h Reset K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 804: Counter Register (Pdbx_Cnt)
Specifies the delay value to schedule the PDB interrupt. It can be used to schedule an independent interrupt at some point in the PDB cycle. If enabled, a PDB interrupt is generated, when the counter is Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 805: Channel N Control Register 1 (Pdbx_Chnc1)
PDB Channel Pre-Trigger Enable These bits enable the PDB ADC pre-trigger outputs. Only lower M pre-trigger bits are implemented in this MCU. PDB channel's corresponding pre-trigger disabled. PDB channel's corresponding pre-trigger enabled. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 806: Channel N Status Register (Pdbx_Chns)
Specifies the delay value for the channel's corresponding pre-trigger. The pre-trigger asserts when the counter is equal to DLY. Reading this field returns the value of internal register that is effective for the current PDB cycle. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 807: Channel N Delay 1 Register (Pdbx_Chndly1)
1. DAC external trigger input enabled. DAC interval counter is bypassed and DAC external trigger input triggers the DAC interval trigger. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 808: Dac Interval N Register (Pdbx_Dacintn)
This read-only field is reserved and always has the value 0. 7–0 PDB Pulse-Out Enable POEN Enables the pulse output. Only lower Y bits are implemented in this MCU. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 809: Pulse-Out N Delay Register (Pdbx_Pondly)
1. For each channel, a delay m determines the time between assertion of the trigger input event to the time at which changes in the pre-trigger m output signal are started. The time is defined as: K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 810 2 peripheral cycles after the acknowledgment m is received. The acknowledgment connections in this MCU are described in Back-to-back acknowledgment connections. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 811: Pdb Trigger Input Source Selection
PDB can generate pulse outputs of configurable width. When PDB counter reaches the value set in POyDLY[DLY1], the Pulse-Out goes high; when the counter reaches POyDLY[DLY2], it goes low. POyDLY[DLY2] can be set either greater or less than POyDLY[DLY1]. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 812: Updating The Delay Registers
The following diagrams show the cases of the internal registers being updated with SC[LDMOD] is 00 and x1. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 813: Interrupts
SC[PDBEIE] = 1 37.4.6 DMA If SC[DMAEN] is set, PDB can generate a DMA transfer request when SC[PDBIF] is set. When DMA is enabled, the PDB interrupt is not issued. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 814: Application Information
If the applications need a really long delay value and use a prescaler set to 128, then the resolution would be limited to 128 peripheral clock cycles. Therefore, use the lowest possible prescaler and multiplication factor for a given application. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 815: Introduction
All of the features common with the TPM have fully backwards compatible register assignments. The FlexTimer can also use code on the same core platform without change to perform the same functions. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 816: Features
• It can be a free-running counter or a counter with initial and final value • The counting can be up or up-down • Each channel can be configured for input capture, output compare, or edge-aligned PWM mode • In Input Capture mode: K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 817: Flextimer Module (Ftm)
FTM is effectively disabled until clocks resume. During Wait mode, the FTM continues to operate normally. If the FTM does not need to produce a K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 818: Block Diagram
The following figure shows the FTM structure. The central component of the FTM is the 16-bit counter with programmable initial and final values and its counting can be up or up-down. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 819 7 and polarity control) mode logic input DECAPEN CH7F channel 7 COMBINE3 channel 7 interrupt CPWMS CH7TRIG match trigger CH7IE MS7B:MS7A ELS7B:ELS7A Figure 38-1. FTM block diagram K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 820: Ftm Signal Descriptions
This section presents a high-level summary of the FTM registers and how they are mapped. The registers and bits of an unavailable function in the FTM remain in the memory map and in the reset value, but they have no active function. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 821: Register Descriptions
Features Mode Selection (FTM0_MODE) 0000_0004h 38.3.11/ 4003_8058 Synchronization (FTM0_SYNC) 0000_0000h 38.3.12/ 4003_805C Initial State For Channels Output (FTM0_OUTINIT) 0000_0000h 38.3.13/ 4003_8060 Output Mask (FTM0_OUTMASK) 0000_0000h Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 822 4003_902C Channel (n) Status And Control (FTM1_C4SC) 0000_0000h 38.3.6/829 4003_9030 Channel (n) Value (FTM1_C4V) 0000_0000h 38.3.7/832 4003_9034 Channel (n) Status And Control (FTM1_C5SC) 0000_0000h 38.3.6/829 Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 823 0000_0000h 38.3.24/ 4003_908C Synchronization Configuration (FTM1_SYNCONF) 0000_0000h 38.3.25/ 4003_9090 FTM Inverting Control (FTM1_INVCTRL) 0000_0000h 38.3.26/ 4003_9094 FTM Software Output Control (FTM1_SWOCTRL) 0000_0000h 38.3.27/ 4003_9098 FTM PWM Load (FTM1_PWMLOAD) 0000_0000h K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 824 4003_A06C FTM External Trigger (FTM2_EXTTRIG) 0000_0000h 38.3.17/ 4003_A070 Channels Polarity (FTM2_POL) 0000_0000h 38.3.18/ 4003_A074 Fault Mode Status (FTM2_FMS) 0000_0000h 38.3.19/ 4003_A078 Input Capture Filter Control (FTM2_FILTER) 0000_0000h Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 825 0000_0000h 38.3.24/ 4003_A08C Synchronization Configuration (FTM2_SYNCONF) 0000_0000h 38.3.25/ 4003_A090 FTM Inverting Control (FTM2_INVCTRL) 0000_0000h 38.3.26/ 4003_A094 FTM Software Output Control (FTM2_SWOCTRL) 0000_0000h 38.3.27/ 4003_A098 FTM PWM Load (FTM2_PWMLOAD) 0000_0000h K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 826: Status And Control (Ftmx_Sc)
TOF remains set indicating an overflow has occurred. In this case, a TOF interrupt request is not lost due to the clearing sequence for a previous TOF. FTM counter has not overflowed. FTM counter has overflowed. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 827: Counter (Ftmx_Cnt)
Reset clears the CNT register. Writing any value to COUNT updates the counter with its initial value, CNTIN. When BDM is active, the FTM counter is frozen. This is the value that you may read. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 828: Modulo (Ftmx_Mod)
Address: Base address + 8h offset Reserved Reset FTMx_MOD field descriptions Field Description 31–16 This field is reserved. Reserved 15–0 Modulo Value K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 829: Channel (N) Status And Control (Ftmx_Cnsc)
(set on channel (n) match, and clear on channel (n+1) match) Low-true pulses (clear on channel (n) match, and set on channel (n +1) match) Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 830 Enabled Falling edge Enabled Rising and falling edges Address: Base address + Ch offset + (8d × i), where i=0d to 7d Reset CHIE MSB MSA ELSB ELSA Reset K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 831 FTM counter is not reset when the selected channel (n) input event is detected. FTM counter is reset when the selected channel (n) input event is detected. DMA Enable Enables DMA transfers for the channel. Disable DMA transfers. Enable DMA transfers. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 832: Channel (N) Value (Ftmx_Cnv)
FTM clock, write the new value to the the CNTIN register and then initialize the FTM counter by writing any value to the CNT register. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 833: Capture And Compare Status (Ftmx_Status)
CHnF remains set indicating an event has occurred. In this case, a CHnF interrupt request is not lost due to the clearing sequence for a previous CHnF. Address: Base address + 50h offset Reset K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 834 CH3F See the register description. No channel event has occurred. A channel event has occurred. Channel 2 Flag CH2F See the register description. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 835: Features Mode Selection (Ftmx_Mode)
• PWM synchronization • Write protection • Channel output initialization These controls relate to all channels within this module. Address: Base address + 54h offset Reset FAULTM INIT Reset K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 836 The INIT bit is always read as 0. FTM Enable FTMEN This field is write protected. It can be written only when MODE[WPDIS] = 1. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 837: Synchronization (Ftmx_Sync)
The synchronization event selection also depends on the PWMSYNC (MODE register) and SYNCMODE (SYNCONF register) bits. See synchronization. Address: Base address + 58h offset Reset K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 838 The REINIT bit configures the synchronization when SYNCMODE is zero. FTM counter continues to count normally. FTM counter is updated with its initial value when the selected trigger is detected. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 839: Initial State For Channels Output (Ftmx_Outinit)
Selects the value that is forced into the channel output when the initialization occurs. The initialization value is 0. The initialization value is 1. Channel 6 Output Initialization Value CH6OI Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 840: Output Mask (Ftmx_Outmask)
This feature is used for BLDC control where the PWM signal is presented to an electric motor at specific times to provide electronic commutation. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 841 Channel output is masked. It is forced to its inactive state. Channel 3 Output Mask CH3OM Defines if the channel output is masked or unmasked. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 842: Function For Linked Channels (Ftmx_Combine)
Dual Edge Capture mode, Complementary, and Combine mode for each pair of channels (n) and (n+1), where n equals 0, 2, 4, and 6. Address: Base address + 64h offset Reset Reset K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 843 The channel (n+1) output is the same as the channel (n) output. The channel (n+1) output is the complement of the channel (n) output. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 844 The Dual Edge Capture mode in this pair of channels is disabled. The Dual Edge Capture mode in this pair of channels is enabled. Complement Of Channel (n) For n = 4 COMP2 Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 845 Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in Dual Edge Capture mode according to Table 38-7. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 846 DECAP bit is cleared automatically by hardware if dual edge capture – one-shot mode is selected and when the capture of channel (n+1) event is made. The dual edge captures are inactive. The dual edge captures are active. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 847: Deadtime Insertion Control (Ftmx_Deadtime)
Selects the division factor of the system clock. This prescaled clock is used by the deadtime counter. This field is write protected. It can be written only when MODE[WPDIS] = 1. Divide the system clock by 1. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 848: Ftm External Trigger (Ftmx_Exttrig)
Several channels can be selected to generate multiple triggers in one PWM period. Channels 6 and 7 are not used to generate channel triggers. Address: Base address + 6Ch offset Reserved Reset K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 849 Enables the generation of the channel trigger when the FTM counter is equal to the CnV register. The generation of the channel trigger is disabled. The generation of the channel trigger is enabled. Channel 5 Trigger Enable CH5TRIG Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 850: Channels Polarity (Ftmx_Pol)
That is, the safe value of a channel is the value of its POL bit. Address: Base address + 70h offset Reserved Reset Reserved POL7 POL6 POL5 POL4 POL3 POL2 POL1 POL0 Reset K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 851 Channel 1 Polarity POL1 Defines the polarity of the channel output. This field is write protected. It can be written only when MODE[WPDIS] = 1. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 852: Fault Mode Status (Ftmx_Fms)
38.3.18 Fault Mode Status (FTMx_FMS) This register contains the fault detection flags, write protection enable bit, and the logic OR of the enabled fault inputs. Address: Base address + 74h offset Reset Reset K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 853 Writing a 1 to FAULTF2 has no effect. FAULTF2 bit is also cleared when FAULTF bit is cleared. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 854: Input Capture Filter Control (Ftmx_Filter)
Writing to the FILTER register has immediate effect and must be done only when the channels 0, 1, 2, and 3 are not in input modes. Failure to do this could result in a missing valid signal. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 855: Fault Control (Ftmx_Fltctrl)
38.3.20 Fault Control (FTMx_FLTCTRL) This register selects the filter value for the fault inputs, enables the fault inputs and the fault inputs filter. Address: Base address + 7Ch offset Reset FFVAL Reset K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 856 Enables the fault input. This field is write protected. It can be written only when MODE[WPDIS] = 1. Fault input is disabled. Fault input is enabled. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 857 Fault Input 0 Enable FAULT0EN Enables the fault input. This field is write protected. It can be written only when MODE[WPDIS] = 1. Fault input is disabled. Fault input is enabled. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 858: Quadrature Decoder Control And Status (Ftmx_Qdctrl)
CH0FVAL field of FILTER. The phase A filter is also disabled when CH0FVAL is zero. Phase A input filter is disabled. Phase A input filter is enabled. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 859 The Quadrature Decoder mode has precedence over the other modes. See Table 38-7. This field is write protected. It can be written only when MODE[WPDIS] = 1. Quadrature Decoder mode is disabled. Quadrature Decoder mode is enabled. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 860: Configuration (Ftmx_Conf)
Selects the FTM behavior in BDM mode. See mode. This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 861: Ftm Fault Input Polarity (Ftmx_Fltpol)
Fault Input 2 Polarity FLT2POL Defines the polarity of the fault input. This field is write protected. It can be written only when MODE[WPDIS] = 1. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 862: Synchronization Configuration (Ftmx_Synconf)
Reset FTMx_SYNCONF field descriptions Field Description 31–21 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 863 The software trigger activates the FTM counter synchronization. Synchronization Mode SYNCMODE Selects the PWM Synchronization mode. Legacy PWM synchronization is selected. Enhanced PWM synchronization is selected. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 864: Ftm Inverting Control (Ftmx_Invctrl)
This register has a write buffer. The INVmEN bit is updated by the INVCTRL register synchronization. Address: Base address + 90h offset Reset K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 865: Ftm Software Output Control (Ftmx_Swoctrl)
• The CHnOCV bits select the value that is forced at the corresponding channel (n) output. This register has a write buffer. The fields are updated by the SWOCTRL register synchronization. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 866 The software output control forces 0 to the channel output. The software output control forces 1 to the channel output. Channel 0 Software Output Control Value CH0OCV Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 867 The channel output is affected by software output control. Channel 0 Software Output Control Enable CH0OC The channel output is not affected by software output control. The channel output is affected by software output control. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 868: Ftm Pwm Load (Ftmx_Pwmload)
Include the channel in the matching process. Channel 5 Select CH5SEL Do not include the channel in the matching process. Include the channel in the matching process. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 869: Functional Description
Include the channel in the matching process. 38.4 Functional description The notation used in this document to represent the counters and the generation of the signals is shown in the following figure. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 870: Clock Source
Refer to the chip specific documentation for further information. Due to FTM hardware implementation limitations, the frequency of the fixed frequency clock must not exceed 1/2 of the system clock frequency. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 871: Prescaler
The FTM counter has these modes of operation: • Up counting • Up-down counting • Quadrature Decoder mode 38.4.3.1 Up counting Up counting is selected when: • QUADEN = 0, and • CPWMS = 0 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 872 FTM counting is up and signed. CNTIN[15] = 0 and CNTIN ≠ 0x0000 The initial value of the FTM counter is a positive number, so the FTM counting is up and unsigned. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 873 FTM operation difficult to comprehend. However, there is no restriction on this configuration, and an example is shown in the following figure. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 874 The TOF bit is set when the FTM counter changes from MOD to (MOD – 1). If (CNTIN = 0x0000), the FTM counting is equivalent to TPM up-down counting, that is, up-down and unsigned counting. See the following figure. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 875 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 TOF bit set TOF bit Figure 38-172. Example when the FTM counter is free running The FTM counter is also a free running counter when: K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 876 FTM counter NUMTOF[4:0] 0x02 TOF counter 0x01 0x02 0x00 0x01 0x02 0x00 0x01 0x02 set TOF bit Figure 38-173. Periodic TOF when NUMTOF = 0x02 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 877: Input Capture Mode
While in BDM, the input capture function works as configured. When a selected edge event occurs, the FTM counter value, which is frozen because of BDM, is captured into the CnV register and the CHnF bit is set. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 878 As long as the new state is stable on the input, the counter continues to increment. When the counter is equal to CHnFVAL[3:0], the state change of the input signal is validated. It is then transmitted as a pulse edge to the edge detector. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 879 The figure below shows the FTM counter reset when the selected input capture event is detected in a channel in input capture mode with ICRST = 1. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 880: Output Compare Mode
The CHnF bit is set and the channel (n) interrupt is generated if CHnIE = 1 at the channel (n) match (FTM counter = CnV). K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 881: Edge-Aligned Pwm (Epwm) Mode
CHnF bit is set and the channel (n) interrupt is generated if CHnIE = 1, however the channel (n) output is not modified and controlled by FTM. 38.4.6 Edge-Aligned PWM (EPWM) mode The Edge-Aligned mode is selected when: • QUADEN = 0 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 882 CNTIN register value is loaded into the FTM counter, and it is forced high at the channel (n) match (FTM counter = CnV). See the following figure. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 883: Center-Aligned Pwm (Cpwm) Mode
0x0001 to 0x7FFF because values outside this range can produce ambiguous results. In the CPWM mode, the FTM counter counts up until it reaches MOD and then counts down until it reaches CNTIN. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 884 If (ELSnB:ELSnA = X:1), then the channel (n) output is forced low at the channel (n) match (FTM counter = CnV) when counting down, and it is forced high at the channel (n) match when counting up. See the following figure. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 885: Combine Mode
(n) match (FTM counter = C(n)V). The CH(n+1)F bit is set and the channel (n +1) interrupt is generated, if CH(n+1)IE = 1, at the channel (n+1) match (FTM counter = C(n+1)V). K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 886 ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 Figure 38-189. Channel (n) output if (CNTIN < C(n)V < MOD) and (CNTIN < C(n+1)V < MOD) and (C(n)V < C(n+1)V) K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 887 (n) output with ELSnB:ELSnA = X:1 Figure 38-192. Channel (n) output if (CNTIN < C(n)V < MOD) and (C(n)V is Almost Equal to CNTIN) and (C(n+1)V = MOD) K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 888 ELSnB:ELSnA = 1:0 channel (n) output 100% duty cycle with ELSnB:ELSnA = X:1 Figure 38-194. Channel (n) output if C(n)V and C(n+1)V are not between CNTIN and MOD K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 889 (n) output 0% duty cycle with ELSnB:ELSnA = 1:0 channel (n) output 100% duty cycle with ELSnB:ELSnA = X:1 Figure 38-197. Channel (n) output if (C(n)V = C(n+1)V = MOD) K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 890 ELSnB:ELSnA = 1:0 channel (n) output 100% duty cycle with ELSnB:ELSnA = X:1 Figure 38-199. Channel (n) output if (C(n)V < CNTIN) and (CNTIN < C(n+1)V < MOD) K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 891 ELSnB:ELSnA = 1:0 channel (n) output 100% duty cycle with ELSnB:ELSnA = X:1 Figure 38-201. Channel (n) output if (C(n)V > MOD) and (CNTIN < C(n+1)V < MOD) K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 892: Complementary Mode
(n+1) match occurs, that is, FTM counter = C(n+1)V. So, Combine mode allows the generation of asymmetrical PWM signals. 38.4.9 Complementary mode The Complementary mode is selected when: K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 893: Registers Updated From Write Buffers
Figure 38-205. Channel (n+1) output in Complementary mode with (ELSnB:ELSnA = X:1) NOTE The complementary mode is not available in Output Compare mode. 38.4.10 Registers updated from write buffers K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 894 Table 38-245. CnV register update When Then CnV register is updated CLKS[1:0] = 0:0 When CnV register is written, independent of FTMEN bit. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 895: Pwm Synchronization
The PWM synchronization with hardware trigger is initiated when a rising edge is detected at the enabled hardware trigger inputs. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 896 PWMSYNC and REINIT bits. In this case if (PWMSYNC = 1) or (PWMSYNC = 0 and REINIT = 0) then SWSYNC bit is cleared at the next selected loading point after that the K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 897 For both counting modes, if neither CNTMIN nor CNTMAX are 1, then the boundary cycles are not used as loading points for registers updates. See the register synchronization descriptions in the following sections for details. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 898 = 0). However, it is expected that the MOD register be synchronized only by the enhanced PWM synchronization. In the case of enhanced PWM synchronization, the MOD register synchronization depends on SWWRBUF, SWRSTCNT, HWWRBUF, and HWRSTCNT bits according to this flowchart: K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 899 If the trigger event was a software trigger, then the SWSYNC bit is cleared on the next selected K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 900 SWSYNC bit is cleared according to the following example. If the trigger event was a hardware trigger, then the TRIGn bit is cleared according to Hardware trigger. Examples with software and hardware triggers follow. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 901 1 to SWSYNC bit SWSYNC bit software trigger event selected loading point MOD register is updated Figure 38-214. MOD synchronization with (SYNCMODE = 0) and (PWMSYNC = 1) K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 902 SYNCMODE = 0). However, it is expected that the OUTMASK register be synchronized only by the enhanced PWM synchronization. In the case of enhanced PWM synchronization, the OUTMASK register synchronization depends on SWOM and HWOM bits. See the following flowchart: K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 903 Figure 38-215. OUTMASK register synchronization flowchart In the case of legacy PWM synchronization, the OUTMASK register synchronization depends on PWMSYNC bit according to the following description. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 904 If (SYNCMODE = 0), (SYNCHOM = 1), and (PWMSYNC = 1), then this synchronization is made on the next enabled hardware trigger. The TRIGn bit is cleared according to Hardware trigger. An example with a hardware trigger follows. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 905 PWM synchronization (INVC = 1 and SYNCMODE = 1) according to the following flowchart. In the case of enhanced PWM synchronization, the INVCTRL register synchronization depends on SWINVC and HWINVC bits. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 906 HWTRIGMODE bit ? clear TRIGn bit Figure 38-219. INVCTRL register synchronization flowchart 38.4.11.9 SWOCTRL register synchronization The SWOCTRL register synchronization updates the SWOCTRL register with its buffer value. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 907 ? wait hardware trigger n update SWOCTRL with its buffer value update SWOCTRL with its buffer value HWTRIGMODE bit ? clear TRIGn bit Figure 38-220. SWOCTRL register synchronization flowchart K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 908 = 0). However, the FTM counter must be synchronized only by the enhanced PWM synchronization. In the case of enhanced PWM synchronization, the FTM counter synchronization depends on SWRSTCNT and HWRSTCNT bits according to the following flowchart. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 909 SWSYNC bit is cleared according to the following example. If the trigger event was a hardware trigger then the TRIGn bit is cleared according to Hardware trigger. Examples with software and hardware triggers follow. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 910 Figure 38-225. FTM counter synchronization with (SYNCMODE = 0), (HWTRIGMODE = 0), (REINIT = 1), (PWMSYNC = 1), and a hardware trigger was used K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 911: Inverting
INV(m) bit selects the inverting to the pair channels (n) and (n+1). Figure 38-226. Channels (n) and (n+1) outputs after the inverting in High-True (ELSnB:ELSnA = 1:0) Combine mode K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 912: Software Output Control
PWM generation. The software output control is selected when: • QUADEN = 0 • DECAPEN = 0, and • CHnOC = 1 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 913 Software output control forces the following values on channels (n) and (n+1) when the COMP bit is one. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 914: Deadtime Insertion
(FTM counter = C(n)V) occurs, the channel (n) output remains at the high value until the end of the deadtime delay when the channel (n) output is cleared. Similarly, K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 915 Figure 38-230. Deadtime insertion with ELSnB:ELSnA = X:1, POL(n) = 0, and POL(n+1) = NOTE • The deadtime feature must be used only in Complementary mode. • The deadtime feature is not available in Output Compare mode. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 916 Figure 38-231. Example of the deadtime insertion (ELSnB:ELSnA = 1:0, POL(n) = 0, and POL(n+1) = 0) when the deadtime delay is comparable to channel (n+1) duty cycle K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 917: Output Mask
If CHnOM = 1, then the channel (n) output is forced to its inactive state (POLn bit value). If CHnOM = 0, then the channel (n) output is unaffected by the output mask. See the following figure. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 918: Fault Control
When there is a state change in the fault input n signal, the 5-bit counter is reset and starts counting up. As long as the new state is stable on the fault input n, the K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 919 1 value FAULTIN fault input 2 value fault input 3 value FAULTIE fault interrupt FAULTF0 FAULTF1 FAULTF FAULTF2 FAULTF3 Figure 38-235. FAULTF and FAULTIN bits and fault interrupt K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 920 FAULTF bit is cleared NOTE The channel (n) output is after the fault control with automatic fault clearing and POLn = 0. Figure 38-236. Fault control with automatic fault clearing K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 921: Polarity Control
• If FLTjPOL = 1, the fault j input polarity is low, so the logical zero at the fault input j indicates a fault. 38.4.17 Polarity control The POLn bit selects the channel (n) output polarity: K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 922: Initialization
See the description of the CLKS field in the Status and Control register. 38.4.19 Features priority The following figure shows the priority of the features used at the generation of channels (n) and (n+1) outputs signals. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 923: Channel Trigger Output
If CHjTRIG = 1, where j = 0, 1, 2, 3, 4, or 5, then the FTM generates a trigger when the channel (j) match occurs (FTM counter = C(j)V). The channel trigger output provides a trigger signal that is used for on-chip modules. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 924: Initialization Trigger
• The FTM counter is automatically updated with the CNTIN register value by the selected counting mode. • When there is a write to CNT register. • When there is the FTM counter synchronization. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 925 0x04 0x05 0x06 0x07 0x00 0x01 0x02 0x03 0x04 0x05 FTM counter FTM counter synchronization initialization trigger Figure 38-242. Initialization trigger is generated when there is the FTM counter synchronization K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 926: Capture Test Mode
FTM counter and CnV registers. In this test mode, all channels must be configured for Input Capture mode and FTM counter must be configured to the counting. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 927: Dma
The channel interrupt is generated if (CHnF = 1). generated. The channel DMA transfer request is not The channel interrupt is not generated. generated. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 928: Dual Edge Capture Mode
* Filtering function for dual edge capture mode is only available in the channels 0 and 2 Figure 38-246. Dual Edge Capture mode block diagram The MS(n)A bit defines if the Dual Edge Capture mode is one-shot or continuous. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 929 The edge captures are enabled while DECAP bit is set. For each new measurement in One-Shot Capture mode, first the CH(n)F and CH(n+1) bits must be cleared, and then the DECAP bit must be set. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 930 The DECAPEN bit selects the Dual Edge Capture mode, so it remains set. The DECAP bit is set to enable the measurement of next K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 931 The CH(n)F bit is set when the first edge of the positive polarity pulse is detected, that is, the edge selected by ELS(n)B:ELS(n)A bits. The CH(n+1)F bit K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 932 If both channels (n) and (n+1) are configured to capture falling edges (ELS(n)B:ELS(n)A = 1:0 and ELS(n+1)B:ELS(n+1)A = 1:0), then the period between two consecutive falling edges is measured. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 933 - Problem 3: channel (n) input = 1, set DECAP, not clear CH(n)F, and not clear CH(n+1)F. Figure 38-249. Dual Edge Capture – One-Shot mode to measure of the period between two consecutive rising edges K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 934 The Dual Edge Capture mode implements a read coherency mechanism between the FTM counter value captured in C(n)V and C(n+1)V registers. The read coherency mechanism is illustrated in the following figure. In this example, the channels (n) and (n K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 935: Quadrature Decoder Mode
The Quadrature Decoder mode is selected if (QUADEN = 1). The Quadrature Decoder mode uses the input signals phase A and B to control the FTM counter increment and decrement. The following figure shows the quadrature decoder block diagram. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 936 An edge at phase A must not occur together an edge at phase B and vice-versa. The PHAPOL bit selects the polarity of the phase A input, and the PHBPOL bit selects the polarity of the phase B input. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 937 • there is a rising edge at phase B signal and phase A signal is at logic zero; • there is a rising edge at phase A signal and phase B signal is at logic one. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 938 FTM counter changes from CNTIN to MOD, TOF bit is set and TOFDIR bit is cleared. TOF bit indicates the FTM counter overflow occurred. TOFDIR indicates the counting was down when the FTM counter overflow occurred. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 939 FTM counter CNTIN 0x0000 Time Figure 38-257. Motor position jittering in a mid count value The following figure shows motor jittering produced by the phase B and A pulses respectively: K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 940: Bdm Mode
The channels outputs are frozen Writes to these registers bypass the registers when the chip enters in BDM buffers mode Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 941: Intermediate Load
In this case, it is not required to use the PWM synchronization. There are multiple possible loading points for intermediate load: K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 942 Table 38-255. Conditions for loads occurring at the next enabled loading point When a new value was written Then To the MOD register The MOD register is updated with its write buffer value. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 943: Global Time Base (Gtb)
FTM module B FTM counter GTBEEN bit FTM counter enable enable logic gtb_in gtb_in example glue logic gtb_out GTBEOUT bit gtb_out Figure 38-260. Global time base (GTB) block diagram K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 944 5. Reset the FTM counter: Write any value to the CNT register. To initiate the GTB feature in the configuration described in the preceding figure, write 1 to CONF[GTBEOUT] in the FTM module used as the time base. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 945: Reset Overview
The next step is to select the FTM counter clock by the CLKS[1:0] bits (item 4). It is important to highlight that the pins are only controlled by FTM when CLKS[1:0] bits are different from zero (See the table in the description of CnSC register). K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 946: Ftm Interrupts
– Channel (n) is in output compare and the channel (n) output is toggled when there is a match – C(n)V = 0x0014 Figure 38-262. FTM behavior after reset when the channel (n) is in Output Compare mode 38.6 FTM Interrupts K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 947: Timer Overflow Interrupt
• Do not use the Inverting without SW synchronization (see item 6). • Do not use the Initialization. • Do not change the polarity control. • Do not configure the HW synchronization K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 948 • Generate the Software Trigger Write to SYNC (SWSYNC = 1, TRIG2 = 0, TRIG1 = 0, TRIG0 = 0, SYNCHOM = 1, REINIT = 0, CNTMAX = 0, CNTMIN = 0) K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 949: Periodic Interrupt Timer (Pit)
The PIT module is an array of timers that can be used to raise interrupts and trigger DMA channels. 39.1.1 Block diagram The following figure shows the block diagram of the PIT module. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 950: Features
• Ability of timers to generate DMA trigger pulses • Ability of timers to generate interrupts • Maskable interrupts • Independent timeout periods for each timer 39.2 Signal description The PIT module has no external pins. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 951: Memory Map/Register Description
39.3.1 PIT Module Control Register (PIT_MCR) This register enables or disables the PIT timer clocks and controls the timers when the PIT enters the Debug mode. Access: User read/write K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 952 Clock for standard PIT timers is disabled. Freeze Allows the timers to be stopped when the device enters the Debug mode. Timers continue to run in Debug mode. Timers are stopped in Debug mode. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 953: Timer Load Value Register (Pit_Ldvaln)
• If the timer is disabled, do not use this field as its value is unreliable. • The timer uses a downcounter. The timer values are frozen in Debug mode if MCR[FRZ] is set. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 954: Timer Control Register (Pit_Tctrln)
Timer Enable Enables or disables the timer. Timer n is disabled. Timer n is enabled. 39.3.5 Timer Flag Register (PIT_TFLGn) These registers hold the PIT interrupt flags. Access: User read/write K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 955: Functional Description
Each time a timer reaches 0, it will generate a trigger pulse and set the interrupt flag. All interrupts can be enabled or masked by setting TCTRLn[TIE]. A new interrupt can be generated only after the previous one is cleared. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 956 LDVAL with the new load value. This value will then be loaded after the next trigger event. See the following figure. Timer enabled New start Value p2 set Start value = p1 Trigger event Figure 39-25. Dynamically setting a new load value K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 957: Interrupts
5.12 ms/20 ns = 256,000 cycles and Timer 3 every 30 ms/20 ns = 1,500,000 cycles. The value for the LDVAL register trigger is calculated as: LDVAL trigger = (period / clock period) -1 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 958: Example Configuration For Chained Timers
The interrupt for Timer 2 is enabled by setting TCTRL2[TIE], the Chain mode is activated by setting TCTRL2[CHN], and the timer is started by writing a 1 to TCTRL2[TEN]. TCTRL1[TEN] needs to be set, and TCTRL1[CHN] and TCTRL1[TIE] are cleared. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 959 PIT_TCTRL2 |= TEN; // start Timer 2 // Timer 1 PIT_LDVAL1 = 0x23C345FF; // setup Timer 1 for 600 000 000 cycles PIT_TCTRL1 = TEN; // start Timer 1 K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 960 Example configuration for chained timers K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 961: Low-Power Timer (Lptmr)
• Configurable clock source for prescaler/glitch filter • Configurable input source for pulse counter • Rising-edge or falling-edge 40.1.2 Modes of operation The following table describes the operation of the LPTMR module in various modes. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 962: Lptmr Signal Descriptions
CNR to increment. Timing Assertion or deassertion may occur at any time; input may assert asynchronously to the bus clock. 40.3 Memory map and register definition K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 963: Low Power Timer Control Status Register (Lptmrx_Csr)
LPTMR is disabled. The input connections vary by device. See the chip configuration details for information on the connections to these inputs. Pulse counter input 0 is selected. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 964: Low Power Timer Prescale Register (Lptmrx_Psr)
LPTMR is disabled and internal logic is reset. LPTMR is enabled. 40.3.2 Low Power Timer Prescale Register (LPTMRx_PSR) Address: 4004_0000h base + 4h offset = 4004_0004h Reset PRESCALE PBYP Reset K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 965 LPTMR is disabled. The clock connections vary by device. NOTE: See the chip configuration details for information on the connections to these inputs. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 966: Low Power Timer Compare Register (Lptmrx_Cmr)
Address: 4004_0000h base + Ch offset = 4004_000Ch COUNTER Reset LPTMRx_CNR field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 15–0 Counter Value COUNTER K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 967: Functional Description
40.4.3 LPTMR prescaler/glitch filter The LPTMR prescaler and glitch filter share the same logic which operates as a prescaler in Time Counter mode and as a glitch filter in Pulse Counter mode. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 968 CNR can increment is once every 2 to 2 prescaler clock edges. When first enabled, the glitch filter will wait an additional one or two prescaler clock edges due to synchronization logic. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 969: Lptmr Compare
When reading the CNR, the bus clock must be at least two times faster than the rate at which the LPTMR counter is incrementing, otherwise incorrect data may be returned. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 970: Lptmr Hardware Trigger
The LPTMR interrupt is generated asynchronously to the system clock and can be used to generate a wakeup from any low-power mode, including the low-leakage modes, provided the LPTMR is enabled as a wakeup source. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 971: Real Time Clock (Rtc)
The RTC remains functional in all low power modes and can generate an interrupt to exit any low power mode. It operates in one of two modes of operation: chip power-up and chip power-down. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 972: Rtc Signal Descriptions
RTC interrupt is asserted or the wakeup pin is turned on via a register bit. The wakeup pin does not assert from the RTC seconds interrupt. NOTE The wakeup pin is optional and may not be implemented on all devices. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 973: Register Definition
4003_D800 RTC Write Access Register (RTC_WAR) 0000_00FFh 41.2.9/981 41.2.10/ 4003_D804 RTC Read Access Register (RTC_RAR) 0000_00FFh 41.2.1 RTC Time Seconds Register (RTC_TSR) Address: 4003_D000h base + 0h offset = 4003_D000h Reset K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 974: Rtc Time Prescaler Register (Rtc_Tpr)
Time Alarm Register When the time counter is enabled, the SR[TAF] is set whenever the TAR[TAR] equals the TSR[TSR] and the TSR[TSR] increments. Writing to the TAR clears the SR[TAF]. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 975: Rtc Time Compensation Register (Rtc_Tcr)
Time Prescaler Register overflows every 32769 clock cycles. Time Prescaler Register overflows every 32768 clock cycles. Time Prescaler Register overflows every 32767 clock cycles. Time Prescaler Register overflows every 32641 clock cycles. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 976: Rtc Control Register (Rtc_Cr)
Disable the load. Enable the additional load. Oscillator 4pF Load Configure SC4P Disable the load. Enable the additional load. Oscillator 8pF Load Configure SC8P Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 977 Resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR registers . The SWR bit is cleared by VBAT POR and by software explicitly clearing it. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 978: Rtc Status Register (Rtc_Sr)
This bit is cleared by writing the TSR register when the time counter is disabled. Time is valid. Time is invalid and time counter is read as zero. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 979: Rtc Lock Register (Rtc_Lr)
Time Compensation Register is locked and writes are ignored. Time Compensation Register is not locked and writes complete as normal. 2–0 This field is reserved. Reserved This read-only field is reserved and always has the value 1. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 980: Rtc Interrupt Enable Register (Rtc_Ier)
Time alarm flag does generate an interrupt. Time Overflow Interrupt Enable TOIE Time overflow flag does not generate an interrupt. Time overflow flag does generate an interrupt. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 981: Rtc Write Access Register (Rtc_War)
After being cleared, this bit is set only by system reset. It is not affected by VBAT POR or software reset. Writes to the Status Register are ignored. Writes to the Status Register complete as normal. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 982: Rtc Read Access Register (Rtc_Rar)
Writes to the Time Seconds Register complete as normal. 41.2.10 RTC Read Access Register (RTC_RAR) Address: 4003_D000h base + 804h offset = 4003_D804h Reset IERR CRR TCRR TARR TPRR TSRR Reset K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 983 After being cleared, this bit is set only by system reset. It is not affected by VBAT POR or software reset. Reads to the Time Seconds Register are ignored. Reads to the Time Seconds Register complete as normal. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 984: Functional Description
SR[TCE] or using the oscillator clock external to the RTC. The crystal oscillator includes tunable capacitors that can be configured by software. Do not change the capacitance unless the oscillator is disabled. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 985: Time Counter
SR[TIF] is set on VBAT POR and software reset and is cleared by initializing the time seconds register. The time seconds register and time prescaler register read as zero whenever SR[TIF] is set. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 986: Compensation
The 32-bit TAR is compared with the 32-bit Time Seconds register (TSR) each time it increments. SR[TAF] will set when TAR equals TSR and TSR increments. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 987: Update Mode
It is always asserted on VBAT POR, and software reset, and when the VBAT power supply is powered down. The RTC interrupt is enabled at the chip level K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 988 RTC clock gate control bit. The RTC seconds interrupt does not cause the RTC wakeup pin to assert. This interrupt is optional and may not be implemented on all devices. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 989: Universal Serial Bus Full Speed Otg Controller (Usbfsotg)
There is only one host in any USB system. The USB interface to the host computer system is referred to as the Host Controller. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 990: Usb On-The-Go
(host or peripheral) based on how it is connected. After connecting, the devices can negotiate using the OTG protocols to assume the role of host or peripheral based on the task to be accomplished. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 991: Usbfs Features
• IRC48 with clock-recovery is supported to eliminate the 48 MHz crystal. It is used for USB device-only implementation. 42.2 Functional description USBOTG communicates with the processor core through status registers, control registers, and data structures in memory. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 992: Programmers Interface
BD or its corresponding data buffer. The BD also contains indirect address pointers to where the actual buffer resides in system memory. This indirect address mechanism is shown in the following diagram. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 993: Rx Vs. Tx As A Usb Target Device Or Usb Host
The following table shows how the data direction corresponds to the USB token type in host and target device applications. Table 42-1. Data direction for USB host or USB target Device OUT or SETUP Host OUT or SETUP K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 994: Addressing Bdt Entries
A buffer descriptor provides endpoint buffer control information for USBFS and the processor. The Buffer Descriptors have different meaning based on whether it is USBFS or the processor reading the BD in memory. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 995 Represents the 10-bit byte count. The USBFS SIE changes this field upon the completion of a RX transfer with the byte count of the data received. 15–8 Reserved RSVD Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 996 • If KEEP=1, this bit is unchanged by USBFS. TOK_PID[1] 0 Data Toggle Synchronization is disabled. 1 Enables USBFS to perform Data Toggle Synchronization. Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 997: Usb Transaction
If OWN =1, the following process occurs: 1. USBFS reads the BDT. 2. The SIE transfers the data via the DMA to or from the buffer pointed to by the ADDR field of the BD. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 998 NAKing the packet can result in retransmission of the already oversized packet data. Therefore, in response to oversized packets, the USB core continues ACKing the packet for non-isochronous transfers. K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 999: Memory Map/Register Definitions
4007_201C OTG Control register (USB0_OTGCTL) 42.4.8/1006 4007_2080 Interrupt Status register (USB0_ISTAT) 42.4.9/1007 42.4.10/ 4007_2084 Interrupt Enable register (USB0_INTEN) 1008 42.4.11/ 4007_2088 Error Interrupt Status register (USB0_ERRSTAT) 1009 Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 1000 1019 42.4.23/ 4007_20E0 Endpoint Control register (USB0_ENDPT8) 1019 42.4.23/ 4007_20E4 Endpoint Control register (USB0_ENDPT9) 1019 42.4.23/ 4007_20E8 Endpoint Control register (USB0_ENDPT10) 1019 Table continues on the next page... K22F Sub-Family Reference Manual , Rev. 3, 7/2014 1000 Freescale Semiconductor, Inc.

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Freescale Semiconductor MK22FN256VDC12 Reference Manual

Chapter 1 About this Document

Chapter 2 Introduction

Chapter 3 Chip Configuration

Chapter 4 Memory Map

Chapter 5 Clock Distribution

Chapter 6 Reset and Boot

Chapter 7 Power Management

Chapter 8 Security

Chapter 9 Debug

Chapter 10 Signal Multiplexing and Signal Descriptions

Chapter 11 Port Control and Interrupts (PORT)

Chapter 12 System Integration Module (SIM)

Chapter 13 Kinetis Flashloader

Chapter 14 Reset Control Module (RCM)

Chapter 15 System Mode Controller (SMC)

Chapter 16 Power Management Controller (PMC)

Chapter 17 Low-Leakage Wakeup Unit (LLWU)

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