Freescale Semiconductor KL02 Series Reference Manual

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KL02 Sub-Family Reference Manual

Supports: MKL02Z32CAF4R and KKL02Z32CAF4R

Document Number: KL02P20M48SF0RM

Rev 2.1, July 2013

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Page 1 KL02 Sub-Family Reference Manual Supports: MKL02Z32CAF4R and KKL02Z32CAF4R Document Number: KL02P20M48SF0RM Rev 2.1, July 2013...
Page 2 KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 3: Table Of Contents
Memories and memory interfaces........................33 2.4.4 Clocks................................33 2.4.5 Security and integrity modules........................33 2.4.6 Analog modules.............................34 2.4.7 Timer modules...............................34 2.4.8 Communication interfaces..........................34 2.4.9 Human-machine interfaces..........................35 Orderable part numbers..............................35 Chapter 3 Chip Configuration Introduction...................................37 KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 4 Peripheral bridge configuration........................51 3.4.7 Computer operating properly (COP) watchdog configuration..............52 Clock modules................................54 3.5.1 MCG configuration............................54 3.5.2 OSC configuration............................55 Memories and memory interfaces..........................56 3.6.1 Flash memory configuration..........................56 3.6.2 Flash memory controller configuration......................58 KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 5 Read-after-write sequence and required serialization of memory operations..........80 4.6.2 Peripheral bridge (AIPS-Lite) memory map....................80 4.6.3 Modules restricted access in user mode......................84 Private Peripheral Bus (PPB) memory map........................84 Chapter 5 Clock Distribution Introduction...................................85 KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 6 6.2.1 Power-on reset (POR)............................95 6.2.2 System reset sources............................96 6.2.3 MCU resets..............................99 6.2.4 RESET_b pin ..............................100 6.2.5 Debug resets..............................100 Boot....................................101 6.3.1 Boot sources..............................101 6.3.2 FOPT boot options............................101 6.3.3 Boot sequence..............................103 KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 7 Debug port pin descriptions............................115 SWD status and control registers..........................116 9.3.1 MDM-AP Control Register..........................117 9.3.2 MDM-AP Status Register..........................118 Debug resets..................................120 Micro Trace Buffer (MTB)............................120 Debug in low-power modes............................121 Debug and security...............................122 KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 8 Introduction...................................131 11.2 Overview..................................131 11.2.1 Features................................131 11.2.2 Modes of operation............................132 11.3 External signal description............................132 11.4 Detailed signal description............................133 11.5 Memory map and register definition..........................133 11.5.1 Pin Control Register n (PORTx_PCRn)......................136 KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 9 12.2.12 Unique Identification Register Mid-High (SIM_UIDMH)................159 12.2.13 Unique Identification Register Mid Low (SIM_UIDML)................159 12.2.14 Unique Identification Register Low (SIM_UIDL)..................160 12.2.15 COP Control Register (SIM_COPC)......................160 12.2.16 Service COP Register (SIM_SRVCOP)......................161 12.3 Functional description..............................162 KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 10 Memory map and register descriptions.........................183 14.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)............184 14.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)............185 14.5.3 Regulator Status And Control register (PMC_REGSC)................186 KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 11 17.2 Memory map/register descriptions..........................215 17.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)..............216 17.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)..............217 17.2.3 Platform Control Register (MCM_PLACR)....................217 17.2.4 Compute Operation Control Register (MCM_CPO)..................220 KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 12 19.3 Functional Description..............................258 19.3.1 General operation............................258 19.3.2 Arbitration..............................259 19.4 Initialization/application information...........................260 Chapter 20 Peripheral Bridge (AIPS-Lite) 20.1 Introduction...................................261 20.1.1 Features................................261 20.1.2 General operation............................261 20.2 Functional description..............................262 20.2.1 Access support...............................262 KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 13 MCG Fixed frequency clock .........................279 21.4.6 MCG Auto TRIM (ATM)..........................279 21.5 Initialization / Application information........................281 21.5.1 MCG module initialization sequence......................281 21.5.2 Using a 32.768 kHz reference........................283 21.5.3 MCG mode switching............................284 KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 14 Chapter 23 Flash Memory Controller (FMC) 23.1 Introduction...................................297 23.1.1 Overview................................297 23.1.2 Features................................297 23.2 Modes of operation...............................298 23.3 External signal description............................298 23.4 Memory map and register descriptions.........................298 23.5 Functional description..............................298 KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 15 24.4.8 Flash Command Operations...........................317 24.4.9 Margin Read Commands..........................322 24.4.10 Flash Command Description..........................323 24.4.11 Security................................336 24.4.12 Reset Sequence..............................338 Chapter 25 Analog-to-Digital Converter (ADC) 25.1 Introduction...................................339 25.1.1 Features................................339 25.1.2 Block diagram..............................340 KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 16 Clock select and divide control........................360 25.4.2 Voltage reference selection..........................360 25.4.3 Hardware trigger and channel selects......................361 25.4.4 Conversion control............................362 25.4.5 Automatic compare function..........................368 25.4.6 Calibration function............................370 25.4.7 User-defined offset function..........................371 KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 17 CMP Status and Control Register (CMPx_SCR)...................390 26.7.5 DAC Control Register (CMPx_DACCR)......................391 26.7.6 MUX Control Register (CMPx_MUXCR)....................392 26.8 Functional description..............................393 26.8.1 CMP functional modes...........................393 26.8.2 Power modes..............................402 26.8.3 Startup and operation.............................403 KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 18 Status and Control (TPMx_SC)........................413 27.3.2 Counter (TPMx_CNT)...........................414 27.3.3 Modulo (TPMx_MOD)..........................415 27.3.4 Channel (n) Status and Control (TPMx_CnSC).....................416 27.3.5 Channel (n) Value (TPMx_CnV)........................417 27.3.6 Capture and Compare Status (TPMx_STATUS)...................418 27.3.7 Configuration (TPMx_CONF)........................420 KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 19 Low Power Timer Compare Register (LPTMRx_CMR)................438 28.3.4 Low Power Timer Counter Register (LPTMRx_CNR).................438 28.4 Functional description..............................439 28.4.1 LPTMR power and reset..........................439 28.4.2 LPTMR clocking............................439 28.4.3 LPTMR prescaler/glitch filter........................439 28.4.4 LPTMR compare............................441 28.4.5 LPTMR counter.............................441 KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 20 SPI Data Register (SPIx_D)...........................453 29.3.6 SPI Match Register (SPIx_M)........................454 29.4 Functional description..............................455 29.4.1 General................................455 29.4.2 Master mode..............................455 29.4.3 Slave mode..............................457 29.4.4 SPI clock formats............................458 29.4.5 SPI baud rate generation..........................461 KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 21 I2C Control Register 2 (I2Cx_C2).........................479 30.3.7 I2C Programmable Input Glitch Filter register (I2Cx_FLT).................480 30.3.8 I2C Range Address register (I2Cx_RA)......................482 30.4 Functional description..............................482 30.4.1 I2C protocol..............................482 30.4.2 10-bit address..............................487 30.4.3 Address matching............................489 30.4.4 Resets................................489 KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 22 31.2.12 UART Control Register 5 (UARTx_C5).......................511 31.3 Functional description..............................512 31.3.1 Baud rate generation............................512 31.3.2 Transmitter functional description.........................512 31.3.3 Receiver functional description........................514 31.3.4 Additional UART functions...........................517 31.3.5 Interrupts and status flags..........................519 KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 23 32.3.4 Port Toggle Output Register (FGPIOx_PTOR).....................529 32.3.5 Port Data Input Register (FGPIOx_PDIR).....................530 32.3.6 Port Data Direction Register (FGPIOx_PDDR)....................530 32.4 Functional description..............................530 32.4.1 General-purpose input............................530 32.4.2 General-purpose output..........................531 32.4.3 IOPORT.................................531 KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 24 KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 25: About This Document
Hexadecimal number. For example, the hexadecimal equivalent of the number 60 is written 3Ch. In some cases, hexadecimal numbers are shown with the prefix 0x. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 26: Typographic Notation
Refers to a memory space, register, or field that is either reserved for future use or for which, when written to, the module or chip behavior is unpredictable. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 27: Introduction
• Powerful timers for a broad range of applications including motor control • Low-power focused serial communication interfaces such as low-power UART, SPI, I2C, and others. • Single power supply: 1.71–3.6 V with multiple low-power modes support single operation temperature: KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 28 • ARM Cortex-M0+ Core running up to 48 MHz with zero wait state execution from memories • Single-cycle access to I/O: Up to 50 percent faster than standard I/O, improves reaction time to external events allowing bit banging and software protocol emulation KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 29 • Scalable memory footprints from 8 KB flash / 1 KB SRAM to 256 KB flash / 32 KB SRAM • Embedded 64 B cache memory for optimizing bus bandwidth and flash execution performance (32 B cache on KL02 family) • Mixed-signal analog: KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 30: Kl02 Sub-Family Introduction
Cortex-M0+ (CM0+) core platform. The features of the KL0x family derivatives are as follows. • Core platform clock up to 48 MHz, bus clock up to 24 MHz KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 31: Module Functional Categories
• System tick timer Communications • One8-bit serial peripheral interface • Two inter-integrated circuit (I C) modules • One low power UART module Human-Machine Interfaces (HMI) • General purpose input/output controller KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 32: Arm Cortex-M0+ Core Modules
Includes power-on-reset (POR) and integrated low voltage detect (LVD) with reset (brownout) capability and selectable LVD trip points. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 33: Memories And Memory Interfaces
The system oscillator, in conjunction with an external crystal or resonator, generates a reference clock for the MCU. 2.4.5 Security and integrity modules The following security and integrity modules are available on this device: KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 34: Analog Modules
Low power timer (LPTMR) • 16-bit time counter or pulse counter with compare • Configurable clock source for prescaler/glitch filter • Configurable input source for pulse counter KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 35: Communication Interfaces
MKL02Z32CAF4R 48 MHz WLCSP 32 KB 4 KB 100 pieces -40 to 85 °C KKL02Z32CAF4R 48 MHz WLCSP 32 KB 4 KB 3000 -40 to 85 °C pieces KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 36 Orderable part numbers KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 37: Chip Configuration
LPTMR Hardware ADC (Trigger) SOPT7_ADC0TRGSE — trigger Triggering (A L (4-bit field), or B) ADC0PRETRGSEL to select A or B Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 38 TPMx TPM Trigger TPMx_CONF[TRGSE — input L] (4-bit field) CMP0 CMP0_OUT TPMx TPM Trigger TPMx_CONF[TRGSE — input L] (4-bit field) UART0 UART0_TX Modulated by UART SOPT5_UART0TXSR TPM1 CH0 modulation KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 39: Analog Reference Options
Related module Reference Full description ARM Cortex-M0+ core, ARM Cortex-M0+ Technical Reference Manual, r0p0 r0p0 System memory map System memory map Clocking Clock distribution Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 40 1 = Present Implements system tick timer (for CM4 compatibility) DAP Target ID TARGETID — User/Privileged USER 1 = Present Implements processor operating modes Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 41 ARM documentation uses different terms than this document to distinguish between privilege levels. If you see this term... it also means this term... Privileged Supervisor Unprivileged or user User KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 42: Nested Vectored Interrupt Controller (Nvic) Configuration
The non-maskable interrupt request to the NVIC is controlled by the external NMI signal. The pin the NMI signal is multiplexed on, must be configured for the NMI function to generate the non-maskable interrupt request. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 43 ARM core System tick timer (SysTick) Non-Core Vectors 0x0000_0040 — — 0x0000_0044 — — 0x0000_0048 — — 0x0000_004C — — 0x0000_0050 — — Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 44 3.3.2.3.1 Determining the bitfield and register location for configuring a particular interrupt Suppose you need to configure the SPI0 interrupt. The following table is an excerpt of the SPI0 row from Interrupt priority levels. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 45: Asynchronous Wake-Up Interrupt Controller (Awic) Configuration
Table 3-9. Reference links to related information Topic Related module Reference System memory map — System memory map Clocking — Clock distribution Power management — Power management Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 46: System Modules
3.4 System modules 3.4.1 SIM configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 47: System Mode Controller (Smc) Configuration
Table 3-12. Reference links to related information Topic Related module Reference Full description System mode controller (SMC) System memory map — System memory map Power management — Power management Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 48: Pmc Configuration
Full description System memory map — System memory map Power management — Power management Full description System mode controller System Mode Controller (SMC) — Reset control module Reset (RCM) KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 49: Mcm Configuration
3.4.5 Crossbar-light switch configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 50 GPIO controller GPIO controller 3.4.5.1 Crossbar-light switch master assignments The masters connected to the crossbar switch are assigned as follows: Master module Master port number ARM core unified bus KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 51: Peripheral Bridge Configuration
The peripheral bridges are used to access the registers of most of the modules on this device. See AIPS0 Memory Map for the memory slot assignment for each module. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 52: Computer Operating Properly (Cop) Watchdog Configuration
After any reset, the COP watchdog is enabled. If the COP watchdog is not used in an application, it can be disabled by clearing SIM_COPCTRL[COPT]. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 53 The write to the SIM_SRVCOP register that services (clears) the COP counter should not be placed in an interrupt service routine (ISR) because the ISR could continue to be executed periodically even if the main application program fails. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 54: Clock Modules
Register access Multipurpose Clock Generator (MCG) Figure 3-11. MCG configuration Table 3-19. Reference links to related information Topic Related module Reference Full description Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 55: Osc Configuration
Related module Reference Full description System memory map — System memory map Clocking — Clock distribution Power management — Power management Signal multiplexing Port control Signal multiplexing Full description KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 56: Memories And Memory Interfaces
Full description Flash memory Flash memory System memory map — System memory map Clocking — Clock distribution Transfers Flash memory Flash memory controller controller Register access Peripheral bridge Peripheral bridge KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 57 3.6.1.3 Flash security For information on how flash security is implemented on this device, see Chip Security. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 58: Flash Memory Controller Configuration
Figure 3-15. Flash memory controller configuration Table 3-23. Reference links to related information Topic Related module Reference Full description Flash memory Flash memory controller controller Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 59: Sram Configuration
The amount of SRAM for the devices covered in this document is shown in the following table. Table 3-25. KL02 SRAM memory size Freescale part number MKL02Z32CAF4R 4 KB KKL02Z32CAF4R 4 KB KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 60 0x2000_0000 – SRAM_size/4 SRAM_L 0x1FFF_FFFF 0x2000_0000 SRAM_U 0x2000_0000 + SRAM_size(3/4) - 1 Figure 3-17. SRAM blocks memory map For example, for a device containing 16 KB of SRAM, the ranges are: KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 61: Analog
Clock distribution Power management — Power management Signal multiplexing Port control Signal multiplexing 3.7.1.1 ADC instantiation information This device contains one 12-bit successive approximation ADC with up to 10 channels. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 62 AD17 Reserved Reserved 10010 AD18 Reserved Reserved 10011 AD19 Reserved Reserved 10100 AD20 Reserved Reserved 10101 AD21 Reserved Reserved 10110 AD22 Reserved Reserved Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 63: Cmp Configuration
3.7.2 CMP configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 64 CMP_CR1[WE]. The sample function has limited functionality since the SAMPLE input to the block is not connected to a valid input. Usage of sample operation is limited to a divided version of the bus clock (CMP_CR1[SE] = 0). KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 65 TCF flag is set. The delay to the second signal that triggers the CMP to capture the result of the compare operation is dependent on the LPTMR configuration. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 66: Timers
Reference Full description Timer/PWM module Timer/PWM module System memory map — System memory map Clocking — Clock distribution Power management — Power management Signal multiplexing Port control Signal multiplexing KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 67 The options available are shown in the following table. Table 3-32. TPM trigger options TPMx_CONF[TRGSEL] Selected source 0000 External trigger pin input (EXTRG_IN) Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 68: Low-Power Timer Configuration
3.8.2 Low-power timer configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 69 LPTMR_CSR[TPS] Pulse counter input number Chip input CMP0 output LPTMR_ALT1 pin LPTMR_ALT2 pin Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 70: Communication Interfaces
3.9 Communication interfaces 3.9.1 SPI configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 71: I2C Configuration
SPI can wake the MCU from VLPS mode upon reception of SPI data in slave mode. 3.9.2 I2C configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 72: Uart Configuration
3.9.3 UART configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 73: Human-Machine Interfaces (Hmi)
ISO7816 protocol is intended to be handled in software for this product. To support smart card reading, TxD pin can be configured as pseudo open drain for 1-wire half-duplex like ISO7816 communication via SIM_SOPT5[UART0ODE]. 3.10 Human-machine interfaces (HMI) KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 74: Gpio Configuration
Other pins can be enabled by writing to PORTx_PCRn[PE]. All the pins are hard wired to be pullup except for SWD_CLK. The state will be reflected in the PORTx_PCRn[PS] field. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 75 BME operations to the GPIO space can be accomplished referencing the aliased slot (15) at address 0x4000_F000. Only some of the BME operations can be accomplished referencing GPIO at address 0x400F_F000. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 76 Human-machine interfaces (HMI) KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 77: Memory Map
Cortex-M0+ core 0xE010_0000–0xEFFF_FFFF Reserved – 0xF000_0000–0xF000_0FFF Micro Trace Buffer (MTB) registers Cortex-M0+ core 0xF000_1000–0xF000_1FFF MTB Data Watchpoint and Trace (MTBDWT) registers Cortex-M0+ core Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 78: Flash Memory Map
An alternate IRC trim to the factory loaded trim can be stored at this location. To override the factory trim, the user software must load new values into the MCG trim registers. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 79: Sram Memory Map
• A 128 KB region, partitioned as 32 spaces, each 4 KB in size and reserved for on- platform peripheral devices. The AIPS controller generates unique module enables for all 32 spaces. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 80: Read-After-Write Sequence And Required Serialization Of Memory Operations
4.6.2 Peripheral bridge (AIPS-Lite) memory map Table 4-2. Peripheral bridge 0 slot assignments System 32-bit base address Slot Module number 0x4000_0000 — 0x4000_1000 — 0x4000_2000 — 0x4000_3000 — Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 81 0x4002_0000 Flash memory 0x4002_1000 — 0x4002_2000 — 0x4002_3000 — 0x4002_4000 — 0x4002_5000 — 0x4002_6000 — 0x4002_7000 — 0x4002_8000 — 0x4002_9000 — 0x4002_A000 — Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 82 Port A multiplexing control 0x4004_A000 Port B multiplexing control 0x4004_B000 — 0x4004_C000 — 0x4004_D000 — 0x4004_E000 — 0x4004_F000 — 0x4005_0000 — 0x4005_1000 — Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 83 — 0x4007_2000 — 0x4007_3000 Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) 0x4007_4000 — 0x4007_5000 — 0x4007_6000 SPI 0 0x4007_7000 — 0x4007_8000 — Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 84: Modules Restricted Access In User Mode
Reserved 0xE000_E000–0xE000_EFFF System Control Space 0xE000_E000–0xE000_E00F Reserved (SCS) 0xE000_E010–0xE000_E0FF SysTick 0xE000_E100–0xE000_ECFF NVIC 0xE000_ED00–0xE000_ED8F System Control Block 0xE000_ED90–0xE000_EDEF Reserved 0xE000_EDF0–0xE000_EEFF Debug 0xE000_EF00–0xE000_EFFF Reserved 0xE000_F000–0xE00F_EFFF Reserved 0xE00F_F000–0xE00F_FFFF Core ROM Space (CRS) KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 85: Clock Distribution
MCG, and module registers control the multiplexers, dividers, and clock gates shown in the following figure: Multiplexers MCG_Cx MCG_Cx SIM_SOPT1, SIM_SOPT2 Dividers — MCG_Cx SIM_CLKDIVx Clock gates OSC_CR MCG_C1 SIM_SCGCx KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 86: Clock Definitions
Clocks the crossbar switch and NVIC. System clock MCGOUTCLK divided by OUTDIV1 Clocks the bus masters directly . Bus clock System clock divided by OUTDIV4. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 87: Device Clock Summary
STOP2 mode, and Compute Operation SWD Clock Up to 24 MHz Up to 1 MHz SWD_CLK pin In all stop modes Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 88: Internal Clocking Requirements
5.5 Internal clocking requirements The clock dividers are programmed via the CLKDIV registers of the SIM module. The following requirements must be met when configuring the clocks for this device: KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 89: Clock Divider Values After Reset
FTFA_FOPT. During the reset sequence, if either of the control bits is cleared, the system is in a slower clock configuration. Upon any system reset, the clock dividers return to this configurable reset state. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 90: Clock Gating
Internal clocks I/O interface clocks Core modules ARM Cortex-M0+ core Platform clock Core clock — NVIC Platform clock — — Platform clock — SWD_CLK Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 91: Pmc 1-Khz Lpo Clock
The Power Management Controller (PMC) generates a 1-kHz clock that is enabled in all modes of operation, including all low-power modes except VLLS0. This 1-kHz source is commonly referred to as LPO clock or 1-kHz LPO clock. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 92: Cop Clocking
ERCLK32K OSCERCLK LPTMRx_PSR[PCS] Figure 5-3. LPTMRx prescaler/glitch filter clock generation 5.7.4 TPM clocking The counter for the TPM modules has a selectable clock as shown in the following figure. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 93: Uart Clocking
The chosen clock must remain enabled if the UART0 is to continue operating in all required low-power modes. MCGIRCLK OSCERCLK UART0 clock MCGFLLCLK SIM_SOPT2[UART0SRC] Figure 5-5. UART0 clock generation KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 94 Module clocks KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 95: Reset And Boot
6.2 Reset This section discusses basic reset mechanisms and sources. Some modules that cause resets can be configured to cause interrupts instead. Consult the individual peripheral chapters for more information. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 96: System Reset Sources
When this option is selected, there could be a short period of contention during a POR ramp where the device drives the pin-out low prior to establishing the setting of this option and releasing the reset function on the pin. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 97 (or refreshing) the COP watchdog. If this periodic refreshing does not occur, the watchdog issues a system reset. The COP reset causes RCM_SRS0[WDOG] to set. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 98 The LOCKUP condition causes a system reset and also causes RCM_SRS1[LOCKUP] to set. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 99: Mcu Resets
The Chip Reset not VLLS reset asserts on all reset sources except a VLLS Wakeup that does not occur via the RESET_b pin. It resets parts of the SMC and other modules that remain powered during VLLS mode. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 100: Reset_B Pin
POR ramp where the device drives the pinout low prior to establishing the setting of this option and releasing the RESET function on the pin. 6.2.5 Debug resets The following sections detail the debug resets available on the device. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 101: Boot
0x0 (initial SP_main), 0x4 (initial PC), and RAM with relocating the exception vector table to RAM. 1. CDBGRSTREQ does not affect AHB resources so that debug resources on the private peripheral bus are available during System Reset. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 102 NMI_b pin/interrupts reset default to enabled. Reserved Reserved for future expansion. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 103: Boot Sequence
(LR). The processor reads the start SP (SP_main) from vector-table offset 0. The core reads the start PC from vector-table offset 4. LR is set to KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 104 NMI interrupt. The processor executes an Exception Entry and reads the NMI interrupt handler address from vector-table offset 8. The CPU begins execution at the NMI interrupt handler. Subsequent system resets follow this same reset flow. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 105: Power Management
PSTOP2 is functionally similar to WAIT mode, but offers additional power savings through the gating of the System clock. All the bus masters are disabled. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 106: Compute Operation
Compute Operation is controlled by the CPO register in the MCM (MCM_CPO), which is only accessible to the CPU. Setting or clearing MCM_CPO[CPOREQ] initiates entry or exit into Compute Operation. Compute Operation can also be configured to exit KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 107: Peripheral Doze
SIM module. The bits of these registers are cleared after any reset, which disables the clock to the corresponding module. Prior to initializing a module, set the KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 108: Power Modes
Only MCG modes BLPI and BLPE can be used in VLPR. • Reduced frequency Flash access mode (1 MHz) Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 109: Entering And Exiting Power Modes
The WFI instruction invokes wait and stop modes for the chip. The processor exits the low-power mode via an interrupt. For VLLS3 and VLLS1 modes, the wakeup sources are limited to LPTMR, CMP,NMI_b pin, or RESET_b pin assertions. When the NMI_b pin KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 110: Module Operation In Low-Power Modes
• wakeup = Modules can serve as a wake-up source for the chip. Table 7-2. Module operation in low-power modes Modules VLPR VLPW Stop VLPS VLLSx Core modules NVIC static static System modules Mode controller Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 111 500 kbit/s, static, slave mode static, slave mode kbit/s, receive receive slave mode 250 kbit/s slave mode 250 FF in PSTOP2 kbit/s Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 112 VLLSx only supports low speed external pin to pin or external pin to DAC compares. Windowed, sampled & filtered modes of operation are not available while in stop, VLPS or VLLSx modes. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 113: Security
The flash security settings are used by the system to determine what resources are available. The following sections describe the interactions between modules and the flash security settings or the impact that the flash security has on non-flash modules. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 114: Security Interactions With Debug
All Blocks) command. A mass erase via the debugger is allowed even when some memory locations are protected. When mass erase is disabled, mass erase via the debugger is blocked. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 115: Debug
Input / Output Serial Wire Debug Data Input/Output The SWD_DIO pin is used by an external debug tool for communication and device control. This pin is pulled up internally. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 116: Swd Status And Control Registers
Table 9-2. MDM-AP register summary Address Register Description 0x0100_0000 Status MDM-AP Status Register 0x0100_0004 Control MDM-AP Control Register 0x0100_00FC Read-only identification register that always reads as 0x001C_0020 KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 117: Mdm-Ap Control Register
Set to disable debug. Clear to allow debug operation. When set, it overrides the C_DEBUGEN bit within the DHCSR and force disables Debug logic. Debug Request Set to force the core to halt. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 118: Mdm-Ap Status Register
This bit is used by the debugger to clear the sticky VLLSx mode entry status bits. This bit is asserted and cleared by the debugger. 8 – Reserved for future use 1. Command available in secure mode KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 119 Once communication is reestablished, this bit indicates that the system had been in VLLSx. Since the debug modules lose their state during VLLSx modes, they need to be reconfigured. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 120: Debug Resets
The MTB does not include any form of load/store data trace capability or tracing of any other information. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 121: Debug In Low-Power Modes
KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 122: Debug And Security
In the case of a secure device, the debugger has the capability of only performing a mass erase operation. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 123: Signal Multiplexing And Signal Descriptions
Table 10-1. Reference links to related information Topic Related module Reference Full description Port control Port control System memory map System memory map Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 124: Port Control And Interrupt Module Features
The GPIO shared with NMI_b pin is configurable. All other GPIOs are fixed and read only. IRQC No exceptions—all are cleared on reset. — No exceptions—all are cleared on reset. — — KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 125: Clock Gating
I2C, GPIO, and UART0. Pin Name Default ALT0 ALT1 ALT2 ALT3 VREFH VREFH VREFH VREFL VREFL VREFL PTA3 EXTAL0 EXTAL0 PTA3 I2C0_SCL I2C1_SDA PTA4 XTAL0 XTAL0 PTA4 I2C0_SDA I2C1_SCL KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 126: Kl02 Pinouts
The following figures show the pinout diagrams for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see KL02 signal multiplexing and pin assignments. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 127: Module Signal Description Tables
This pin is pulled down internally. 10.4.2 System modules Table 10-4. System signal descriptions Chip signal name Module signal Description name NMI_b — Non-maskable interrupt Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 128: Clock Modules
REFSL VDDA Analog Power Supply VSSA Analog Ground Table 10-7. CMP0 signal descriptions Chip signal name Module signal Description name CMP0_IN[5:0] IN[5:0] Analog voltage inputs CMP0_OUT CMPO Comparator output KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 129: Timer Modules
C0 signal descriptions Chip signal name Module signal Description name I2C0_SCL Bidirectional serial clock line of the I C system. I2C0_SDA Bidirectional serial data line of the I C system. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 130: Human-Machine Interfaces (Hmi)
PORTA31–PORTA0 General-purpose input/output PTB[31:0] PORTB31–PORTB0 General-purpose input/output 1. The available GPIO pins depend on the specific package. See the signal multiplexing section for which exact GPIO signals are available. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 131: Port Control And Interrupts (Port)
• Support for interrupt request configured per pin • Asynchronous wakeup in Low-Power modes • Pin interrupt is functional in all digital Pin Muxing modes • Port control KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 132: Modes Of Operation
11.2.2.4 Debug mode In Debug mode, PORT operates normally. 11.3 External signal description The following table describes the PORT external signal. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 133: Detailed Signal Description
Pin Control Register n (PORTA_PCR5) See section 11.5.1/136 4004_9018 Pin Control Register n (PORTA_PCR6) See section 11.5.1/136 4004_901C Pin Control Register n (PORTA_PCR7) See section 11.5.1/136 Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 134 Pin Control Register n (PORTB_PCR5) See section 11.5.1/136 4004_A018 Pin Control Register n (PORTB_PCR6) See section 11.5.1/136 4004_A01C Pin Control Register n (PORTB_PCR7) See section 11.5.1/136 Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 135 Global Pin Control Low Register (PORTB_GPCLR) (always 0000_0000h 11.5.2/138 reads 0) 4004_A084 Global Pin Control High Register (PORTB_GPCHR) (always 0000_0000h 11.5.3/139 reads 0) 4004_A0A0 Interrupt Status Flag Register (PORTB_ISFR) 0000_0000h 11.5.4/139 KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 136: Pin Control Register N (Portx_Pcrn)
This bit is read only for pins that do not support interrupt generation. The pin interrupt configuration is valid in all digital pin muxing modes. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 137 This read-only field is reserved and always has the value 0. Passive Filter Enable This bit is read only for pins that do not support a configurable passive input filter. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 138 Only 32-bit writes are supported to this register. Address: Base address + 80h offset GPWE GPWD Reset PORTx_GPCLR field descriptions Field Description 31–16 Global Pin Write Enable GPWE Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 139 The pin interrupt configuration is valid in all digital pin muxing modes. The Interrupt Status Flag for each pin is also visible in the corresponding Pin Control Register, and each flag can be cleared in either location. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 140 When the Pin Muxing mode is configured for analog or is disabled, all the digital functions on that pin are disabled. This includes the pullup and pulldown enables, and passive filter enable. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 141 During Stop mode, the interrupt status flag for any enabled interrupt is asynchronously set if the required level or edge is detected. This also generates an asynchronous wakeup signal to exit the Low-Power mode. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 142 Functional description KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 143 The SIM module contains many bitfields for selecting the clock source and dividers for various module clocks. NOTE The SIM registers can be written only in supervisor mode. In user mode, write accesses are blocked and will result in a bus error. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 144 Reset SIM_SOPT2 field descriptions Field Description 31–28 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 145 This field is reserved. This read-only field is reserved and always has the value 0. 12.2.2 System Options Register 4 (SIM_SOPT4) Address: 4004_7000h base + 100Ch offset = 4004_800Ch Reset Reset KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 146 NOTE: When TPM1 is not in input capture mode, clear this field. TPM1_CH0 signal CMP0 output Reserved This field is reserved. This read-only field is reserved and always has the value 0. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 147 Selects the source for the UART0 receive data. UART0_RX pin CMP0 output This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 148 This read-only field is reserved and always has the value 0. ADC0 Pretrigger Select ADC0PRETRGSEL Selects the ADC0 pre-trigger source when alternative triggers are enabled through ADC0ALTTRGEN. Pre-trigger A Pre-trigger B Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 149 Kinetis family ID FAMID Specifies the Kinetis family of the device. 0000 KL0x Family (low end) 0001 KL1x Family (basic) 0010 KL2x Family (USB) Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 150 Specifies the pincount of the device. 0000 16-pin 0001 24-pin 0010 32-pin 0011 36-pin 0100 48-pin 0101 64-pin 0110 80-pin 0111 Reserved 1000 100-pin 1001 Reserved Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 151 This read-only field is reserved and always has the value 0. Comparator Clock Gate Control Controls the clock gate to the comparator module. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 152 This field is reserved. Reserved This read-only field is reserved and always has the value 1. Reserved This field is reserved. This read-only field is reserved and always has the value 0. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 153 This read-only field is reserved and always has the value 0. 4–2 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 154 Controls the clock gate to the ADC0 module. Clock disabled Clock enabled This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 155 The CLKDIV1 register cannot be written to when the device is in VLPR mode. NOTE Reset value loaded during System Reset from FTFA_FOPT[LPBOOT] (See Table 6-2). Address: 4004_7000h base + 1044h offset = 4004_8044h OUTDIV1 OUTDIV4 Reset * Notes: KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 156 0001 (divide by two). Divide-by-1. Divide-by-2. Divide-by-3. Divide-by-4. Divide-by-5. Divide-by-6. Divide-by-7. Divide-by-8. Reserved This field is reserved. This read-only field is reserved and always has the value 0. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 157 128 KB of program flash memory, 4 KB protection region 1001 256 KB of program flash memory, 8 KB protection region 1111 32 KB of program flash memory, 1 KB protection region Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 158 This read-only field is reserved and always has the value 0. 30–24 Max address block MAXADDR0 This field concatenated with leading zeros indicates the first invalid address of program flash. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 159 Unique identification for the device. 12.2.13 Unique Identification Register Mid Low (SIM_UIDML) Address: 4004_7000h base + 105Ch offset = 4004_805Ch Reset * Notes: • UID field: Device specific value. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 160 12.2.15 COP Control Register (SIM_COPC) All of the bits in this register can be written only once after a reset. Address: 4004_7000h base + 1100h offset = 4004_8100h Reset COPT Reset KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 161 SIM_SRVCOP field descriptions Field Description 31–8 This field is reserved. Reserved SRVCOP Service COP Register Write 0x55 and then 0xAA (in that order) to reset the COP timeout counter. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 162 Functional description 12.3 Functional description Introduction section. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 163: System Mode Controller (Smc)
Stop are the common terms used for the primary operating modes of Freescale microcontrollers. The following table shows the translation between the ARM CPU modes and the Freescale MCU power modes. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 164 The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 165: Memory Map And Register Descriptions
Power Mode Control register (PMCTRL). The PMPROT register can be written only once after any system reset. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 166 (VLLSx). Any VLLSx mode is not allowed Any VLLSx mode is allowed This field is reserved. Reserved This read-only field is reserved and always has the value 0. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 167: Power Mode Control Register (Smc_Pmctrl)
The previous stop mode entry was successsful. The previous stop mode entry was aborted. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 168: Stop Control Register (Smc_Stopctrl)
Stop mode from RUN mode, the PMC, MCG and flash remain fully powered, allowing the device to wakeup almost instantaneously at the expense of higher power consumption. In PSTOP2, only system Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 169: Power Mode Status Register (Smc_Pmstat)
This register is reset on Chip POR not VLLS and by reset types that trigger Chip POR not VLLS. It is unaffected by reset types that do not trigger Chip POR not VLLS. See the Reset section details for more information. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 170: Functional Description
13.4.1 Power mode transitions The following figure shows the power mode state transitions available on the chip. Any reset always brings the MCU back to the normal run state. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 171 Sleep-now or sleep-on-exit modes entered with SLEEPDEEP clear, controlled in System Control Register in ARM core. See note. WAIT Interrupt or Reset STOP PMCTRL[RUNM]=00, PMCTRL[STOPM]=000 Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 172 1. If debug is enabled, the core clock remains to support debug. 2. If PMCTRL[STOPM]=000 and STOPCTRL[PSTOPO]=01 or 10, then only a Partial Stop mode is entered instead of STOP KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 173: Power Mode Entry/Exit Sequencing
Module (SMC) (CCM) PMC low power bus Flash low power bus MCG enable System Flash Power System Memory (PMC) Clocks Module (MCG) Figure 13-6. Low-power system components and connections KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 174 For wait modes (WAIT and VLPW), the CPU clock is gated off while all other clocking continues, as in RUN and VLPR mode operation. Some modules that support stop-in- wait functionality have their clocks disabled in these configurations. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 175: Run Modes
• The MCG must be configured in a mode which is supported during VLPR. See the Power Management details for information about these MCG modes. • All clock monitors in the MCG must be disabled. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 176: Wait Modes
RUN mode, beginning with the stacking operations leading to the interrupt service routine. A system reset will cause an exit from WAIT mode, returning the device to normal RUN mode. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 177: Stop Modes
PMCTRL. The selected stop mode is entered during the sleep-now or sleep-on-exit entry with the SLEEPDEEP bit set in the System Control Register in the ARM core. The available stop modes are: KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 178 A module capable of providing an asynchronous interrupt to the device takes the device out of VLPS and returns the device to VLPR mode. A system reset will also cause a VLPS exit, returning the device to normal RUN mode. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 179: Debug In Low Power Modes
STOP and VLPS by entering an emulated stop state. In this emulated stop state: • the regulator is in run regulation, • the MCG-generated clock source is enabled, KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 180 The VLLDBGACK bit is cleared by the debugger (or can be left set as is) or clears automatically due to the reset generated as part of the next VLLS recovery. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 181: Power Management Controller (Pmc)
). The trip voltage is selected by LVDH LVDL LVDSC1[LVDV]. The LVD is disabled upon entering VLPx and VLLSx modes. Two flags are available to indicate the status of the low-voltage detect system: KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 182: Lvd Reset Operation
LVDSC2[LVWIE]. If enabled, an LVW interrupt request occurs when LVDSC2[LVWF] is set. LVDSC2[LVWF] is cleared by writing 1 to LVDSC2[LVWACK]. LVDSC2[LVWV] selects one of the four trip voltages: KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 183: I/O Retention
Low Voltage Detect Status And Control 1 register 4007_D000 14.5.1/184 (PMC_LVDSC1) Low Voltage Detect Status And Control 2 register 4007_D001 14.5.2/185 (PMC_LVDSC2) 4007_D002 Regulator Status And Control register (PMC_REGSC) 14.5.3/186 KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 184: Low Voltage Detect Status And Control 1 Register (Pmc_Lvdsc1)
Low-Voltage Detect Interrupt Enable LVDIE Enables hardware interrupt requests for LVDF. Hardware interrupt disabled (use polling) Request a hardware interrupt when LVDF = 1 Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 185: Low Voltage Detect Status And Control 2 Register (Pmc_Lvdsc2)
Chip Reset Not VLLS. For more information about these reset types, refer to the Reset section details. Address: 4007_D000h base + 1h offset = 4007_D001h Read LVWF LVWIE LVWV Write LVWACK Reset KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 186: Regulator Status And Control Register (Pmc_Regsc)
(REGONS) indicating the regulator is in run regulation. NOTE This register is reset on Chip Reset Not VLLS and by reset types that trigger Chip Reset not VLLS. See the Reset section details for more information. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 187 This field is reserved. Reserved NOTE: This reserved bit must remain cleared (set to 0). Bandgap Buffer Enable BGBE Enables the bandgap buffer. Bandgap buffer not enabled Bandgap buffer enabled KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 188 Memory map and register descriptions KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 189: Reset Control Module (Rcm)
This register includes read-only status flags to indicate the source of the most recent reset. The reset state of these bits depends on what caused the MCU to reset. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 190 Refer to the detailed MCG description for information on enabling the clock monitor. Reset not caused by a loss of external clock. Reset caused by a loss of external clock. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 191: System Reset Status Register 1 (Rcm_Srs1)
This read-only field is reserved and always has the value 0. This field is reserved. Reserved This read-only field is reserved and always has the value 0. Stop Mode Acknowledge Error Reset SACKERR Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 192: Reset Pin Filter Control Register (Rcm_Rpfc)
The bus clock filter is reset when disabled or when entering stop mode. The LPO filter is reset when disabled . Address: 4007_F000h base + 4h offset = 4007_F004h Read RSTFLTSS RSTFLTSRW Write Reset KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 193: Reset Pin Filter Width Register (Rcm_Rpfw)
Bus clock filter count is 2 00010 Bus clock filter count is 3 00011 Bus clock filter count is 4 00100 Bus clock filter count is 5 Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 194 Bus clock filter count is 28 11100 Bus clock filter count is 29 11101 Bus clock filter count is 30 11110 Bus clock filter count is 31 11111 Bus clock filter count is 32 KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 195: Bit Manipulation Engine (Bme)
KB space based at 0x400F_F000 for GPIO accesses. This organization provides compatibility with the Kinetis K Family. Attempted accesses to the memory space located between 0x4008_0000 - 0x400E_FFFF are error terminated due to an illegal address. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 196: Overview
16.1.2 Features The key features of the BME include: • Lightweight implementation of decorated storage for peripheral address space • Additional access semantics encoded into the reference address KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 197: Modes Of Operation
(mx_h{rdata, ready, resp}) which are outputs from BME. Likewise, the sx_h<signal> AHB bus is the primary output even though there are specific data phase signals (sx_h{rdata, ready, resp}) which are inputs to BME. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 198: Memory Map And Register Definition
AHB data phase. A generic timing diagram of a decorated store showing a bit field insert operation is shown as follows: KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 199 (reg_addr_data_dp); the input bus cycle is stalled (mx_hready = 0). 4. Cycle x+2, 2nd AHB data phase: Registered write data is sourced onto the output write data bus (sx_hwdata). KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 200 In the cycle definition tables, the notations AHB_ap and AHB_dp refer to the address and data phases of the BME AHB transaction. The cycle-by-cycle BME operations are detailed in the following table. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 201 & 0xE00FFFFF, size] // memory read tmp | wdata // modify mem[accessAddress & 0xE00FFFFF, size] = tmp // memory write The cycle-by-cycle BME operations are detailed in the following table. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 202 & 0xE00FFFFF, size] // memory read tmp ^ wdata // modify mem[accessAddress & 0xE00FFFFF, size] = tmp // memory write The cycle-by-cycle BME operations are detailed in the following table. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 203 "don't care". Note, unlike the other decorated store operations, BFI uses addr[19] as the least significant bit in the "w" specifier and not as an address bit. The decorated BFI write operation is defined in the following pseudo-code as: KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 204 BME AHB_dp <previous> Perform memory read; Form Perform write sending bit mask; Form bitwise registered data to memory ((mask) ? wdata : rdata)) and capture destination data in register KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 205: Bme Decorated Loads
+ 1bit sx_hwdata rdata sx_hrdata sx_hready BME States + Datapath control_state_dp1 control_state_dp2 4c.v_wxyz rdata + 1bit reg_addr_data_dp Figure 16-7. Decorated load: load-and-set 1-bit field insert timing diagram KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 206 AHB transaction cycle for cycle. A generic timing diagram of a decorated load showing an unsigned bit field operation is shown in the following figure. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 207 Any wait states inserted by the peripheral slave device (sx_hready = 0) are simply passed through the BME back to the master input bus, stalling the AHB transaction cycle for cycle. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 208 Perform memory read; Form Return extracted bit to master; bit mask; Extract bit from Perform write sending rdata; Form (rdata & ~mask) registered data to memory and capture destination data in register KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 209 Perform memory read; Form Return extracted bit to master; bit mask; Extract bit from Perform write sending rdata; Form (rdata | mask) registered data to memory and capture destination data in register KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 210 Stated differently, if (b + w+1) > container_width, only the low-order "container_width - b" bits are actually extracted. The cycle-by-cycle BME operations are detailed in the following table. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 211: Additional Details On Decorated Addresses And Gpio Accesses
Illegal addresses; attempted references are aborted and error terminated 0x400F_F000–0x400F_FFFF Undecorated (normal) GPIO accesses using standard address 0x4010_0000–0x43FF_FFFF Illegal addresses; attempted references are aborted and error terminated Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 212: Application Information
%[wdata];" "strh r2, [r3];" :: [addr] "r" (ADDR), [wdata] "r" (WDATA) : "r2", "r3"); #define IOORB(ADDR,WDATA) __asm("ldr r3, =(1<<27);" "orr r3, %[addr];" "mov r2, %[wdata];" "strb r2, [r3];" KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 213 :: [addr] "r" (ADDR), [wdata] "r" (WDATA) : "r2", "r3"); #define IOXORB(ADDR,WDATA) __asm("ldr r3, =(3<<26);" "orr r3, %[addr];" "mov r2, %[wdata];" "strb r2, [r3];" :: [addr] "r" (ADDR), [wdata] "r" (WDATA) : "r2", "r3"); KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 214 Application information KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 215: Miscellaneous Control Module (Mcm)
MCM memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) Crossbar Switch (AXBS) Slave Configuration F000_3008 0007h 17.2.1/216 (MCM_PLASC) Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 216: Crossbar Switch (Axbs) Slave Configuration (Mcm_Plasc)
Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port. A bus slave connection to AXBS input port n is absent. A bus slave connection to AXBS input port n is present. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 217: Crossbar Switch (Axbs) Master Configuration (Mcm_Plamc)
DFCS EFDS Description Speculation buffer is on for instruction and off for data. Speculation buffer is on for instruction and on for data. Speculation buffer is off. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 218 Enables stalling flash controller when flash is busy. Disable stalling flash controller when flash is busy. Enable stalling flash controller when flash is busy. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 219 Arbitration select Fixed-priority arbitration for the crossbar masters Round-robin arbitration for the crossbar masters Reserved This field is reserved. This read-only field is reserved and always has the value 0. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 220: Compute Operation Control Register (Mcm_Cpo)
Compute operation entry has completed or compute operation exit has not completed. Compute Operation request CPOREQ This bit is auto-cleared by vector fetching if CPOWOI = 1. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 221 Chapter 17 Miscellaneous Control Module (MCM) MCM_CPO field descriptions (continued) Field Description Request is cleared. Request Compute Operation. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 222 Memory map/register descriptions KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 223: Micro Trace Buffer (Mtb)
This document details the functionality of both the MTB_RAM and MTB_DWT capabilities. 18.1.1 Overview A generic block diagram of the processor core and platform for this class of ultra low-end microcontrollers is shown as follows: KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 224 PC value changes non-sequentially. A non-sequential PC change can occur during branch instructions or during exception entry. The processor can cause a trace packet to be generated for any instruction. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 225 For an exception return operation, two packets are generated: • The first packet has the: • Source address field set to the address of the instruction that causes the exception return, BX or POP. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 226: Features
• Program trace information in RAM available to MCU's application code or external debugger • Program trace watchpoint configuration accessible by MCU's application code or debugger • Location and size of RAM trace buffer is configured by software KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 227: Modes Of Operation
PC >> 1. ATOMIC Input Indicates the processor is performing non-instruction related activities. EDBGRQ Output Request for the processor to enter the Debug state, if enabled, and halt. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 228: Memory Map And Register Definition
See section 18.3.1.3/ F000_0008 MTB Flow Register (MTB_FLOW) Undefined 18.3.1.4/ F000_000C MTB Base Register (MTB_BASE) Undefined 18.3.1.5/ F000_0F00 Integration Mode Control Register (MTB_MODECTRL) 0000_0000h Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 229 F000_0FF0 Component ID Register (MTB_COMPID0) See section 18.3.1.15/ F000_0FF4 Component ID Register (MTB_COMPID1) See section 18.3.1.15/ F000_0FF8 Component ID Register (MTB_COMPID2) See section 18.3.1.15/ F000_0FFC Component ID Register (MTB_COMPID3) See section KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 230 See the MTB_FLOW register description for more details. Address: F000_0000h base + 0h offset = F000_0000h POINTER Reset POINTER Reset KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 231 If MTB_FLOW[WATERMARK] is used to stop tracing or to halt the processor, MTB_MASTER[MASK] must still be set to a value that prevents MTB_POSITION[POINTER] from wrapping before it reaches the MTB_FLOW[WATERMARK] value. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 232 1, then only privileged AHB read and write accesses to the RAM are permitted and user accesses are RAZ/WI. The HPROT[1] signal determines if an access is a user or privileged mode reference. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 233 Cortex-M0+ processor to enter the Debug state. To enter Debug state, the Cortex-M0+ processor might have to perform additional branch type operations. Therefore, the MTB_FLOW[WATERMARK] field must be set below the final entry in the trace buffer region. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 234 Cortex-M0+ processor by asserting the EDBGRQ signal. If this field is 1 and WATERMARK is equal to MTB_POSITION[POINTER], then MTB_MASTER[EN] is AUTOSTOP automatically set to 0. This stops tracing. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 235 It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_0000h base + F00h offset = F000_0F00h MODECTRL Reset MTB_MODECTRL field descriptions Field Description MODECTRL Hardwired to 0x0000_0000 KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 236 0. It is hardwired to specific values used during the auto- discovery process by an external debug agent. Address: F000_0000h base + FA4h offset = F000_0FA4h TAGCLEAR Reset MTB_TAGCLEAR field descriptions Field Description TAGCLEAR Hardwired to 0x0000_0000 KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 237 Where functionality changes on a given security level, this change must be reported in this register. It is connected to specific signals used during the auto-discovery process by an external debug agent. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 238 This register indicates the device architecture. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_0000h base + FBCh offset = F000_0FBCh DEVICEARCH Reset MTB_DEVICEARCH field descriptions Field Description DEVICEARCH Hardwired to 0x4770_0A31. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 239 This register indicates the device type ID. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_0000h base + FCCh offset = F000_0FCCh DEVICETYPID Reset MTB_DEVICETYPID field descriptions Field Description DEVICETYPID Hardwired to 0x0000_0031. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 240: Mtb_Dwt Memory Map
See field descriptions for the reset values.x = Undefined at reset. MTB_COMPIDn field descriptions Field Description COMPID Component ID Component ID0 is hardwired to 0x0000_000D; ID1 to 0x0000_0090; ID2 to 0x0000_0005; ID3 to 0x0000_00B1. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 241 F000_1FE8 Peripheral ID Register (MTBDWT_PERIPHID2) See section 18.3.2.9/ F000_1FEC Peripheral ID Register (MTBDWT_PERIPHID3) See section 18.3.2.10/ F000_1FF0 Component ID Register (MTBDWT_COMPID0) See section Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 242 MTBDWT_CTRL[17] = CPIEVTENA = 0, no CPI counter overflow events MTBDWT_CTRL[16] = EXCTRCENA = 0, generation of exception trace disabled MTBDWT_CTRL[12] = PCSAMPLENA = 0, no periodic PC sample packets generated Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 243 Note the format of this mask field is different than the MTB_MASTER[MASK]. Address: F000_1000h base + 24h offset + (16d × i), where i=0d to 1d MASK Reset KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 244 An attempted write of a MASK value > 24 is limited by the MTBDWT hardware to 24. If MTBDWT_COMP0 is used as a data value comparator, then MTBDWT_MASK0 should be programmed to zero. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 245 If this read-only flag is asserted, it indicates the operation defined by the FUNCTION field occurred since the last read of the register. Reading the register clears this bit. No match. Match occurred. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 246 0100 Instruction fetch. 0101 Data operand read. 0110 Data operand write. 0111 Data operand (read + write). others Reserved. Any attempts to use this value results in UNPREDICTABLE behavior. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 247 If this read-only flag is asserted, it indicates the operation defined by the FUNCTION field occurred since the last read of the register. Reading the register clears this bit. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 248 MTB's control logic by setting the appropriate enable bits, MTB_MASTER[TSTARTEN, TSTOPEN]. In the event of simultaneous assertion of both TSTART and TSTOP, TSTART takes priority. Address: F000_1000h base + 200h offset = F000_1200h NUMCOMP Reset KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 249 • Data match in MTBDWT_COMP0 and address match in MTBDWT_COMP1 when MTBDWT_FCT0[DATAVMATCH, DATAVADDR0] = {1,1} Trigger TSTOP based on the assertion of MTBDWT_FCT0[MATCHED]. Trigger TSTART based on the assertion of MTBDWT_FCT0[MATCHED]. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 250 This register indicates the device type ID. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_1000h base + FCCh offset = F000_1FCCh DEVICETYPID Reset MTBDWT_DEVICETYPID field descriptions Field Description DEVICETYPID Hardwired to 0x0000_0004. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 251 See field descriptions for the reset values.x = Undefined at reset. MTBDWT_COMPIDn field descriptions Field Description COMPID Component ID Component ID0 is hardwired to 0x0000_000D; ID1 to 0x0000_0090; ID2 to 0x0000_0005; ID3 to 0x0000_00B1. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 252: System Rom Memory Map
See section 18.3.3.1/ F000_2008 Entry (ROM_ENTRY2) See section 18.3.3.2/ F000_200C End of Table Marker Register (ROM_TABLEMARK) 0000_0000h 18.3.3.3/ F000_2FCC System Access Register (ROM_SYSACCESS) 0000_0001h Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 253 Reset * Notes: • See field descriptions for reset values.x = Undefined at reset. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 254 This register indicates system access. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_2000h base + FCCh offset = F000_2FCCh SYSACCESS Reset ROM_SYSACCESS field descriptions Field Description SYSACCESS Hardwired to 0x0000_0001 KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 255 See field descriptions for reset values.x = Undefined at reset. ROM_COMPIDn field descriptions Field Description COMPID Component ID Component ID0 is hardwired to 0x0000_000D; ID1 to 0x0000_0010; ID2 to 0x0000_0005; ID3 to 0x0000_00B1. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 256 Memory map and register definition KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 257: Crossbar Switch Lite (Axbs-Lite)
• Programmable configuration for fixed-priority or round-robin slave port arbitration 19.2 Memory Map / Register Definition This crossbar switch is designed for minimal gate count. It, therefore, has no memory- mapped configuration registers. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 258: Functional Description
This is done to save the initial clock of arbitration delay that otherwise would be seen if the master had to arbitrate to gain control of the slave port. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 259: Arbitration
Table 19-1. How AXBS grants control of a slave port to a master When Then AXBS grants control to the requesting master Both of the following are true: At the next clock edge Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 260: Initialization/Application Information
19.4 Initialization/application information No initialization is required for the crossbar switch. See the AXBS section of the configuration chapter for the reset state of the arbitration scheme. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 261: Peripheral Bridge (Aips-Lite)
The peripheral bridge performs a bus protocol conversion of the master transactions and generates the following as inputs to the peripherals: • Module enables • Module addresses KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 262: Functional Description
Bus decomposition is terminated by a transfer error caused by an access to an empty register area. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 263: Multipurpose Clock Generator (Mcg)
• Option to program and maximize DCO output frequency for a low frequency external reference clock source. • Option to prevent FLL from resetting its current locked frequency when switching clock modes if FLL reference frequency is not changed. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 264 • MCG Fixed Frequency Clock (MCGFFCLK) is provided as a clock source for other on-chip peripherals • MCG Internal Reference Clock (MCGIRCLK) is provided as a clock source for other on-chip peripherals KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 265 Peripheral BUSCLK Multipurpose Clock Generator (MCG) Figure 21-1. Multipurpose Clock Generator (MCG) block diagram NOTE Refer to the chip configuration chapter to identify the oscillator used in this MCU. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 266: Modes Of Operation
MCG Auto Trim Compare Value Low Register 4006_400B 21.3.9/274 (MCG_ATCVL) 21.3.1 MCG Control 1 Register (MCG_C1) Address: 4006_4000h base + 0h offset = 4006_4000h Read CLKS FRDIV IREFS IRCLKEN IREFSTEN Write Reset KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 267: Mcg Control 2 Register (Mcg_C2)
Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode. 21.3.2 MCG Control 2 Register (MCG_C2) Address: 4006_4000h base + 1h offset = 4006_4001h Read LOCRE0 FCFTRIM RANGE0 HGO0 EREFS0 IRCS Write Reset KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 268 FLL is disabled in bypass modes (lower power) Internal Reference Clock Select IRCS Selects between the fast or slow internal reference clock source. Slow internal reference clock selected. Fast internal reference clock selected. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 269: Mcg Control 3 Register (Mcg_C3)
DCO Maximum Frequency with 32.768 kHz Reference DMX32 The DMX32 bit controls whether the DCO frequency range is narrowed to its maximum frequency with a 32.768 kHz reference. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 270 1. A value for FCTRIM is loaded during reset from a factory programmed location. 2. A value for SCFTRIM is loaded during reset from a factory programmed location . KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 271: Mcg Control 6 Register (Mcg_C6)
MCG_S field descriptions Field Description 7–5 Reserved Reserved This field is reserved. This read-only field is reserved and always has the value 0. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 272: Mcg Status And Control Register (Mcg_Sc)
NOTE: ATME deasserts after the Auto Trim Machine has completed trimming all trim bits of the IRCS clock selected by the ATMS bit. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 273 CME0 is set. This bit is cleared by writing a logic 1 to it when set. Loss of OSC0 has not occurred. Loss of OSC0 has occurred. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 274: Mcg Auto Trim Compare Value High Register (Mcg_Atcvh)
21.4.1 MCG mode state diagram The seven states of the MCG are shown in the following figure and are described in Table 21-11. The arrows indicate the permitted MCG mode transitions. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 275 FLL Engaged External FLL engaged external (FEE) mode is entered when all the following conditions occur: (FEE) • 00 is written to C1[CLKS] Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 276 • 0 is written to C1[IREFS] • 1 is written to C2[LP] In BLPE mode, MCGOUTCLK is derived from the external reference clock. The FLL is disabled Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 277 FLL remains unlocked for several reference cycles. DCO startup time is equal to the FLL acquisition time. After the selected DCO startup time is over, the FLL is locked. The completion of the switch is shown by the C4[DRST_DRS] read bits. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 278: Low Power Bit Usage
MCGOUTCLK frequency if the MCG is in FEI mode. Additionally, this clock can be enabled in Stop mode by setting C1[IRCLKEN] and C1[IREFSTEN], otherwise this clock is disabled in Stop mode. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 279: External Reference Clock
The MCG Auto Trim (ATM) is a MCG feature that when enabled, it configures the MCG hardware to automatically trim the MCG Internal Reference Clocks using an external clock as a reference. The selection between which MCG IRC clock gets tested and KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 280 128 before storing it in the ATCV register. Therefore, the ATCV Expected Count Value for trimming the 4 MHz IRC is calculated using the following formula. (128) KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 281: Initialization / Application Information
• If entering FBE, clear the C1[IREFS] bit to switch to the external reference and change the C1[CLKS] bits to 2'b10 so that the external reference clock is selected as the system clock source. The C1[FRDIV] bits should also be set KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 282 32.768 kHz reference is desired, set C4[DRST_DRS] bits to 2'b00 and set C4[DMX32] bit to 1. The resulting DCO output (MCGOUTCLK) frequency with the new multiplier of 732 will be 24 MHz. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 283: Using A 32.768 Khz Reference
If C4[DRST_DRS] bits are set to 2'b01, the multiplication factor is doubled to 1280, and the resulting DCO output frequency is 41.94 MHz at mid-low-range. If C4[DRST_DRS] bits are set to 2'b10, the multiplication factor is set to 1920, and the KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 284: Mcg Mode Switching
Selectable between slow and fast BLPE (Bypassed low power external) OSCCLK 1. FLL_R is the reference divider selected by the C1[FRDIV] bits, F is the FLL factor selected by C4[DRST_DRS] and C4[DMX32] bits. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 285 Chapter 21 Multipurpose Clock Generator (MCG) This section will include three mode switching examples using an MHz external crystal. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 286 Initialization / Application information KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 287: Oscillator (Osc)
• Optionally external input bypass clock from EXTAL signal directly • One clock for MCU clock system • Two clocks for on-chip peripherals that can work in Stop modes Functional Description describes the module's operation in more detail. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 288: Block Diagram
Figure 22-1. OSC Module Block Diagram 22.4 OSC Signal Descriptions The following table shows the user-accessible signals available for the OSC module. Refer to signal multiplexing information for this MCU for more details. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 289: External Crystal / Resonator Connections
Low-frequency (32 kHz), low-power Connection 1 XTAL EXTAL Crystal or Resonator Figure 22-2. Crystal/Ceramic Resonator Connections - Connection 1 XTAL EXTAL Crystal or Resonator Figure 22-3. Crystal/Ceramic Resonator Connections - Connection 2 KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 290: External Clock Connections
In external clock mode, the pins can be connected as shown below. NOTE XTAL can be used as a GPIO when the GPIO alternate function is configured for it. XTAL EXTAL Clock Input Figure 22-5. External Clock Connections KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 291: Memory Map/Register Definitions
External reference clock is enabled. This field is reserved. Reserved This read-only field is reserved and always has the value 0. External Reference Stop Enable EREFSTEN Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 292: Functional Description
22.8.1 OSC Module States The states of the OSC module are shown in the following figure. The states and their transitions between each other are described in this section. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 293 MCU, refer to the chip configuration chapter. The EXTAL and XTAL pins are also decoupled from all other oscillator circuitry in this state. The OSC module circuitry is configured to draw minimal current. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 294: Osc Module Modes
(MCG, Timer, and so on) is configured to use the oscillator output clock (OSC_CLK_OUT). Table 22-7. Oscillator Modes Mode Frequency Range Low-frequency, low-power (VLP) (1 kHz) up to f (32.768 kHz) osc_lo osc_lo KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 295: Counter
Oscillator mode, but requires only the EXTAL pin in External clock mode. The EXTAL and XTAL pins are available for I/O. For the implementation of these pins on this device, refer to the Signal Multiplexing chapter. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 296: Reset
Very Low Leakage Stop (VLLSx) modes, all OSC register bits are reset and initialization is required through software. 22.11 Interrupts The OSC module does not generate any interrupts. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 297: Flash Memory Controller (Fmc)
• Interface between bus masters and the 32-bit program flash memory: • 8-bit, 16-bit, and 32-bit read operations to nonvolatile flash memory. • Acceleration of data transfer from the program flash memory to the device: KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 298: Modes Of Operation
(when enabled), the requested data is transferred within a single system clock. Upon system reset, the FMC is configured as follows: • Flash cache is enabled. • Instruction speculation and caching are enabled. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 299 When reconfiguring the FMC, do not program the control and configuration inputs to the FMC while the program flash memory is being accessed. Instead, change them with a routine executing from RAM in supervisor mode. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 300 Functional description KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 301: Flash Memory Module (Ftfa)
('1') states and/or programmed ('0') states. Therefore, it is recommended that each flash block or sector be re-erased immediately prior to factory programming to ensure that the full data retention capability is achieved. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 302: Features
• Supports MCU security mechanisms which prevent unauthorized access to the flash memory contents 24.1.2 Block Diagram The block diagram of the flash memory module is shown in the following figure. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 303: Glossary
The CPU or other bus masters initiate flash program and erase operations (or other flash commands) using writes to the FCCOB register group in the flash memory module. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 304: External Signal Description
This section describes the memory map and registers for the flash memory module. Data read from unimplemented memory space in the flash memory module is undefined. Writes to unimplemented or reserved memory space (registers) in the flash memory module are ignored. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 305: Program Flash Ifr Map
The user can program the Program Once Field one time only as there is no program flash IFR erase mechanism available to the KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 306: Register Descriptions
Flash Common Command Object Registers 24.3.3.5/ 4002_0008 (FTFA_FCCOB7) Flash Common Command Object Registers 24.3.3.5/ 4002_0009 (FTFA_FCCOB6) Flash Common Command Object Registers 24.3.3.5/ 4002_000A (FTFA_FCCOB5) Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 307 (by writing a one to it). Address: 4002_0000h base + 0h offset = 4002_0000h Read CCIF RDCOLERR ACCERR FPVIOL MGSTAT0 Write Reset KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 308 CCIF=1 and before the next command has been launched. At some point during the execution of "command-N+1," the previous result is discarded and any previous error is cleared. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 309 4. release MCU security by setting the FSEC[SEC] field to the unsecure state. Erase Suspend ERSSUSP The ERSSUSP bit allows the user to suspend (interrupt) the Erase Flash Sector command while it is executing. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 310 Backdoor key access disabled (preferred KEYEN state to disable backdoor key access) Backdoor key access enabled Backdoor key access disabled 5–4 Mass Erase Enable Bits MEEN Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 311 During the reset sequence, the register is loaded from the flash nonvolatile option byte in the Flash Configuration Field located in program flash memory. The flash basis for the values is signified by X in the reset value. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 312 This 8-bit value defines the command to be executed. The command code is followed by the parameters required for this specific flash command, typically an address and/or data values. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 313 KB of program flash memory or less, FPROT1 is not used. For configurations with 8 KB of program flash memory, FPROT2 is not used. The bitfields are defined in each register as follows: KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 314 Trying to alter data in any protected area in the program flash memory results in a protection violation error and sets the FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible if it contains any protected region. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 315: Functional Description
Program flash size / 32 FPROT3[PROT3] Program flash size / 32 FPROT0[PROT29] Program flash size / 32 FPROT0[PROT30] Program flash size / 32 FPROT0[PROT31] Last program flash address Figure 24-24. Program flash protection KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 316: Interrupts
MCU is allowed to enter stop mode. CAUTION The MCU should never enter stop mode while any flash command is running (CCIF = 0). KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 317: Functional Modes Of Operation
The user cannot initiate any further flash commands until notified that the current command has completed. The flash command structure and operation are detailed in Flash Command Operations. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 318 (FSTAT[ACCERR]=1) or a protection violation (FSTAT[FPVIOL]=1). In error scenarios, two writes to FSTAT are required to initiate the next command: the first write clears the error flags, the second write clears CCIF. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 319 4. The flash memory module sets the FSTAT[CCIF] bit signifying that the command has completed. The flow for a generic command write sequence is illustrated in the following figure. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 320 IFR, ID Read 4 bytes from program flash IFR or version ID. 0x06 Program Longword × Program 4 bytes in a program flash block. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 321 0x43 Program Once × × × × — — 0x44 Erase All Blocks × × × × × — Verify Backdoor Access 0x45 × × × × — — KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 322: Margin Read Commands
'factory' margin levels, the flash memory contents should be erased and reprogrammed. CAUTION Factory margin levels must only be used during verify of the initial factory programming. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 323: Flash Command Description
Number of longwords to be verified [15:8] Number of longwords to be verified [7:0] Read-1 Margin Choice 1. Must be longword aligned (Flash address [1:0] = 00). KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 324 Flash address [7:0] Margin Choice Byte 0 expected data Byte 1 expected data Byte 2 expected data Byte 3 expected data 1. Must be longword aligned (Flash address [1:0] = 00). KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 325 The special-purpose memory resources available include program flash IFR space and the Version ID field. Each resource is assigned a select code as shown in Table 24-33. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 326 FSTAT[ACCERR] Flash address is not longword aligned FSTAT[ACCERR] 24.4.10.4 Program Longword Command The Program Longword command programs four previously-erased bytes in the program flash memory using an embedded algorithm. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 327 FSTAT[ACCERR] An invalid flash address is supplied FSTAT[ACCERR] Flash address is not longword aligned FSTAT[ACCERR] Flash address points to a protected area FSTAT[FPVIOL] Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 328 Erase Flash Sector command. During the Erase Flash Sector operation (see Erase Flash Sector Command), the flash memory module samples the state of the ERSSUSP bit at convenient points. If the flash memory module detects that the KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 329 Data in this sector is not reliable until a new erase command fully completes. The following figure shows how to suspend and resume the Erase Flash Sector operation. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 330 ERSSCR Suspended Resume Erase? ERSSUSP: Bit in FCNFG register No, Abort SUSPACK: Internal Suspend Acknowledge Clear ERSSUSP User Cmd Interrupt/Suspend Figure 24-26. Suspend and Resume of Erase Flash Sector Operation KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 331 Apply the 'Factory' margin to the normal read-1 level Table 24-41. Read 1s All Blocks Command Error Handling Error Condition Error Bit An invalid margin choice is specified FSTAT[ACCERR] Read-1s fails FSTAT[MGSTAT0] KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 332 Command) or using the Read Resource command (see Read Resource Command). Each Program Once record can be programmed only once since the program flash 0 IFR cannot be erased. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 333 1. If a Program Once record is initially programmed to 0xFFFF_FFFF, the Program Once command is allowed to execute again on that same record. 24.4.10.9 Erase All Blocks Command The Erase All Blocks operation erases all flash memory, verifies all memory contents, and releases MCU security. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 334 The status of the erase-all request is reflected in the FCNFG[ERSAREQ] bit. The FCNFG[ERSAREQ] bit is cleared once the operation completes and the normal FSTAT error reporting is available as described in Erase All Blocks Command. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 335 Table 24-49. Verify Backdoor Access Key Command Error Handling Error Condition Error Bit The supplied key is all-0s or all-Fs FSTAT[ACCERR] An incorrect backdoor key is supplied FSTAT[ACCERR] Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 336: Security
Table 24-51. Flash Memory Access Summary Chip Security State Operating Mode Unsecure Secure NVM Normal Full command set Only the Erase All Blocks and Read 1s All NVM Special Full command set Blocks commands. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 337 FSEC register only. It does not alter the security byte or the keys stored in the Flash Configuration Field (Flash Configuration Field Description). After the next reset of the chip, the security state of the flash memory KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 338: Reset Sequence
If a reset occurs while any flash command is in progress, that command is immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. Commands and operations do not automatically resume after exiting reset. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 339: Analog-To-Digital Converter (Adc)
• Single or continuous conversion, that is, automatic return to idle after single conversion • Configurable sample time and conversion speed/power • Conversion complete/hardware average complete flag and interrupt KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 340: Block Diagram
• Temperature sensor • Hardware average function • Selectable voltage reference: external or alternate • Self-Calibration mode 25.1.2 Block diagram The following figure is the ADC module block diagram. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 341: Adc Signal Descriptions
The ADC module supports up to 24 single-ended inputs. The ADC also requires four supply/reference/ground connections. NOTE Refer to ADC configuration section in chip configuration chapter for the number of channels supported on this device. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 342: Analog Power (Vdda)
ADC Status and Control Registers 1 (ADC0_SC1B) 0000_001Fh 25.3.1/343 4003_B008 ADC Configuration Register 1 (ADC0_CFG1) 0000_0000h 25.3.2/347 4003_B00C ADC Configuration Register 2 (ADC0_CFG2) 0000_0000h 25.3.3/348 Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 343: Adc Status And Control Registers 1 (Adcx_Sc1N)
Writing SC1A while SC1A is actively controlling a conversion aborts the current conversion. In Software Trigger mode, when SC2[ADTRG]=0, writes to SC1A subsequently initiate a new conversion, if SC1[ADCH] contains a value other than all 1s. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 344 SC1B–SC1n registers do not initiate a new conversion. Address: 4003_B000h base + 0h offset + (4d × i), where i=0d to 1d Reset KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 345 Enables conversion complete interrupts. When COCO becomes set while the respective AIEN is high, an interrupt is asserted. Conversion complete interrupt is disabled. Conversion complete interrupt is enabled. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 346 Voltage reference selected is determined by SC2[REFSEL]. REFSH 11110 is selected as input. Voltage reference selected is determined by SC2[REFSEL]. REFSL 11111 Module is disabled. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 347: Adc Configuration Register 1 (Adcx_Cfg1)
When ADLSMP=1, the long sample time select bits, (ADLSTS[1:0]), can select the extent of the long sample time. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 348: Adc Configuration Register 2 (Adcx_Cfg2)
Configuration Register 2 (CFG2) selects the special high-speed configuration for very high speed conversions and selects the long sample time duration during long sample mode. Address: 4003_B000h base + Ch offset = 4003_B00Ch Reset ADLSTS Reset KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 349: Adc Data Result Register (Adcx_Rn)
Unused bits in R n are cleared in unsigned right-aligned modes and carry the sign bit (MSB) in sign-extended 2's complement modes. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 350: Compare Value Registers (Adcx_Cvn)
Therefore, the compare function uses only the CVn fields that are related to the ADC mode of operation. The compare value 2 register (CV2) is used only when the compare range function is enabled, that is, SC2[ACREN]=1. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 351: Status And Control Register 2 (Adcx_Sc2)
The status and control register 2 (SC2) contains the conversion active, hardware/software trigger select, compare function, and voltage reference select of the ADC module. Address: 4003_B000h base + 20h offset = 4003_B020h Reset REFSEL Reset KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 352 . This pair may be additional external pins or ALTH ALTL internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 353: Status And Control Register 3 (Adcx_Sc3)
Begins the calibration sequence when set. This field stays set while the calibration is in progress and is cleared when the calibration sequence is completed. CALF must be checked to determine the result of the Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 354 Hardware Average Select Determines how many ADC conversions will be averaged to create the ADC average result. 4 samples averaged. 8 samples averaged. 16 samples averaged. 32 samples averaged. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 355: Adc Offset Correction Register (Adcx_Ofs)
Otherwise, the gain error specifications may not be met. Address: 4003_B000h base + 2Ch offset = 4003_B02Ch Reset KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 356: Adc Plus-Side General Calibration Value Register (Adcx_Clpd)
This read-only field is reserved and always has the value 0. CLPD Calibration Value 25.3.11 ADC Plus-Side General Calibration Value Register (ADCx_CLPS) For more information, see CLPD register description. Address: 4003_B000h base + 38h offset = 4003_B038h CLPS Reset KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 357: Adc Plus-Side General Calibration Value Register (Adcx_Clp4)
Address: 4003_B000h base + 40h offset = 4003_B040h CLP3 Reset ADCx_CLP3 field descriptions Field Description 31–9 This field is reserved. Reserved This read-only field is reserved and always has the value 0. CLP3 Calibration Value KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 358: Adc Plus-Side General Calibration Value Register (Adcx_Clp2)
Address: 4003_B000h base + 48h offset = 4003_B048h CLP1 Reset ADCx_CLP1 field descriptions Field Description 31–7 This field is reserved. Reserved This read-only field is reserved and always has the value 0. CLP1 Calibration Value KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 359: Adc Plus-Side General Calibration Value Register (Adcx_Clp0)
The ADC module has the capability of automatically averaging the result of multiple conversions. The hardware average function is enabled by setting SC3[AVGE] and operates in any of the conversion modes and configurations. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 360: Clock Select And Divide Control
(V and V ) used for conversions. Each pair contains a REFSH REFSL positive reference that must be between the minimum Ref Voltage High and V , and a KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 361: Hardware Trigger And Channel Selects
When the conversion is completed, the result is placed in the Rn registers associated with the ADHWTSn received. For example: • ADHWTSA active selects RA register • ADHWTSn active selects Rn register KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 362: Conversion Control
ADHWTSn prior to a conversion completion. • Following the transfer of the result to the data registers when continuous conversion is enabled, that is, when SC3[ADCO] = 1. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 363 • A write to any ADC register besides the SC1A-SC1n registers occurs. This indicates that a change in mode of operation has occurred and the current conversion is therefore invalid. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 364 CFG2[ADHSC]=1, there is an additional 2-cycle adder on any conversion. The table below summarizes sample times for the possible ADC configurations. ADC configuration Sample time (ADCK cycles) CFG1[ADLSMP] CFG2[ADLSTS] CFG2[ADHSC] First or Single Subsequent KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 365 5 μs + 3 ADCK cycles + 5 bus clock cycles 0x, 10 5 ADCK cycles + 5 bus clock cycles 5 ADCK cycles + 5 bus clock cycles Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 366 CFG2[ADHSC] High-speed conversion time adder (HSCAdder) 0 ADCK cycles 2 ADCK cycles Note The ADCK frequency must be between f minimum and ADCK maximum to meet ADC specifications. ADCK KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 367 The conversion time for this conversion is calculated by using the Equation 1 on page 365, and the information provided in Table 25-54 through Table 25-58. The table below lists the variables of Equation 1 on page 365. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 368: Automatic Compare Function
The hardware average function can perform conversions on a channel while the MCU is in Wait or Normal Stop modes. The ADC interrupt wakes the MCU when the hardware average is completed if SC1n[AIEN] is set. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 369 The same compare function definitions apply. An ADC interrupt is generated when SC1n[COCO] is set and the respective ADC interrupt is enabled, that is, SC1n[AIEN]=1. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 370: Calibration Function
SC1n[COCO] will be set. SC1n[AIEN] can be used to allow an interrupt to occur at the end of a calibration sequence. At the end of the calibration routine, if SC3[CALF] is not set, the automatic calibration routine is completed successfully. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 371: User-Defined Offset Function
For example, in 8-bit single-ended mode, OFS[14:7] are subtracted from D[7:0]; OFS[15] indicates the sign (negative numbers are effectively added to the result) and OFS[6:0] are ignored. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 372: Temperature Sensor
25 °C. TEMP25 • m is referred as temperature sensor slope in the device data sheet. It is the hot or cold voltage versus temperature slope in V/°C. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 373: Mcu Wait Mode Operation
25.4.10 MCU Normal Stop mode operation Stop mode is a low-power consumption Standby mode during which most or all clock sources on the MCU are disabled. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 374: Mcu Low-Power Stop Mode Operation
Stop mode. Therefore, the module must be re-enabled and re-configured following exit from Low-Power Stop mode. NOTE For the chip specific modes of operation, see the power management information for the device. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 375: Initialization Information
(ADCO) and whether to perform hardware averaging. 5. Update SC1:SC1n registers to enable or disable conversion complete interrupts. Also, select the input channel which can be used to perform conversions. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 376 Bit 4:0 ADCH 00001 Input channel 1 selected as ADC input channel. RA = 0xxx Holds results of conversion. CV = 0xxx Holds compare value when compare function enabled. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 377: Application Information
MCU digital supply, V and V , and must be routed carefully for maximum noise immunity and bypass capacitors placed as near as possible to the package. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 378 Resistance in the path is not recommended because the current causes a voltage drop that could result in conversion errors. Inductance in this path must be minimum, that is, parasitic only. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 379: Sources Of Error
Figure 25-47. Sampling equation Where: RAS = External analog source resistance SC = Number of ADCK cycles used during sample window CADIN = Internal ADC input capacitance NUMTAU = -ln(LSBERR / 2 KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 380 Normal Stop reduces V noise but increases effective conversion time due to stop recovery. • There is no I/O switching, input or output, on the MCU during the conversion. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 381 The ADC may also exhibit non-linearity of several forms. Every effort has been made to reduce these errors, but the system designers must be aware of these errors because they affect overall accuracy: KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 382 • Missing codes: Missing codes are those values never converted for any input value. In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and have no missing codes. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 383: Comparator (Cmp)
26.2 CMP features The CMP has the following features: • Operational over the entire supply range • Inputs may range from rail to rail • Programmable hysteresis control KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 384: 6-Bit Dac Key Features
• Power Down mode to conserve power when not in use • Option to route the output to internal comparator input 26.4 ANMUX key features • Two 8-to-1 channel mux • Operational over the entire supply range KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 385: Cmp, Dac And Anmux Diagram
Reference Input 3 Reference Input 4 Sample input Reference Input 5 Reference Input 6 Window ANMUX and filter control CMPO MSEL[2:0] Figure 26-1. CMP, DAC and ANMUX block diagram KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 386: Cmp Block Diagram
• The Filter block acts as a simple sampler if the filter is bypassed and CR0[FILTER_CNT] is set to 0x01. • The Filter block filters based on multiple samples when the filter is bypassed and CR0[FILTER_CNT] is set greater than 0x01. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 387: Memory Map/Register Definitions
Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 388: Cmp Control Register 1 (Cmpx_Cr1)
At any given time, either SE or WE can be set. It is mandatory request to not set SE and WE both at a given time. Windowing mode is not selected. Windowing mode is selected. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 389 When the user selects the same input from analog mux to the positive and negative port, the comparator is disabled automatically. Analog Comparator is disabled. Analog Comparator is enabled. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 390: Cmp Filter Period Register (Cmpx_Fpr)
Enables the CFR interrupt from the CMP. When this field is set, an interrupt will be asserted when CFR is set. Interrupt is disabled. Interrupt is enabled. Comparator Interrupt Enable Falling Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 391: Dac Control Register (Cmpx_Daccr)
V is selected as resistor ladder network supply reference V. in2in VOSEL DAC Output Voltage Select Selects an output voltage from one of 64 distinct levels. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 392: Mux Control Register (Cmpx_Muxcr)
NOTE: When an inappropriate operation selects the same input for both muxes, the comparator automatically shuts down to prevent itself from becoming a noise generator. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 393: Functional Description
This is especially useful when implementing zero-crossing-detection for certain PWM applications. The comparator filter and sampling features can be combined as shown in the following table. Individual modes are discussed below. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 394 FTM, it must be configured to operate in Continuous mode so that an external fault can immediately pass through the comparator to the target fault circuitry. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 395 Clock COUTA CMPO to prescaler divided FILT_PER CGMUX clock Figure 26-15. Comparator operation in Continuous mode NOTE See the chip configuration section for the source of sample/ window input. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 396 In Sampled, Non-Filtered mode, the analog comparator block is powered and active. The path from analog inputs to COUTA is combinational unclocked. Windowing control is completely bypassed. COUTA is sampled whenever a rising-edge is detected on the filter block clock input. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 397 COUTA is sampled whenever a rising edge is detected on the filter block clock input. The only difference in operation between Sampled, Non-Filtered (# 3A) and Sampled, Filtered (# 4A) is that, now, CR0[FILTER_CNT]>1, which activates filter operation. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 398 CMPO COUT To other SOC functions WINDOW/SAMPLE bus clock Clock COUTA CMPO to prescaler divided FILT_PER CGMUX clock SE=1 Figure 26-18. Sampled, Filtered (# 4A): sampling point externally driven KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 399 WINDOW signal is high. In actual operation, COUTA may lag the analog inputs by up to one bus clock cycle plus the combinational path delay through the comparator and polarity select logic. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 400 COUTA CMPO to divided prescaler FILT_PER CGMUX clock SE=0 Figure 26-21. Windowed mode For control configurations which result in disabling the filter block, see Filter Block Bypass Logic diagram. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 401 Configuration for this mode is virtually identical to that for the Windowed/Filtered Mode shown in the next section. The only difference is that the value of CR0[FILTER_CNT] must be 1. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 402: Power Modes
Figure 26-23. Windowed/Filtered mode 26.8.2 Power modes 26.8.2.1 Wait mode operation During Wait and VLPW modes, the CMP, if enabled, continues to operate normally and a CMP interrupt can wake the MCU. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 403: Startup And Operation
When programmed for filtering modes, COUT will initially be equal to 0, until sufficient clock cycles have elapsed to fill all stages of the filter. This occurs even if COUTA is at a logic 1. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 404 Always switch to this setting prior to making any changes in filter parameters. This resets the filter to a known state. Switching CR0[FILTER_CNT] on the fly without this intermediate step can result in unexpected behavior. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 405 0x01 0x01 - 0xFF Windowed / Resampled + (FPR[FILT_PER] * mode ) + 2T > 0x01 0x01 - 0xFF Windowed / Filtered mode + (CR0[FILTER_CNT] * FPR[FILT_PER] x T KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 406: Cmp Interrupts
Control Register (DACCR). Its supply reference source can be selected from two sources and V . The module can be powered down or disabled when not in use. When in Disabled mode, DACO is connected to the analog ground. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 407: Dac Functional Description
26.12 DAC resets This module has a single reset input, corresponding to the chip-wide peripheral reset. 26.13 DAC clocks This module has a single clock input, the bus clock. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 408: Dac Interrupts
Upon setting TRIGM, the CMP and DAC are placed in a standby state until an external timer resource trigger is received. See the chip configuration chapter for details about the external timer resource. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 409: Timer/Pwm Module (Tpm)
• Can increment on rising edge of an external clock input synchronized to the asynchronous counter clock • Prescaler divide-by 1, 2, 4, 8, 16, 32, 64, or 128 • TPM includes a 16-bit counter KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 410: Modes Of Operation
MCU from stop mode. 27.1.4 Block Diagram The TPM uses one input/output (I/O) pin per channel, CHn (TPM channel (n)) where n is the channel number. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 411: Tpm Signal Descriptions
External clock. TPM external clock can be selected to increment the TPM counter on every rising edge synchronized to the counter clock. TPM_CHn TPM channel (n = 1 to 0) KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 412: Tpm_Chn - Tpm Channel (N) I/O Pin
4003_9010 Channel (n) Value (TPM1_C0V) 0000_0000h 27.3.5/417 4003_9014 Channel (n) Status and Control (TPM1_C1SC) 0000_0000h 27.3.4/416 4003_9018 Channel (n) Value (TPM1_C1V) 0000_0000h 27.3.5/417 Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 413: Status And Control (Tpmx_Sc)
Set by hardware when the TPM counter equals the value in the MOD register and increments. The TOF bit is cleared by writing a 1 to TOF bit. Writing a 0 to TOF has no effect. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 414: Counter (Tpmx_Cnt)
The CNT register contains the TPM counter value. Reset clears the CNT register. Writing any value to COUNT also clears the counter. When debug is active, the TPM counter does not increment unless configured otherwise. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 415: Modulo (Tpmx_Mod)
This field is reserved. Reserved This read-only field is reserved and always has the value 0. Modulo value When writing this field, all bytes must be written at the same time. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 416: Channel (N) Status And Control (Tpmx_Cnsc)
Output on match- down) Low-true pulses (set Output on match-up, clear Output on match- down) Address: Base address + Ch offset + (8d × i), where i=0d to 1d Reset KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 417: Channel (N) Value (Tpmx_Cnv)
These registers contain the captured TPM counter value for the input modes or the match value for the output modes. In input capture mode, any write to a CnV register is ignored. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 418: Capture And Compare Status (Tpmx_Status)
CHF remains set indicating another event has occurred. In this case a CHF interrupt request is not lost due to the clearing sequence for a previous CHF. Address: Base address + 50h offset Reset KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 419 See the register description. No channel event has occurred. A channel event has occurred. Channel 0 Flag CH0F See the register description. No channel event has occurred. A channel event has occurred. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 420: Configuration (Tpmx_Conf)
CSOT set. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 421: Functional Description
Reserved This field is reserved. This read-only field is reserved and always has the value 0. 27.4 Functional Description The following sections describe the TPM features. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 422: Clock Domains
The selected counter clock source passes through a prescaler that is a 7-bit counter. The value of the prescaler is selected by the PS[2:0] bits. The following figure shows an example of the prescaler counter and TPM counter. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 423: Counter
The TPM period when using up counting is (MOD + 0x0001) × period of the TPM counter clock. The TOF bit is set when the TPM counter changes from MOD to zero. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 424 The TPM period when using up-down counting is 2 × MOD × period of the TPM counter clock. The TOF bit is set when the TPM counter changes from MOD to (MOD – 1). KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 425: Input Capture Mode
4, which is required to meet Nyquist criteria for signal sampling. Writes to the CnV register are ignored in input capture mode. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 426: Output Compare Mode
(logic 0 for set/toggle/pulse high and logic one for clear/ pulse low). The CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1) at the channel (n) match (TPM counter = CnV). KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 427: Edge-Aligned Pwm (Epwm) Mode
CnV register, the CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1), however the channel (n) output is not modified and controlled by TPM. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 428 If (ELSnB:ELSnA = X:1), then the channel (n) output is forced low at the counter overflow (when zero is loaded into the TPM counter), and it is forced high at the channel (n) match (TPM counter = CnV) (see the following figure). KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 429: Center-Aligned Pwm (Cpwm) Mode
The other channel modes are not designed to be used with the up-down counter (CPWMS = 1). Therefore, all TPM channels should be used in CPWM mode when (CPWMS = 1). KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 430 (n) match in channel (n) match in down counting up counting down counting channel (n) output CHnF bit previous value TOF bit Figure 27-47. CPWM signal with ELSnB:ELSnA = X:1 KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 431: Registers Updated From Write Buffers
TPM counter changes from MOD to zero. • If the selected mode is CPWM then CnV register is updated after CnV register was written and the TPM counter changes from MOD to (MOD – 1). KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 432: Reset Overview
The timer overflow interrupt is generated when (TOIE = 1) and (TOF = 1). 27.4.10.2 Channel (n) Interrupt The channel (n) interrupt is generated when (CHnIE = 1) and (CHnF = 1). KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 433: Low-Power Timer (Lptmr)
• Configurable clock source for prescaler/glitch filter • Configurable input source for pulse counter • Rising-edge or falling-edge 28.1.2 Modes of operation The following table describes the operation of the LPTMR module in various modes. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 434: Lptmr Signal Descriptions
CNR to increment. Timing Assertion or deassertion may occur at any time; input may assert asynchronously to the bus clock. 28.3 Memory map and register definition KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 435: Low Power Timer Control Status Register (Lptmrx_Csr)
LPTMR is disabled. The input connections vary by device. See the chip configuration details for information on the connections to these inputs. Pulse counter input 0 is selected. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 436: Low Power Timer Prescale Register (Lptmrx_Psr)
LPTMR is disabled and internal logic is reset. LPTMR is enabled. 28.3.2 Low Power Timer Prescale Register (LPTMRx_PSR) Address: 4004_0000h base + 4h offset = 4004_0004h Reset PRESCALE PBYP Reset KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 437 LPTMR is disabled. The clock connections vary by device. NOTE: See the chip configuration details for information on the connections to these inputs. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 438: Low Power Timer Compare Register (Lptmrx_Cmr)
Address: 4004_0000h base + Ch offset = 4004_000Ch COUNTER Reset LPTMRx_CNR field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. COUNTER Counter Value KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 439: Functional Description
28.4.3 LPTMR prescaler/glitch filter The LPTMR prescaler and glitch filter share the same logic which operates as a prescaler in Time Counter mode and as a glitch filter in Pulse Counter mode. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 440 CNR can increment is once every 2 to 2 prescaler clock edges. When first enabled, the glitch filter will wait an additional one or two prescaler clock edges due to synchronization logic. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 441: Lptmr Compare
When reading the CNR, the bus clock must be at least two times faster than the rate at which the LPTMR counter is incrementing, otherwise incorrect data may be returned. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 442 The LPTMR interrupt is generated asynchronously to the system clock and can be used to generate a wakeup from any low-power mode, including the low-leakage modes, provided the LPTMR is enabled as a wakeup source. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 443 The SPI includes these distinctive features: • Master mode or slave mode operation • Full-duplex or single-wire bidirectional mode • Programmable transmit bit rate • Double-buffered transmit and receive data register KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 444 When the CPU wakes from these Stop modes, all SPI register content is reset. Detailed descriptions of operating modes appear in Low-power mode options. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 445 SPIx_D. Pin multiplexing logic controls connections between MCU pins and the SPI module. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 446 MSTR SLAVE MODE SELECT MOD- SSOE MODE FAULT DETECTION SPRF 8-BIT COMPARATOR SPMF SPIxM SPMIE SPTEF SPTIE INTERRUPT MODF REQUEST SPIE Figure 29-2. SPI module block diagram without FIFO KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 447 (BIDIROE is 0) or an output (BIDIROE is 1). If SPC0 is 1 and master mode is selected, this pin is not used by the SPI and reverts to other functions (based on chip configuration). KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 448 This read/write register includes the SPI enable control, interrupt enables, and configuration options. Address: 4007_6000h base + 0h offset = 4007_6000h Read SPIE SPTIE MSTR CPOL CPHA SSOE LSBFE Write Reset KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 449 This bit is used in combination with the Mode Fault Enable (MODFEN) field in the C2 register and the Master/Slave (MSTR) control bit to determine the function of the SS pin. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 450 In master mode, this bit determines how the SS pin is used. For details, refer to the description of the SSOE bit in the C1 register. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 451 Use this register to set the prescaler and bit rate divisor for an SPI master. This register may be read or written at any time. Address: 4007_6000h base + 2h offset = 4007_6002h Read SPPR[2:0] SPR[3:0] Write Reset KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 452 This register contains read-only status bits. Writes have no meaning or effect. NOTE Bits 3 through 0 are not implemented and always read 0. Address: 4007_6000h base + 3h offset = 4007_6003h Read SPRF SPMF SPTEF MODF Write Reset KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 453 When the SPI is configured as a master, data queued in the transmit data buffer is transmitted immediately after the previous transmission has completed. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 454 SPI Match Flag in the S register (S[SPMF]) sets. Address: 4007_6000h base + 7h offset = 4007_6007h Read Bits[7:0] Write Reset SPI0_M field descriptions Field Description Bits[7:0] Hardware compare value (low byte) KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 455 S[SPTEF] = 1 and writing to the master SPI data registers. If the shift register is empty, the byte immediately transfers to the shift register. The data begins shifting out on the MOSI pin under the control of the serial clock. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 456 SPI into idle state. The remote slave cannot detect this, therefore the master has to ensure that the remote slave is set back to idle state. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 457 Even numbered edges cause the value previously latched from the serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on the LSBFE bit. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 458 SPSCK cycle before the start of the transfer and goes back high at the end of the eighth bit time of the transfer. The SS IN waveform applies to the slave select input of a slave. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 459 2. A new data byte is written to the transmit buffer before the in-progress transmission is complete. 3. When the in-progress transmission is complete, the new, ready data byte is transmitted immediately. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 460 LSB FIRST BIT 0 BIT 1 BIT 5 BIT 6 BIT 7 MISO (SLAVE OUT) SS OUT (MASTER) SS IN (SLAVE) Figure 29-16. SPI clock formats (CPHA = 0) KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 461 1, 2, 3, 4, 5, 6, 7, or 8 BIT RATE 256, or 512 SPPR2:SPPR1:SPPR0 SPR3:SPR2:SPR1:SPR0 Figure 29-17. SPI baud rate generation 29.4.6 Special features The following section describes the special features of SPI module. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 462 The same pin is also the serial input to the shift register. The SPSCK is an output for the master mode and an input for the slave mode. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 463 MOMI (MOSI in bidirectional mode) is cleared if it was set. No mode fault error occurs in the bidirectional mode for the SPI system configured in slave mode. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 464 Otherwise, if the slave is currently sending the last data received byte from the master, it continues to send each previously received data from the master byte). KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 465 • If a data transmission occurs in slave mode after a reset without a write to SPIx_D, the transmission consists of "garbage" or the data last received from the master before the reset. • Reading from SPIx_D after reset always returns zeros. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 466 (that is, SPRF remains active throughout another transfer), the subsequent transfers are ignored and no new data is copied into the Data register. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 467 This section discusses an example of how to initialize and use the SPI. 29.5.1 Initialization sequence Before the SPI module can be used for communication, an initialization procedure must be carried out, as follows: KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 468 Bit 6 Unimplemented Bit 5 Reserved Bit 4 MODFEN Disables mode fault function Bit 3 BIDIROE SPI data I/O pin acts as input Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 469 Holds bits 0–7 of the hardware match buffer. SPIx_D = 0xxx Holds bits 0–7 of the data to be transmitted by the transmit buffer and received by the receive buffer. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 470 SPRF = 1 READ SPIxD SPMF = 1 READ SPMF WHILE SET TO CLEAR FLAG, THEN WRITE A 1 TO IT CONTINUE Figure 29-18. Initialization Flowchart Example for SPI Master Device KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 471 • START and STOP signal generation and detection • Repeated START signal generation and detection • Acknowledge bit generation and detection • Bus busy detection • General call recognition • 10-bit address extension KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 472 Stop mode. The STOP instruction does not affect the I2C module's register states. 30.1.3 Block diagram The following figure is a functional block diagram of the I2C module. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 473 C system. Bidirectional serial data line of the I C system. 30.3 Memory map and register descriptions This section describes in detail all I2C registers accessible to the end user. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 474 7-bit address scheme and the lower seven bits in the 10-bit address scheme. This field is reserved. Reserved This read-only field is reserved and always has the value 0. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 475 C baud rate of 100 kbit/s. Hold times (μs) MULT SCL Start SCL Stop 3.500 3.000 5.500 2.500 4.000 5.250 2.250 4.000 5.250 2.125 4.250 5.125 1.125 4.750 5.125 KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 476 Writing a one to this bit generates a repeated START condition provided it is the current master. This bit will always be read as zero. Attempting a repeat at the wrong time results in loss of arbitration. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 477 Indicates the status of the bus regardless of slave or master mode. This bit is set when a START signal is detected and cleared when a STOP signal is detected. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 478 No interrupt pending Interrupt pending Receive Acknowledge RXAK Acknowledge signal was received after the completion of one byte of data transmission on the bus No acknowledge signal detected KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 479 ADEXT HDRS SBRC RMEN AD[10:8] Write Reset I2Cx_C2 field descriptions Field Description General Call Address Enable GCAEN Enables general call address. Disabled Enabled Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 480 Description Stop Hold Enable SHEN Set this bit to hold off entry to stop mode when any data transmission or reception is occurring. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 481 No filter/bypass 01-1Fh Filter glitches up to width of n bus clock cycles, where n=1-31d KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 482 2. Slave address transmission 3. Data transfer 4. STOP signal The STOP signal should not be confused with the CPU STOP instruction. The following figure illustrates I2C bus system communication. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 483 Only the slave with a calling address that matches the one transmitted by the master responds by sending an acknowledge bit. The slave sends the acknowledge bit by pulling SDA low at the ninth clock. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 484 A STOP signal is defined as a low-to-high transition of SDA while SCL is asserted. The master can generate a STOP signal even if the slave has generated an acknowledgement, at which point the slave must release the bus. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 485 Afterward there is no difference between the device clocks and the state of SCL, and all devices start counting their high periods. The first device to complete its high period pulls SCL low again. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 486 These potentially varying SCL divider values are highlighted in the following table. For the actual SCL divider values for your device, see the chip-specific details about the I2C module. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 487 (hex) value value (clocks) value value 1024 1152 1280 1536 1920 1280 1536 1792 2048 1022 1025 2304 1150 1153 2560 1278 1281 3072 1534 1537 3840 1918 1921 KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 488 A3. The slave-transmitter remains addressed until it receives a STOP condition (P) or a repeated START condition (Sr) followed by a different slave address. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 489 When the I2C module responds to one of these addresses, it acts as a slave-receiver and the IAAS bit is set after the address cycle. Software must read the Data register after the first byte transfer to determine that the address is matched. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 490 When the stop status is detected on the I C bus, the STOPF bit is set to 1. The CPU is interrupted, provided the IICIE and STOPIE bits are both set to 1. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 491 I2C module. The programmer must specify the size of the glitch (in terms of bus clock cycles) for the filter to absorb and not pass. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 492 (set FLT[SHEN] to 1). 30.5 Initialization/application information Module Initialization (Slave) 1. Write: Control Register 2 • to enable or disable general call • to select 10-bit or 7-bit addressing mode KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 493 The routine shown in the following figure encompasses both master and slave I2C operations. For slave operation, an incoming I2C message that contains the proper address begins I2C communication. For master operation, communication must be initiated by writing the Data register. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 494 2. When 10-bit addressing addresses a slave, the slave sees an interrupt following the first byte of the extended address. Ensure that for this interrupt, the contents of the Data register are ignored and not treated as a valid data transfer. Figure 30-29. Typical I2C interrupt routine KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 495 • Programmable 1-bit or 2-bit stop bits • Receiver wakeup by idle-line, address-mark or address match • Optional 13-bit break character generation / 11-bit break character detection • Selectable transmitter output and receiver input polarity KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 496 31.1.2.3 Debug mode The UART remains functional in debug mode. 31.1.3 Block diagram The following figure shows the transmitter portion of the UART. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 497 Transmit Control Pin Logic TxD Direction TXDIR BRK13 TDRE Tx Interrupt Request TCIE Figure 31-1. UART transmitter block diagram The following figure shows the receiver portion of the UART. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 498 31.2.7/507 4006_A007 UART Data Register (UART0_D) 31.2.8/508 4006_A008 UART Match Address Registers 1 (UART0_MA1) 31.2.9/509 4006_A009 UART Match Address Registers 2 (UART0_MA2) 31.2.10/510 Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 499 The 13 bits in SBR[12:0] are referred to collectively as BR, and they set the modulo divide rate for the baud rate generator. When BR is 1 - 8191, the baud rate equals baud clock / ((OSR+1) × BR). KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 500 Selects between loop back modes and normal 2-pin full-duplex modes. When LOOPS is set, the transmitter output is internally connected to the receiver input. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 501 1s in the data character, including the parity bit, is odd. Even parity means the total number of 1s in the data character, including the parity bit, is even. Even parity. Odd parity. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 502 When the UART receiver is off or LOOPS is set, the UART_RX pin is not used by the UART . When RE is written to 0, the receiver finishes receiving the current character (if any). Receiver disabled. Receiver enabled. Receiver Wakeup Control Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 503 • Queue a break character by writing 1 to UART_C2[SBK] Transmitter active (sending data, a preamble, or a break). Transmitter idle (transmission activity complete). Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 504 PF is set at the same time as RDRF when parity is enabled (PE = 1) and the parity bit in the received character does not agree with the expected parity value. To clear PF, write a logic one to the PF. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 505 This bit should only be changed when the transmitter and receiver are both disabled. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 506 RAF is set when the UART receiver detects the beginning of a valid start bit, and RAF is cleared automatically when the receiver detects an idle line. UART receiver idle waiting for a start bit. UART receiver active ( UART_RXD input not idle). KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 507 Transmit data not inverted. Transmit data inverted. Overrun Interrupt Enable ORIE This bit enables the overrun flag (OR) to generate hardware interrupt requests. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 508 Read receive data buffer 6 or write transmit data buffer 6. R6T6 Read receive data buffer 5 or write transmit data buffer 5. R5T5 Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 509 Software should only write a MA register when the associated C4[MAEN] bit is clear. Address: 4006_A000h base + 8h offset = 4006_A008h Read Write Reset UARTx_MA1 field descriptions Field Description Match Address KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 510 MA2 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. Table continues on the next page... KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 511 This bit should only be changed when the receiver is disabled. Resynchronization during received data word is supported Resynchronization during received data word is disabled KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 512 • Synchronization with the asynchronous UART baud clock can cause phase shift. 31.3.2 Transmitter functional description This section describes the overall block diagram for the UART transmitter, as well as specialized functions for sending break and idle characters. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 513 When idle-line wakeup is used, a full character time of idle (logic 1) is needed between messages to wake up any sleeping receivers. Normally, a program would wait for UART_S1[TDRE] to become set to indicate the last character of a message has moved to KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 514 (UART_S1[RDRF]) status flag is set. If UART_S1[RDRF] was already set indicating the receive data register (buffer) was already full, the overrun (OR) KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 515 This improves the reliability of the receiver in the presence of noise or mismatched baud rates. It does not improve worst case analysis because some characters do not have any extra falling edges anywhere in the character frame. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 516 When UART_C1[ILT] is set, the idle bit counter does not start until after the stop bit time, so the idle detection is not affected by the data in the last character of the previous message. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 517 • If UART_C4[MAEN1] and UART_C4[MAEN2] are asserted, a marked address is compared with both match registers and data is transferred only on a match with either register. 31.3.4 Additional UART functions The following sections describe additional UART functions. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 518 (UART_C1[RSRC] = 0) or single-wire mode (UART_C1[RSRC] = 1). Single-wire mode implements a half-duplex serial connection. The receiver is internally connected to the transmitter output and to the UART_TX pin (the UART_RX pin is not used). KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 519 UART_RX line remains idle for an extended period of time. IDLE is cleared by writing 1 to the UART_S1[IDLE] flag. After UART_S1[IDLE] has been cleared, it cannot become set again until the receiver has received at least one new character and has set UART_S1[RDRF]. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 520 At any time, an active edge on the UART_RX serial data input pin causes the UART_S2[RXEDGIF] flag to set. The UART_S2[RXEDGIF] flag is cleared by writing a 1 to it. This function depends on the receiver being enabled (UART_C2[RE] = 1). KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 521 • Pin output data register with corresponding set/clear/toggle registers • Pin data direction register • Zero wait state access to GPIO registers through IOPORT NOTE GPIO module is clocked by system clock. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 522 Deassertion: When output, this signal occurs on the rising-edge of the system KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 523 0) 400F_F04C Port Toggle Output Register (GPIOB_PTOR) (always 0000_0000h 32.2.4/525 reads 0) 400F_F050 Port Data Input Register (GPIOB_PDIR) 0000_0000h 32.2.5/526 400F_F054 Port Data Direction Register (GPIOB_PDDR) 0000_0000h 32.2.6/526 KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 524 Writing to this register will update the contents of the corresponding bit in the PDOR as follows: Corresponding bit in PDORn does not change. Corresponding bit in PDORn is set to logic 1. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 525 Writing to this register will update the contents of the corresponding bit in the PDOR as follows: Corresponding bit in PDORn does not change. Corresponding bit in PDORn is set to the inverse of its existing logic state. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 526 Port Data Direction Configures individual port pins for input or output. Pin is configured as general-purpose input, for the GPIO function. Pin is configured as general-purpose output, for the GPIO function. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 527 0) F800_004C Port Toggle Output Register (FGPIOB_PTOR) (always 0000_0000h 32.3.4/529 reads 0) F800_0050 Port Data Input Register (FGPIOB_PDIR) 0000_0000h 32.3.5/530 F800_0054 Port Data Direction Register (FGPIOB_PDDR) 0000_0000h 32.3.6/530 KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 528 Writing to this register will update the contents of the corresponding bit in the PDOR as follows: Corresponding bit in PDORn does not change. Corresponding bit in PDORn is set to logic 1. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 529 Writing to this register will update the contents of the corresponding bit in the PDOR as follows: Corresponding bit in PDORn does not change. Corresponding bit in PDORn is set to the inverse of its existing logic state. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 530 Configures individual port pins for input or output. Pin is configured as general-purpose input, for the GPIO function. Pin is configured as general-purpose output, for the GPIO function. 32.4 Functional description KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 531 Since the clocks to the Port Control and Interrupt modules are disabled during Compute Operation, the Pin Data Input Registers do not update with the current state of the pins. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 532 Functional description KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 533 Table A-2. Changes between revisions 2 and 1 Chapter Description Throughout the whole • Removed the DMA involved registers and information, KL02 does not support DMA. reference manual • Updated pinout of C4 and D4. KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 534 KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013 Freescale Semiconductor, Inc.
Page 535 Freescale, the Freescale logo, Energy Efficient Solutions logo, and Kinetis are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. All other product or service names are the property of their respective owners. ARM and Cortex-M0+ are the registered trademarks of ARM Limited.

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Freescale Semiconductor KL02 Series Reference Manual

Chapter 1 About this Document

Chapter 2 Introduction

Chapter 3 Chip Configuration

Chapter 4 Memory Map

Chapter 5 Clock Distribution

Chapter 6 Reset and Boot

Chapter 7 Power Management

Chapter 8 Security

Chapter 9 Debug

Chapter 10 Signal Multiplexing and Signal Descriptions

Chapter 11 Port Control and Interrupts (PORT)

Chapter 13 System Mode Controller (SMC)

Chapter 14 Power Management Controller (PMC)

Chapter 15 Reset Control Module (RCM)

Chapter 16 Bit Manipulation Engine (BME)

Chapter 17 Miscellaneous Control Module (MCM)

Chapter 18 Micro Trace Buffer (MTB)

Chapter 19 Crossbar Switch Lite (AXBS-Lite)

Chapter 20 Peripheral Bridge (AIPS-Lite)

Chapter 21 Multipurpose Clock Generator (MCG)

Chapter 22 Oscillator (OSC)

Chapter 23 Flash Memory Controller (FMC)

Chapter 24 Flash Memory Module (FTFA)

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Summary of Contents for Freescale Semiconductor KL02 Series