Freescale Semiconductor K02F Reference Manual

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K02F Sub-Family Reference Manual

Supports: MK02FN128VLH10, MK02FN128VLF10,

MK02FN128VFM10, MK02FN64VLH10, MK02FN64VLF10,

MK02FN64VFM10

Document Number: K02P64M100SFARM

Rev. 1, 7/2014

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Summary of Contents for Freescale Semiconductor K02F

Page 1 K02F Sub-Family Reference Manual Supports: MK02FN128VLH10, MK02FN128VLF10, MK02FN128VFM10, MK02FN64VLH10, MK02FN64VLF10, MK02FN64VFM10 Document Number: K02P64M100SFARM Rev. 1, 7/2014...
Page 2 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 3: Table Of Contents
Memories and Memory Interfaces.......................43 2.2.4 Clocks................................44 2.2.5 Security and Integrity modules........................44 2.2.6 Analog modules............................44 2.2.7 Timer modules.............................45 2.2.8 Communication interfaces...........................46 2.2.9 Human-machine interfaces..........................46 Orderable part numbers..............................47 Chapter 3 Chip Configuration Introduction...................................49 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 4 Watchdog Configuration..........................71 Clock modules................................72 3.4.1 MCG Configuration.............................72 3.4.2 OSC Configuration............................74 Memories and memory interfaces..........................74 3.5.1 Flash Memory Configuration........................74 3.5.2 Flash Memory Controller Configuration.....................77 3.5.3 SRAM Configuration...........................78 Security..................................79 3.6.1 CRC Configuration............................79 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 5 SRAM memory map..............................115 Peripheral bridge (AIPS-Lite) memory map.........................115 4.5.1 Read-after-write sequence and required serialization of memory operations..........116 4.5.2 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map..................116 Private Peripheral Bus (PPB) memory map........................120 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 6 LPTMR clocking............................130 5.7.7 CLKOUT32K clocking..........................131 5.7.8 UART clocking............................131 Chapter 6 Reset and Boot Introduction...................................133 Reset....................................133 6.2.1 Power-on reset (POR)..........................134 6.2.2 System reset sources............................134 6.2.3 MCU Resets..............................137 6.2.4 Reset Pin ..............................139 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 7 Power modes shutdown sequencing..........................153 Flash Program Restrictions............................154 Module Operation in Low Power Modes........................154 Chapter 8 Security Introduction...................................159 Flash Security................................159 Security Interactions with other Modules........................160 8.3.1 Security Interactions with Debug.........................160 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 8 Debug & Security.................................174 Chapter 10 Signal Multiplexing and Signal Descriptions 10.1 Introduction...................................175 10.2 Signal Multiplexing Integration............................175 10.2.1 Port control and interrupt module features....................176 10.2.2 Clock gating..............................177 10.2.3 Signal multiplexing constraints........................177 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 9 Interrupt Status Flag Register (PORTx_ISFR)....................202 11.5.5 Digital Filter Enable Register (PORTx_DFER)...................202 11.5.6 Digital Filter Clock Register (PORTx_DFCR)....................203 11.5.7 Digital Filter Width Register (PORTx_DFWR)..................203 11.6 Functional description..............................204 11.6.1 Pin control..............................204 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 10 Flash Configuration Register 2 (SIM_FCFG2)...................235 12.2.16 Unique Identification Register High (SIM_UIDH)..................235 12.2.17 Unique Identification Register Mid-High (SIM_UIDMH)................236 12.2.18 Unique Identification Register Mid Low (SIM_UIDML)................236 12.2.19 Unique Identification Register Low (SIM_UIDL)..................237 12.3 Functional description..............................237 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 11 14.2.2 System Reset Status Register 1 (RCM_SRS1)....................281 14.2.3 Reset Pin Filter Control register (RCM_RPFC)..................283 14.2.4 Reset Pin Filter Width register (RCM_RPFW)...................284 14.2.5 Sticky System Reset Status Register 0 (RCM_SSRS0)................285 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 12 16.4 I/O retention..................................313 16.5 Memory map and register descriptions.........................313 16.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)............314 16.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)............315 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 13 17.4.1 LLS mode..............................337 17.4.2 VLLS modes..............................337 17.4.3 Initialization..............................337 Chapter 18 Miscellaneous Control Module (MCM) 18.1 Introduction...................................339 18.1.1 Features................................339 18.2 Memory map/register descriptions..........................339 18.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)..............340 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 14 General operation............................353 20.2 Functional description..............................354 20.2.1 Access support.............................354 Chapter 21 Direct Memory Access Multiplexer (DMAMUX) 21.1 Introduction...................................355 21.1.1 Overview..............................355 21.1.2 Features................................356 21.1.3 Modes of operation............................356 21.2 External signal description............................357 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 15 Enable Error Interrupt Register (DMA_EEI)....................383 22.3.5 Clear Enable Error Interrupt Register (DMA_CEEI)..................384 22.3.6 Set Enable Error Interrupt Register (DMA_SEEI)..................385 22.3.7 Clear Enable Request Register (DMA_CERQ)...................386 22.3.8 Set Enable Request Register (DMA_SERQ)....................387 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 16 TCD Control and Status (DMA_TCDn_CSR)....................407 22.3.31 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCDn_BITER_ELINKYES)......................410 22.3.32 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCDn_BITER_ELINKNO)......................411 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 17 Service Register (EWM_SERV)........................441 23.3.3 Compare Low Register (EWM_CMPL)......................441 23.3.4 Compare High Register (EWM_CMPH).....................442 23.3.5 Clock Prescaler Register (EWM_CLKPRESCALER)................443 23.4 Functional Description..............................443 23.4.1 The EWM_out Signal..........................443 23.4.2 The EWM_in Signal............................444 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 18 Watchdog Time-out Value Register High (WDOG_TOVALH)..............459 24.7.4 Watchdog Time-out Value Register Low (WDOG_TOVALL)..............460 24.7.5 Watchdog Window Register High (WDOG_WINH)..................460 24.7.6 Watchdog Window Register Low (WDOG_WINL)...................461 24.7.7 Watchdog Refresh register (WDOG_REFRESH)..................461 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 19 MCG Auto Trim Compare Value High Register (MCG_ATCVH)............478 25.3.9 MCG Auto Trim Compare Value Low Register (MCG_ATCVL)..............478 25.3.10 MCG Control 7 Register (MCG_C7)......................479 25.3.11 MCG Control 8 Register (MCG_C8)......................479 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 20 OSC Memory Map/Register Definition.......................501 26.8 Functional Description..............................503 26.8.1 OSC module states............................503 26.8.2 OSC module modes.............................505 26.8.3 Counter.................................507 26.8.4 Reference clock pin requirements........................507 26.9 Reset....................................507 26.10 Low power modes operation............................508 26.11 Interrupts..................................508 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 21 Cache Data Storage (upper word) (FMC_DATAW3SnU)................530 27.4.15 Cache Data Storage (lower word) (FMC_DATAW3SnL)................531 27.5 Functional description..............................531 27.5.1 Default configuration...........................531 27.5.2 Configuration options..........................532 27.5.3 Speculative reads............................532 27.6 Initialization and application information........................533 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 22 Flash Program and Erase..........................558 28.4.9 Flash Command Operations.........................558 28.4.10 Margin Read Commands..........................562 28.4.11 Flash Command Description........................563 28.4.12 Security................................577 28.4.13 Reset Sequence............................579 Chapter 29 Cyclic Redundancy Check (CRC) 29.1 Introduction...................................581 29.1.1 Features................................581 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 23 ADC Configuration Register 1 (ADCx_CFG1)...................599 30.3.3 ADC Configuration Register 2 (ADCx_CFG2)...................601 30.3.4 ADC Data Result Register (ADCx_Rn).......................602 30.3.5 Compare Value Registers (ADCx_CVn).....................603 30.3.6 Status and Control Register 2 (ADCx_SC2)....................604 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 24 Voltage reference selection..........................618 30.4.3 Hardware trigger and channel selects......................618 30.4.4 Conversion control............................619 30.4.5 Automatic compare function........................627 30.4.6 Calibration function.............................628 30.4.7 User-defined offset function........................630 30.4.8 Temperature sensor............................631 30.4.9 MCU wait mode operation...........................632 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 25 DAC Control Register (CMPx_DACCR)....................652 31.2.6 MUX Control Register (CMPx_MUXCR)....................653 31.3 Functional description..............................654 31.3.1 CMP functional modes..........................654 31.3.2 Power modes..............................663 31.3.3 Startup and operation...........................664 31.3.4 Low-pass filter.............................665 31.4 CMP interrupts................................667 31.5 DMA support................................667 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 26 DAC Control Register 2 (DACx_C2)......................678 32.5 Functional description..............................678 32.5.1 DAC data buffer operation...........................678 32.5.2 DMA operation............................680 32.5.3 Resets................................680 32.5.4 Low-Power mode operation.........................680 Chapter 33 Voltage Reference (VREFV1) 33.1 Introduction...................................683 33.1.1 Overview..............................684 33.1.2 Features................................684 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 27 Interrupt Delay register (PDBx_IDLY).......................702 34.3.5 Channel n Control register 1 (PDBx_CHnC1).....................703 34.3.6 Channel n Status register (PDBx_CHnS).....................704 34.3.7 Channel n Delay 0 register (PDBx_CHnDLY0)..................704 34.3.8 Channel n Delay 1 register (PDBx_CHnDLY1)..................705 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 28 35.3.1 Memory map..............................718 35.3.2 Register descriptions............................719 35.3.3 Status And Control (FTMx_SC)........................724 35.3.4 Counter (FTMx_CNT)..........................725 35.3.5 Modulo (FTMx_MOD)..........................726 35.3.6 Channel (n) Status And Control (FTMx_CnSC)..................727 35.3.7 Channel (n) Value (FTMx_CnV).........................730 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 29 FTM PWM Load (FTMx_PWMLOAD).....................766 35.4 Functional description..............................767 35.4.1 Clock source..............................768 35.4.2 Prescaler...............................769 35.4.3 Counter.................................769 35.4.4 Input Capture mode............................775 35.4.5 Output Compare mode..........................778 35.4.6 Edge-Aligned PWM (EPWM) mode......................779 35.4.7 Center-Aligned PWM (CPWM) mode......................781 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 30 BDM mode..............................838 35.4.27 Intermediate load............................839 35.4.28 Global time base (GTB)..........................841 35.5 Reset overview................................843 35.6 FTM Interrupts................................844 35.6.1 Timer Overflow Interrupt..........................845 35.6.2 Channel (n) Interrupt............................845 35.6.3 Fault Interrupt..............................845 35.7 Initialization Procedure..............................845 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 31 Detailed signal descriptions.........................860 37.3 Memory map and register definition..........................860 37.3.1 Low Power Timer Control Status Register (LPTMRx_CSR)..............861 37.3.2 Low Power Timer Prescale Register (LPTMRx_PSR)................862 37.3.3 Low Power Timer Compare Register (LPTMRx_CMR)................864 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 32 Module Configuration Register (SPIx_MCR).....................878 38.3.2 Transfer Count Register (SPIx_TCR)......................881 38.3.3 Clock and Transfer Attributes Register (In Master Mode) (SPIx_CTARn)..........881 38.3.4 Clock and Transfer Attributes Register (In Slave Mode) (SPIx_CTARn_SLAVE)........886 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 33 38.5.4 Baud rate settings............................918 38.5.5 Delay settings...............................918 38.5.6 Calculation of FIFO pointer addresses......................919 Chapter 39 Inter-Integrated Circuit (I2C) 39.1 Introduction...................................923 39.1.1 Features................................923 39.1.2 Modes of operation............................924 39.1.3 Block diagram..............................924 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 34 39.4.5 Resets................................948 39.4.6 Interrupts..............................948 39.4.7 Programmable input glitch filter........................951 39.4.8 Address matching wake-up..........................951 39.4.9 DMA support...............................952 39.5 Initialization/application information...........................953 Chapter 40 Universal Asynchronous Receiver/Transmitter (UART) 40.1 Introduction...................................957 40.1.1 Features................................957 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 35 UART FIFO Status Register (UARTx_SFIFO)...................982 40.3.19 UART FIFO Transmit Watermark (UARTx_TWFIFO)................983 40.3.20 UART FIFO Transmit Count (UARTx_TCFIFO)..................984 40.3.21 UART FIFO Receive Watermark (UARTx_RWFIFO)................984 40.3.22 UART FIFO Receive Count (UARTx_RCFIFO)..................985 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 36 Modes of operation............................1017 41.1.3 GPIO signal descriptions..........................1018 41.2 Memory map and register definition..........................1019 41.2.1 Port Data Output Register (GPIOx_PDOR)....................1021 41.2.2 Port Set Output Register (GPIOx_PSOR)....................1022 41.2.3 Port Clear Output Register (GPIOx_PCOR)....................1022 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 37 42.4 Functional description..............................1033 42.4.1 JTAGC reset configuration..........................1033 42.4.2 IEEE 1149.1-2001 (JTAG) Test Access Port....................1033 42.4.3 TAP controller state machine........................1033 42.4.4 JTAGC block instructions..........................1035 42.4.5 Boundary scan..............................1038 42.5 Initialization/Application information..........................1038 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 38 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 39: Chapter 1 About This Document
Hexadecimal number. For example, the hexadecimal equivalent of the number 60 is written 3Ch. In some cases, hexadecimal numbers are shown with the prefix 0x. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 40: Typographic Notation
Write 1 to clear: Refers to a register bitfield that must be written as 1 to be "cleared." K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 41: Chapter 2 Introduction
• Multiple clock generation options available from internally- and externally- generated clocks • System oscillator to provide clock source for the MCU Security • Cyclic Redundancy Check module for error detection Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 42: Arm® Cortex®-M4 Core Modules
After clock restart, the NVIC observes the pending interrupt and performs the normal interrupt or event processing. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 43: System Modules
The WDOG monitors internal system operation and forces a reset in case of failure. It can run from an independent 1 KHz low power oscillator with a programmable refresh window to detect deviations in program flow or system frequency. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 44: Memories And Memory Interfaces
Hardware CRC generator circuit using 16/32-bit shift register. Error detection for all single, double, odd, and most multi-bit errors, programmable initial seed value, and optional feature to transpose input data and CRC result via transpose register. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 45: Analog Modules
• Continuous-pulse output or single-shot mode supported, each output is independently enabled, with possible trigger events • Supports bypass mode • Supports DMA Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 46: Communication Interfaces
Universal asynchronous receiver/ Asynchronous serial bus communication interface with programmable 8- or 9-bit transmitters (UART) data format 2.2.9 Human-machine interfaces The following human-machine interfaces (HMI) are available on this device: K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 47: Orderable Part Numbers
100 MHz LQFP 64 KB 16 KB MK02FN64VLF10 100 MHz LQFP 64 KB 16 KB MK02FN64VFM10 100 MHz 64 KB 16 KB 1. This part number is subject to removal. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 48 Orderable part numbers K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 49: Chapter 3 Chip Configuration
3.2.1 ARM Cortex-M4 Core Configuration This section summarizes how the module has been configured in the chip. Full documentation for this module is provided by ARM and can be found at arm.com. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 50: Buses, Interconnects, And Interfaces
Data code (DCODE) bus System bus The system bus is connected to a separate master port on the crossbar. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 51: Debug Facilities
3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration This section summarizes how the module has been configured in the chip. Full documentation for this module is provided by ARM and can be found at arm.com. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 52: Interrupt Priority Levels
The pin the NMI signal is multiplexed on, must be configured for the NMI function to generate the non-maskable interrupt request. 3.2.2.3 Interrupt channel assignments The interrupt source assignments are defined in the following table. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 53 – – 0x0000_0054 – – 0x0000_0058 – – 0x0000_005C – – 0x0000_0060 – – 0x0000_0064 – – 0x0000_0068 – – 0x0000_006C – – Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 54 UART1 Single interrupt vector for UART error sources 0x0000_00CC — — 0x0000_00D0 — — 0x0000_00D4 — — 0x0000_00D8 — — 0x0000_00DC ADC0 — Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 55 2. Indicates the NVIC's ISER, ICER, ISPR, ICPR, and IABR register number used for this IRQ. The equation to calculate this value is: IRQ div 32 3. Indicates the NVIC's IPR register number used for this IRQ. The equation to calculate this value is: IRQ div 4 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 56: Determining The Bitfield And Register Location For Configuring A Particular Interrupt
NVICIPR14 bitfield range is 20-23 Therefore, the following bitfield locations are used to configure the LPTMR interrupts: • NVICISER1[26] • NVICICER1[26] • NVICISPR1[26] • NVICICPR1[26] • NVICIABR1[26] • NVICIPR14[23:20] K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 57: Asynchronous Wake-Up Interrupt Controller (Awic) Configuration
Port Control Module - Any enabled pin interrupt is capable of waking the system ADCx The ADC is functional when using internal clock source Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 58: Fpu Configuration
3.2.5 JTAG Controller Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 59: System Modules
Figure 3-6. SIM configuration Table 3-10. Reference links to related information Topic Related module Reference Full description System memory map System memory map Clocking Clock distribution Power management Power management K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 60: System Mode Controller (Smc) Configuration
Table 3-12. Reference links to related information Topic Related module Reference Full description System memory map System memory map Power management Power management Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 61: Low-Leakage Wake-Up Unit (Llwu) Configuration
The device uses the following internal peripheral and external pin inputs as wakeup sources to the LLWU module. LLWU_Px are external pin inputs, and LLWU_M0IF- M7IF are connections to the internal peripheral interrupt flags. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 62: Mcm Configuration
After wakeup, the flags are cleared based on the peripheral clearing mechanism. 3.3.5 MCM Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 63: Crossbar-Light Switch Configuration
3.3.6 Crossbar-Light Switch Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 64: Crossbar-Light Switch Master Assignments
Crossbar switch slave Peripheral bridges Peripheral bridge Crossbar switch slave GPIO controller GPIO controller 3.3.6.1 Crossbar-Light Switch Master Assignments The masters connected to the crossbar switch are assigned as follows: K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 65: Crossbar-Light Switch Slave Assignments
Peripheral bridge (AIPS-Lite) (AIPS-Lite) System memory map System memory map Clocking Clock Distribution Crossbar switch Crossbar switch Crossbar switch 3.3.7.1 Number of peripheral bridges This device contains one peripheral bridge. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 66: Memory Maps
DMA request sources and a specific DMA channel. Some of the modules support Asynchronous DMA operation as indicated by the last column in the following DMA source assignment table. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 67 FTM1 Channel 1 FTM2 Channel 0 FTM2 Channel 1 Reserved — Reserved — Reserved — Reserved — Reserved — Reserved — Reserved — Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 68: Dma Transfers Via Pit Trigger
3.3.9 DMA Controller Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 69: External Watchdog Monitor (Ewm) Configuration
3.3.10 External Watchdog Monitor (EWM) Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 70: Ewm Clocks
This table shows the EWM low-power modes and the corresponding chip low-power modes. Table 3-23. EWM low-power modes Module mode Chip mode Wait Wait, VLPW Stop Stop, VLPS, LLS K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 71: Ewm_Out Pin State In Low Power Modes
This table shows the WDOG module clocks and the corresponding chip clocks. Table 3-25. WDOG clock connections Module clock Chip clock LPO Oscillator 1 kHz LPO Clock Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 72: Wdog Low-Power Modes
3.4 Clock modules 3.4.1 MCG Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 73: Mcg Oscillator Clock Input Options
Clock Distribution for more details on these clocks. NOTE The MCG chapter has many references to the RTC oscillator source. On this device that clock source is not available and K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 74: Osc Configuration
3.4.2.1 OSC modes of operation with MCG The MCG's C2 register bits configure the oscillator frequency range. See the OSC and MCG chapters for more details. 3.5 Memories and memory interfaces K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 75: Flash Memory Configuration
The amounts of flash memory for the devices covered in this document are: Device Program flash (KB) Block 0 address range MK02FN128VLH10 0x0000_0000–0x0001_FFFF Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 76 How flash security is implemented on this device is described in Chip Security. 3.5.1.5 Flash Program Restrictions The flash memory on this device should not be programmed or erased while operating in High Speed Run or VLPR power modes. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 77: Flash Modes
Figure 3-20. Flash memory controller configuration Table 3-31. Reference links to related information Topic Related module Reference Full description Flash memory Flash memory controller controller Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 78: Number Of Masters
Table 3-32. Reference links to related information Topic Related module Reference Full description SRAM SRAM System memory map System memory map Clocking Clock Distribution Transfers SRAM controller SRAM controller ARM Cortex-M4 core ARM Cortex-M4 core K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 79: Sram Sizes
The SRAM is retained down to LLS3 and VLLS3 mode. In LLS2 and VLLS2 the entire region of SRAM_U from 0x2000_0000 is powered. In VLLS1 and VLLS0 no SRAM is retained. 3.6 Security K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 80: Crc Configuration
3.7.1 16-bit SAR ADC Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 81: Adc Instantiation Information
CPU load, the ADC supports DMA request functionality for higher performance when the ADC is sampled at a very high rate or cases where PDB is bypassed. The ADC can trigger the DMA (via DMA req) on conversion completion. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 82: Adcx Connections/Channel Assignment
ADC0_DM1 10101 AD21 Reserved Reserved 10110 AD22 Reserved Reserved 10111 AD23 Reserved 12-bit DAC0 Output/ADC0_SE23 11000 AD24 Reserved Reserved 11001 AD25 Reserved Reserved Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 83: Adc Channels Mux Selection
3.7.1.5 ADC Reference Options The ADC supports the following references: • VREFH/VREFL - connected as the primary reference option • 1.2 V VREF_OUT - connected as the V reference option K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 84: Adc Triggers
1001 FTM1 trigger 1010 FTM2 trigger 1011 Reserved 1100 Reserved 1101 Reserved 1110 LPTMR trigger 1111 Reserved For operation of triggers in different modes, refer to Power Management chapter. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 85: Adc Conversion Clock Options
LLS, VLLS3, VLLS2, VLLS1, VLLS0 3.7.2 CMP Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 86: Cmp Input Connections
Bandgap 6b DAC0 Reference 6b DAC1 Reference 3.7.2.2 CMP external references The 6-bit DAC sub-block supports selection of two references. For this device, the references are connected as follows: K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 87: External Window/Sample Input
3.7.3 12-bit DAC Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 88: 12-Bit Dac Overview
DACREF_2 input. Use DACx_C0[DACRFS] control bit to select between these two options. Be aware that if the DAC and ADC use the VREF_OUT reference simultaneously, some degradation of ADC accuracy is to be expected due to DAC switching. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 89: Vref Configuration
PMC_REGSC[BGEN] bit must be set if the VREF regulator is required to remain operating in VLPx modes. NOTE For either an internal or external reference if the VREF_OUT functionality is being used, VREF_OUT signal must be K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 90: Timers
3.8.1.1 PDB Instantiation 3.8.1.1.1 PDB Output Triggers Table 3-44. PDB output triggers Number of PDB channels for ADC trigger Number of pre-triggers per PDB channel Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 91: Pdb Module Interconnections
Channel 0 triggers ADC0 trigger Channel 1 triggers synchronous input 1 of FTM0 DAC triggers DAC0 trigger Pulse-out Pulse-out connected to each CMP module's sample/window input to control sample operation K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 92: Back-To-Back Acknowledgement Connections
• PDB interval trigger 0 connects to DAC0 hardware trigger input. 3.8.1.5 DAC External Trigger Input Connections In this MCU, the following DAC external trigger inputs are implemented. • DAC external trigger input 0: ADC0SC1A_COCO K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 93: Pulse-Out Connection
31:2 - Reserved 3.8.2 FlexTimer Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 94: Instantiation Information
Each module contains a register setting that allows the module to be clocked from an external clock instead. There are two external FTM_CLKINx pins that can be selected by any FTM module via the SIM_SOPT4 register. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 95: Fixed Frequency Clock
• FTM0 hardware trigger 2 = FTM0_FLT0 pin • FTM1 hardware trigger 0 = SIM_SOPT8[FTM1SYNCBIT] or CMP0 Output • FTM1 hardware trigger 1 = CMP1 Output • FTM1 hardware trigger 2 = FTM1_FLT0 pin K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 96: Input Capture Options For Ftm Module Instances
FTM2_CH1 input or the XOR of FTM2_CH0, FTM2_CH1 and FTM1_CH1 pins that will be applied to FTM2_CH1. Note: If the user utilizes FTM1_CH1 to be an input to FTM2_CH1, FTM1_CH0 can still be utilized for other functions. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 97: Ftm Modulation Implementation
Also it limits the use of the FTM1_CH0 function, as the FTM1_CH1 will be programmed to provide a 50% duty PWM signal and limit the start and modulus values for the free running counter. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 98: Ftm Output Triggers For Other Modules
Global time base (GTB)). FTM0 provides the only source for the FTM global time base. The other FTM modules can share the time base as shown in the following figure: K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 99: Ftm Bdm And Debug Halt Mode
Figure 3-34. PIT configuration Table 3-49. Reference links to related information Topic Related module Reference Full description System memory map System memory map Clocking Clock Distribution Power management Power management K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 100: Pit/Dma Periodic Trigger Assignments
Topic Related module Reference Full description Low-power timer Low-power timer System memory map System memory map Clocking Clock Distribution Power management Power management Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 101: Lptmr Prescaler/Glitch Filter Clocking Options
The LPTMR_CSR[TPS] bitfield configures the input source used in pulse counter mode. The following table shows the chip-specific input assignments for this bitfield. LPTMR_CSR[TPS] Pulse counter input number Chip input CMP0 output LPTMR_ALT1 pin LPTMR_ALT2 pin LPTMR_ALT3 pin K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 102: Communication Interfaces
The SPI module is clocked by the internal bus clock (the DSPI refers to it as system clock). The module has an internal divider, with a minimum divide is two. So, the SPI can run at a maximum frequency of bus clock/2. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 103: Tx Fifo Size
Table 3-55. SPI PCS signals SPI Module PCS Signals SPI0 For packages with 64 pins: SPI0_PCS[4:0] For packages with 48 pins: SPI0_PCS[4:0] For packages with 32 pins: SPI0_PCS[3:0] K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 104: Spi Interrupts
The SPI has multiple sources of interrupt requests. However, these sources are OR'd together to generate a single interrupt request to the interrupt controller. When an SPI interrupt occurs, read the SPI_SR to determine the exact interrupt source. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 105: Spi Clocks
3.9.2 I2C Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 106: I2C Instantiation Information
3.9.3 UART Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 107: Uart Configuration Information
5. UART1 implements 1-entry transmit and 1-entry receive FIFOs 3.9.3.2 UART wakeup The UART can be configured to generate an interrupt/wakeup on the first active edge that it receives. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 108: Uart Interrupts
3.10 Human-machine interfaces 3.10.1 GPIO configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 109: Number Of Gpio Signals
PTD7, PTC3, and PTC4. All other GPIO support normal drive option only. PTA4 includes a passive input filter that is enabled or disabled by PORTA_PCR4[PFE] control. This reset default is to have this function disabled. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 110 Human-machine interfaces K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 111: Chapter 4 Memory Map
32-bit word of the aliased address space to a unique bit in the underlying RAM or peripheral address space to support single-bit insert and extract operations from the processor. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 112 1. Access rights to AIPS-Lite peripheral bridge and general purpose input/output (GPIO) module address space is limited to the core, DMA . 2. ARM Cortex-M4 core access privileges also includes accesses via the debug interface. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 113: Aliased Bit-Band Regions
Figure 4-1. Alias bit-band mapping NOTE Each bit in bit-band region has an equivalent bit that can be manipulated through bit 0 in a corresponding long word in the alias bit-band region. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 114: Flash Access Control Introduction
The base address for each is specified in System memory map. Flash memory base address Registers Program flash base address Flash configuration field Program flash Figure 4-2. Flash memory map K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 115: Alternate Non-Volatile Irc User Trim Description
Accesses to the SRAM_L and SRAM_U memory ranges outside the amount of RAM on the device causes the bus cycle to be terminated with an error followed by the appropriate response in the requesting bus master. 4.5 Peripheral bridge (AIPS-Lite) memory map K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 116: Read-After-Write Sequence And Required Serialization Of Memory Operations
4.5.2 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map Table 4-2. Peripheral bridge 0 slot assignments System 32-bit base address Slot Module number 0x4000_0000 — 0x4000_1000 — 0x4000_2000 — Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 117 0x4002_0000 Flash memory 0x4002_1000 DMA channel mutiplexer 0x4002_2000 — 0x4002_3000 — 0x4002_4000 — 0x4002_5000 — 0x4002_6000 — 0x4002_7000 — 0x4002_8000 — 0x4002_9000 — Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 118 Port B multiplexing control 0x4004_B000 Port C multiplexing control 0x4004_C000 Port D multiplexing control 0x4004_D000 Port E multiplexing control 0x4004_E000 — 0x4004_F000 — 0x4005_0000 — Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 119 0x4007_1000 — 0x4007_2000 — 0x4007_3000 Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) 0x4007_4000 Voltage reference (VREF) 0x4007_5000 — 0x4007_6000 — 0x4007_7000 — Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 120: Private Peripheral Bus (Ppb) Memory Map
Trace Port Interface Unit (TPIU) 0xE004_1000–0xE004_1FFF Reserved 0xE004_2000–0xE004_2FFF Reserved 0xE004_3000–0xE004_3FFF Reserved 0xE004_4000–0xE007_FFFF Reserved 0xE008_0000–0xE008_0FFF Miscellaneous Control Module (MCM) 0xE008_1000–0xE008_1FFF Reserved 0xE008_2000–0xE00F_EFFF Reserved 0xE00F_F000–0xE00F_FFFF ROM Table - allows auto-detection of debug components K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 121: Chapter 5 Clock Distribution
SIM module. Reference those sections for detailed register and bit descriptions. 5.3 High-Level device clocking diagram The following system oscillator, MCG, and module registers control the multiplexers, dividers, and clock gates shown in the below figure: K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 122: Clock Definitions
The following table describes the clocks in the previous block diagram. Clock name Description Core clock MCGOUTCLK divided by OUTDIV1 clocks the ARM Cortex- M4 core Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 123: Device Clock Summary
Up to 100 MHz MCG clock controls do not enable. Overriding forced disable in all low powers modes (including STOP and VLPx modes). Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 124 1 kHz 1 kHz 1 kHz in VLLS0 TRACE clock Up to 100 MHz Up to 100 MHz Up to 4 MHz System clock or Trace is disabled MCGOUTCLK K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 125: Internal Clocking Requirements
36 MHz Flash clock 24 MHz Option 3: High Speed Run Clock Frequency Core clock 100 MHz System clock 100 MHz Bus clock 50 MHz Flash clock 25 MHz K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 126: Clock Divider Values After Reset
800 kHz or less. In this case, one example of correct configuration is MCG_SC[FCRDIV]=000b and SIM_CLKDIV1[OUTDIV4]=0100b, resulting in a divide by 5 setting. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 127: Clock Gating
Bus clock — Watchdog timer Bus clock — Clocks Flash clock MCGOUTCLK, MCGFLLCLK, — MCGIRCLK, OSCCLK, IRC48MCLK Bus clock OSCERCLK, OSCCLK, — OSCERCLK_UNDIV, OSC32KCLK Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 128: Pmc 1-Khz Lpo Clock
Compute Only, PSTOP2 and PSTOP1 modes of operation when entered from Run mode. IRC48MCLK is forced disabled when the MCU transitions into VLPS, LLSx, and VLLSx low power modes. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 129: Wdog Clocking
The WDOG may be clocked from two clock sources as shown in the following figure. WDOG clock Bus clock WDOG_STCTRLH[CLKSRC] Figure 5-2. WDOG clock generation 5.7.4 Debug trace clock The debug trace clock source can be clocked as shown in the following figure. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 130: Port Digital Filter Clocking
The prescaler and glitch filters in each of the LPTMRx modules can be clocked as shown in the following figure. NOTE The chosen clock must remain enabled if the LPTMRx is to continue operating in all required low-power modes. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 131: Clkout32K Clocking
Reserved Others Other modules Figure 5-6. CLKOUT32K generation 5.7.8 UART clocking UART0 and UART1 modules operate from the core/system clock, which provides higher performance level for these modules. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 132 Module clocks K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 133: Chapter 6 Reset And Boot
6.2 Reset This section discusses basic reset mechanisms and sources. Some modules that cause resets can be configured to cause interrupts instead. Consult the individual peripheral chapters for more information. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 134: Power-On Reset (Por)
• TDO with no pull-down or pull-up Note that the nTRST signal is initially configured as disabled, however once configured to its JTAG functionality its associated input pin is configured as: • nTRST in PU K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 135: External Pin Reset (Pin)
LVD system holds the MCU in reset until the supply voltage has risen above the low voltage detection threshold. The RCM's SRS0[LVD] bit is set following either an LVD reset or POR. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 136: Computer Operating Properly (Cop) Watchdog Timer
MCG module, the MCU resets. The RCM's SRS0[LOC] bit is set to indicate this reset source. NOTE To prevent unexpected loss of clock reset events, all clock monitors should be disabled before entering any low power modes, including VLPR and VLPW. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 137: Mcu Resets
Set the core hold reset bit in the MDM-AP control register to hold the core in reset as the rest of the chip comes out of system reset. 6.2.3 MCU Resets A variety of resets are generated by the MCU to reset different modules. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 138 The Early Chip Reset asserts on all reset sources. It resets only the flash memory module. It negates before flash memory initialization begins ("earlier" than when the Chip Reset negates). K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 139: Chip Reset
TAP controller state machine (after exiting LLS or VLLSx) without resetting the state of the debug modules. The nTRST pin does not cause a system reset. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 140: Resetting The Debug Subsystem
The device always exits reset in single chip functional mode with the CPU executing code. 1. CDBGRSTREQ does not affect AHB resources so that debug resources on the private peripheral bus are available during System Reset. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 141: Fopt Boot Options
NMI interrupts are always blocked. The associated pin continues to default to NMI pin controls with internal pullup enabled. NMI pin/interrupts reset default to enabled. Reserved Reserved for future expansion. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 142: Boot Sequence
Once the RESET pin is detected high, the Core clock is enabled and the system is released from reset. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 143 NMI interrupt. The processor executes an Exception Entry and reads the NMI interrupt handler address from vector-table offset 8. The CPU begins execution at the NMI interrupt handler. Subsequent system resets follow this same reset flow. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 144 Boot K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 145: Chapter 7 Power Management
If configured, a DMA request (using the asynchronous DMA wakeup) can also be used to exit Partial Stop for the duration of a DMA transfer before the device is transitioned back into PSTOP2. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 146: Dma Wakeup
Stop mode and then requesting bus slaves to enter Stop mode. In STOP and VLPS modes the MCG and PMC would then also enter their appropriate modes. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 147: Compute Operation
VLPS mode. The MCG, PMC, SRAM and Flash read port are not affected by Compute Operation, although the Flash register interface is disabled. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 148: Peripheral Doze
• The CPU is in Stop mode, including the entry sequence and for the duration of a DMA wakeup. • The CPU is in Compute Operation, including the entry sequence and for the duration of a DMA wakeup. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 149: Clock Gating
Stop mode entry is not supported directly from HSRUN and requires transition to Run prior to an attempt to enter a stop mode. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 150 LLS recovery. A portion of SRAM_U remains powered on (content retained and I/O states held). Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 151: Entering And Exiting Power Modes
RCM is set indicating that the chip is recovering from a low power mode. Code execution begins; however, the I/O pins are held in their pre low power mode entry K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 152: Power Mode Transitions
VLPR and VLPW are limited in frequency. The LLS and VLLSx mode(s) are the lowest power stop modes based on amount of logic or memory that is required to be retained by the application. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 153: Power Modes Shutdown Sequencing
• System level wait and VLPW modes equate to: SLEEPING & SLEEPDEEP • All other low power modes equate to: SLEEPING & SLEEPDEEP When entering the non-wait modes, the chip performs the following sequence: K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 154: Flash Program Restrictions
• static = Module register states and associated memories are retained. • powered = Memory is powered to retain contents. • low power = Memory is powered to retain contents in a lower power state K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 155 Core clock 4 MHz max Platform clock 4 MHz max 4 MHz max System clock 4 MHz max 4 MHz max OFF in CPO Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 156 FF in PSTOP2 static static static static in CPO FF in PSTOP2 LPTMR Async operation Async operation Async operation Async operation FF in PSTOP2 Analog Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 157 VLLSx only supports low speed external pin to pin or external pin to DAC compares. Windowed, sampled & filtered modes of operation are not available while in stop, VLPS, LLSx, or VLLSx modes. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 158 Module Operation in Low Power Modes K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 159: Chapter 8 Security
(FSEC[SEC] = 00, 01, or 11), programmer interfaces are only allowed to launch mass erase operations and have no access to memory locations. Further information regarding the flash security options and enabling/disabling flash security is available in the Flash Memory Module. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 160: Security Interactions With Other Modules
Blocks) command. A mass erase via the debugger is allowed even when some memory locations are protected. When mass erase is disabled, mass erase via the debugger is blocked. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 161: Introduction
• ARM Real-Time Trace Interface(1-pin asynchronous mode only) The basic Cortex-M4 debug architecture is very flexible. The following diagram shows the topology of the core debug architecture and its components. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 162 Singlestep, Register Access, Run, Core Status S/W Instrumentation Messaging + Simple Data Trace Messaging + Watchpoint Messaging DWT (Data and Address Watchpoints) 4 data and address watchpoints Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 163: References
Asynchronous Mode (1-pin) = TRACE_SWO (available on JTAG_TDO) 9.1.1 References For more information on ARM debug components, see these documents: • ARMv7-M Architecture Reference Manual • ARM Debug Interface v5.1 • ARM CoreSight Architecture Specification K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 164: The Debug Port
2. Send the 16-bit sequence on TMS (SWDIO) = 0111_1001_1110_0111 (MSB transmitted first) 3. Send more than 50 TCK cycles with TMS (SWDIO) =1 NOTE See the ARM documentation for the CoreSight DAP Lite for restrictions. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 165: Jtag-To-Cjtag Change Sequence
TAPs (TDO) are muxed based on the IR code which is selected. This design is fully JTAG compliant and appears to the JTAG chain as a single TAP. At power on reset, ARM's IDCODE (IR=4'b1110) is selected. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 166: Ir Codes
JTAG, cJTAG, or SWD. The MDM-AP is accessible as Debug Access Port 1 with the available registers shown in the table below. Table 9-4. MDM-AP Register Summary Address Register Description Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 167 SELECT[7:4] = 0xF selects the bank with IDR A[3:2] = 2’b11 selects the IDR Register See Control and Status Register (IDR register reads 0x001C_0000) Descriptions Figure 9-3. MDM AP Addressing K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 168: Mdm-Ap Control Register
This bit is used by the debugger to clear the sticky LLS and VLLSx mode entry status bits. This bit is asserted and cleared by the debugger. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 169: Mdm-Ap Status Register
1 Mass erase is enabled Backdoor Access Key Enable Indicates if the MCU has the backdoor access key enabled. 0 Disabled 1 Enabled Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 170: Debug Resets
9.6 Debug Resets The debug system receives the following sources of reset: • JTAG_TRST_b from an external signal. This signal is optional and may not be available in all packages. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 171: Ahb-Ap
The ITM is an application-driven trace source that supports printf style debugging to trace Operating System (OS) and application events, and emits diagnostic system information. The ITM emits trace information as packets. There are four sources that can K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 172: Core Trace Connectivity
DWT_COMP1, can also be used as a data comparator. • The DWT contains counters for: • Clock cycles (CYCCNT) • Folded instructions • Load store unit (LSU) operations • Sleep cycles K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 173: Debug In Low Power Modes
HW, the MDM-AP Control register can be configured hold the system in reset on recovery so that the debugger can regain control and reconfigure debug logic prior to the system exiting reset and resuming operation. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 174: Debug Module State In Low Power Modes
MDM-AP Control Register. In the case of a secure device that has mass erase disabled (FSEC[MEEN] = 10), attempts to mass erase via the debug interface are blocked. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 175: Chapter 10 Signal Multiplexing And Signal Descriptions
Table 10-1. Reference links to related information Topic Related module Reference Full description Port control Port control System memory map System memory map Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 176: Port Control And Interrupt Module Features
Drive strength PTB0/PTB1 only PTC3/PTC4 only PTD4/PTD5/PTD6/ enable control PTD7 only Drive strength Disabled Disabled Disabled Disabled Disabled enable at reset Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 177: Clock Gating
The Port Control Module is responsible for selecting which ALT functionality is available on each pin. NOTE The 48-pin LQFP package offering is subject to removal. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 178 PTA4/ FTM0_CH1 NMI_b LLWU_P3 LLWU_P3 — — PTA5 DISABLED PTA5 FTM0_CH2 JTAG_TRST_b — — PTA12 DISABLED PTA12 FTM1_CH0 FTM1_QD_ — — PTA13/ DISABLED PTA13/ FTM1_CH1 FTM1_QD_ LLWU_P4 LLWU_P4 — K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 179 — PTD1 ADC0_SE5b ADC0_SE5b PTD1 SPI0_SCK — PTD2/ DISABLED PTD2/ SPI0_SOUT I2C0_SCL LLWU_P13 LLWU_P13 — PTD3 DISABLED PTD3 SPI0_SIN I2C0_SDA PTD4/ DISABLED PTD4/ SPI0_PCS1 UART0_RTS_b FTM0_CH4 EWM_IN LLWU_P14 LLWU_P14 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 180: K02F Pinouts
The below figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 181 PTE17 PTC0 PTE18 PTB19 PTE19 PTB18 ADC0_DP0 PTB17 ADC0_DM0 PTB16 ADC0_DP3 PTB3 ADC0_DM3 PTB2 VDDA PTB1 VREFH PTB0/LLWU_P5 VREFL RESET_b VSSA PTA19 Figure 10-2. K02F 64 LQFP Pinout Diagram K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 182 ADC0_DP0 PTB3 ADC0_DM0 PTB2 VDDA PTB1 VREFH PTB0/LLWU_P5 VREFL RESET_b VSSA PTA19 Figure 10-3. K02F 48 LQFP Pinout Diagram NOTE The 48-pin LQFP package offering is subject to removal. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 183: Module Signal Description Tables
10.4 Module Signal Description Tables The following sections correlate the chip-level signal name with the signal name used in the module's chapter. They also briefly describe the signal function and direction. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 184: Core Modules
EWM input for safety status of external safety circuits. The polarity of EWM_in is programmable using the EWM_CTRL[ASSIN] bit. The default polarity is active-low. EWM_OUT EWM_out EWM reset out signal K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 185: Clock Modules
Module signal Description name CMP1_IN[5:0] IN[5:0] Analog voltage inputs CMP1_OUT CMPO Comparator output Table 10-11. DAC 0 Signal Descriptions Chip signal name Module signal Description name DAC0_OUT — DAC output K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 186: Timer Modules
Fault input (j), where j can be 3-0 FTM2_QD_PHA Quadrature decoder phase A input. Input pin associated with quadrature decoder phase A. FTM2_QD_PHB Quadrature decoder phase B input. Input pin associated with quadrature decoder phase B. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 187: Communication Interfaces
C system. Table 10-20. UART 0 Signal Descriptions Chip signal name Module signal Description name UART0_CTS Clear to send UART0_RTS Request to send UART0_TX Transmit data UART0_RX Receive data K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 188: Human-Machine Interfaces (Hmi)
PORTD31–PORTD0 General-purpose input/output PTE[31:0] PORTE31–PORTE0 General-purpose input/output 1. The available GPIO pins depends on the specific package. See the signal multiplexing section for which exact GPIO signals are available. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 189: Chapter 11 Port Control And Interrupts (Port)
• Support for interrupt or DMA request configured per pin • Asynchronous wake-up in low-power modes • Pin interrupt is functional in all digital pin muxing modes • Digital input filter on selected pins K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 190: Modes Of Operation
In Stop mode, the digital input filters are bypassed unless they are configured to run from the 1-kHz LPO clock source. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 191: Debug Mode
Any read or write access to the PORT memory space that is outside the valid memory map results in a bus error. All register accesses complete with zero wait states. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 192 11.5.2/200 reads 0) 4004_9084 Global Pin Control High Register (PORTA_GPCHR) (always 0000_0000h 11.5.3/201 reads 0) 4004_90A0 Interrupt Status Flag Register (PORTA_ISFR) 0000_0000h 11.5.4/202 Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 193 See section 11.5.1/198 4004_A07C Pin Control Register n (PORTB_PCR31) See section 11.5.1/198 4004_A080 Global Pin Control Low Register (PORTB_GPCLR) (always 0000_0000h 11.5.2/200 reads 0) Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 194 Pin Control Register n (PORTC_PCR28) See section 11.5.1/198 4004_B074 Pin Control Register n (PORTC_PCR29) See section 11.5.1/198 4004_B078 Pin Control Register n (PORTC_PCR30) See section 11.5.1/198 Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 195 4004_C064 Pin Control Register n (PORTD_PCR25) See section 11.5.1/198 4004_C068 Pin Control Register n (PORTD_PCR26) See section 11.5.1/198 4004_C06C Pin Control Register n (PORTD_PCR27) See section 11.5.1/198 Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 196 4004_D058 Pin Control Register n (PORTE_PCR22) See section 11.5.1/198 4004_D05C Pin Control Register n (PORTE_PCR23) See section 11.5.1/198 4004_D060 Pin Control Register n (PORTE_PCR24) See section 11.5.1/198 Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 197 4004_D0A0 Interrupt Status Flag Register (PORTE_ISFR) 0000_0000h 11.5.4/202 4004_D0C0 Digital Filter Enable Register (PORTE_DFER) 0000_0000h 11.5.5/202 4004_D0C4 Digital Filter Clock Register (PORTE_DFCR) 0000_0000h 11.5.6/203 4004_D0C8 Digital Filter Width Register (PORTE_DFWR) 0000_0000h 11.5.7/203 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 198: Pin Control Register N (Portx_Pcrn)
This read-only field is reserved and always has the value 0. Interrupt Status Flag The pin interrupt configuration is valid in all digital pin muxing modes. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 199 This read-only field is reserved and always has the value 0. Drive Strength Enable Drive strength configuration is valid in all digital pin muxing modes. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 200: Global Pin Control Low Register (Portx_Gpclr)
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 11.5.2 Global Pin Control Low Register (PORTx_GPCLR) Only 32-bit writes are supported to this register. Address: Base address + 80h offset GPWE GPWD Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 201: Global Pin Control High Register (Portx_Gpchr)
Corresponding Pin Control Register is updated with the value in GPWD. 15–0 Global Pin Write Data GPWD Write value that is written to all Pin Control Registers bits [15:0] that are selected by GPWE. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 202: Interrupt Status Flag Register (Portx_Isfr)
The digital filter configuration is valid in all digital pin muxing modes. Address: Base address + C0h offset Reset PORTx_DFER field descriptions Field Description 31–0 Digital Filter Enable K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 203: Digital Filter Clock Register (Portx_Dfcr)
11.5.7 Digital Filter Width Register (PORTx_DFWR) This register is read only for ports that do not support a digital filter. The digital filter configuration is valid in all digital pin muxing modes. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 204: Functional Description
Pin Control register. For example, if an I C function is enabled on a pin, that does not override the pullup or open drain configuration for that pin. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 205: Global Pin Control
The external interrupt capability of the PORT module is available in all digital pin muxing modes provided the PORT module is enabled. Each pin can be individually configured for any of the following external interrupt modes: K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 206: Digital Filter
K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 207 The minimum latency through a digital filter equals two or three filter clock cycles plus the filter width configuration register. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 208 Functional description K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 209: Chapter 12 System Integration Module (Sim)
• Architectural clock gating control • Flash and system RAM size configuration • FlexTimer external clock, hardware trigger, and fault source selection • UART0 and UART1 receive/transmit source selection/configuration K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 210: Memory Map And Register Definition
12.2.16/235 4004_8058 Unique Identification Register Mid-High (SIM_UIDMH) See section 12.2.17/236 4004_805C Unique Identification Register Mid Low (SIM_UIDML) See section 12.2.18/236 4004_8060 Unique Identification Register Low (SIM_UIDL) See section 12.2.19/237 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 211 ERCLK32K is output on PTE0. ERCLK32K is output on PTE26. Reserved. 15–12 RAM size RAMSIZE This field specifies the amount of system RAM available on the device. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 212 Reserved This read-only field is reserved and always has the value 0. 7–0 This field is reserved. Reserved This read-only field is reserved and always has the value 0. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 213 Selects the high frequency clock for various peripheral clocking options. NOTE: Not all chips have the option to select a PLL clock. MCGFLLCLK clock Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 214 Reserved This read-only field is reserved and always has the value 0. 3–0 This field is reserved. Reserved This read-only field is reserved and always has the value 0. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 215 FTM2 external clock driven by FTM_CLK1 pin. FTM1 External Clock Pin Select FTM1CLKSEL Selects the external pin used to drive the clock to the FTM1 module. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 216 NOTE: The pin source for fault 0 must be configured for the FTM module fault function through the appropriate PORTx pin control register. FTM2_FLT0 pin CMP0 out Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 217 FTM0_FLT0 pin CMP0 out 12.2.5 System Options Register 5 (SIM_SOPT5) Address: 4004_7000h base + 1010h offset = 4004_8010h Reset UART1RXSR UART1TXSR UART0RXSR UART0TXSR Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 218 UART0TXSRC Selects the source for the UART 0 transmit data. UART0_TX pin UART0_TX pin modulated with FTM1 channel 0 output UART0_TX pin modulated with FTM2 channel 0 output Reserved K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 219 Selects the ADC0 trigger source when alternative triggers are functional in stop and VLPS modes. . 0000 PDB external trigger pin input (PDB0_EXTRG) 0001 High speed comparator 0 output 0010 High speed comparator 1 output 0011 Reserved Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 220 FTM0_CH5 pin is output of FTM0 channel 5 output FTM0_CH5 pin is output of FTM0 channel 5 output, modulated by FTM1 channel 1 output Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 221 FTM0 Hardware Trigger 0 Software Synchronization FTM0SYNCBIT No effect Write 1 to assert the TRIG0 input to FTM0, software must clear this bit to allow other trigger sources to assert. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 222 This read-only field is reserved and always has the value 0. 15–12 Device revision number REVID Specifies the silicon implementation number for the device. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 223 Reserved 0100 48-pin 0101 64-pin 0110 80-pin 0111 81-pin or 121-pin 1000 100-pin 1001 121-pin 1010 144-pin 1011 Custom pinout (WLCSP) 1100 169-pin 1101 Reserved 1110 256-pin 1111 Reserved K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 224 This read-only field is reserved and always has the value 0. UART1 Clock Gate Control UART1 This bit controls the clock gate to the UART1 module. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 225 This bit controls the clock gate to the EWM module. Clock disabled Clock enabled This field is reserved. Reserved This read-only field is reserved and always has the value 0. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 226 This bit controls the clock gate to the Port C module. Clock disabled Clock enabled Port B Clock Gate Control PORTB This bit controls the clock gate to the Port B module. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 227 This bit controls software access to the Low Power Timer module. Access disabled Access enabled 12.2.11 System Clock Gating Control Register 6 (SIM_SCGC6) Address: 4004_7000h base + 103Ch offset = 4004_803Ch Reset SPI0 Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 228 This bit controls the clock gate to the PDB module. Clock disabled Clock enabled This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 229 DMA Mux Clock Gate Control DMAMUX This bit controls the clock gate to the DMA Mux module. Clock disabled Clock enabled Flash Memory Clock Gate Control Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 230 The maximum divide ratio that can be programmed between core/system clock and the other divided clocks is divide by 8. When OUTDIV1 equals 0000 (divide by 1), the other dividers cannot be set higher than 0111 (divide by 8). K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 231 0000 or 0111 depending on FTF_FOPT[LPBOOT]. The bus clock frequency must be an integer divide of the core/system clock frequency. 0000 Divide-by-1. 0001 Divide-by-2. 0010 Divide-by-3. 0011 Divide-by-4. 0100 Divide-by-5. 0101 Divide-by-6. 0110 Divide-by-7. 0111 Divide-by-8. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 232 1010 Divide-by-11. 1011 Divide-by-12. 1100 Divide-by-13. 1101 Divide-by-14. 1110 Divide-by-15. 1111 Divide-by-16. 15–0 This field is reserved. Reserved This read-only field is reserved and always has the value 0. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 233 32 KB of program flash memory 0101 64 KB of program flash memory 0111 128 KB of program flash memory 1001 256 KB of program flash memory Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 234 Flash accesses are disabled (and generate a bus error) and the Flash memory is placed in a low power state. This bit should not be changed during VLP modes. Relocate the interrupt vectors out of Flash memory before disabling the Flash. Flash is enabled Flash is disabled K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 235 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* Reset * Notes: • Reset value loaded during System Reset from Flash IFR. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 236 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* Reset * Notes: • Reset value loaded during System Reset from Flash IFR. SIM_UIDML field descriptions Field Description 31–0 Unique Identification Unique identification for the device. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 237: Functional Description
Reset value loaded during System Reset from Flash IFR. SIM_UIDL field descriptions Field Description 31–0 Unique Identification Unique identification for the device. 12.3 Functional description For more information about the functions of SIM, see the Introduction section. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 238 Functional description K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 239: Chapter 13 Kinetis Flashloader
The flashloader_loader program copies the contents of flashloader image from the flash to the on-chip RAM; the device then switches execution to the flashloader program to execute from RAM. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 240 Returns the contents of the IFR field or Flash firmware ID, by given offset, byte count and option WriteMemory Write data to memory ReadMemory Read data from memory Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 241: Functional Description
The following sub-sections describe the Kinetis Flashloader functionality. 13.3.1 Memory Maps While executing, the Kinetis Flashloader uses RAM memory. Available 0x2000_4000 Flashloader use 0x1FFF_4000 Figure 13-1. Kinetis Flashloader RAM Memory Map 13.3.2 Kinetis Flashloader K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 242: Start-Up Process
Property and Memory interfaces I2C1 entered Shutdown unused Enter flashloader Init UART1, interrupt state? Peripherals state machine SPI1, and I2C1 SPI1 entered interrupt state? Figure 13-2. Kinetis Flashloader Start-up Flowchart K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 243: Clock Configuration
The protocol for a command with no data phase contains: • Command packet (from host) • Generic response command packet (to host) Target Host Command Process command Response Figure 13-3. Command with No Data Phase K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 244: Command With Incoming Data Phase
• Generic response command packet (to host) Target Host Command Process command Initial Response Data packet Process data Final data packet Process data Final Response Figure 13-4. Command with incoming data phase K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 245: Command With Outgoing Data Phase
The protocol for a command with an outgoing data phase contains: • Command packet (from host) • ReadMemory Response command packet (to host) (kCommandFlag_HasDataPhase set) • Outgoing data packets (to host) • Generic response command packet (to host) K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 246 • If the ReadMemory Response command packet prior to the start of the data phase does not contain the kCommandFlag_HasDataPhase flag, then the data phase is aborted. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 247: Flashloader Packet Types
A Ping packet must be sent before any other communications. In response to a Ping packet, the target sends a Ping Response packet. Table 13-3. Ping Packet Format Byte # Value Name 0x5A start byte 0xA6 ping K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 248: Ping Response Packet
Ping response code Protocol bugfix Protocol minor Protocol major Protocol name = 'P' (0x50) Options low Options high CRC16 low CRC16 high The Serial Protocol Version number returned is 1.1.0. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 249: Framing Packet
^= byte << 8; for (i = 0; i < 8; ++i) uint32_t temp = crc << 1; if (crc & 0x8000) temp ^= 0x1021; crc = temp; K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 250: Command Packet
28 bytes for Parameters (Max 7 parameters) Flags Rsvd Param Param1 Param2 Param3 Param4 Param5 Param6 Param7 Count (32-bit) (32-bit) (32-bit) (32-bit) (32-bit) (32-bit) (32-bit) byte 0 byte 1 byte 2 byte 3 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 251 Kinetis Flashloader (target) returns to the 0xA7 GetPropertyResponse (used for sending host. The valid response tags are listed here. responses to GetProperty command only) 0xA3 ReadMemoryResponse (used for sending responses to ReadMemory command only) K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 252: Data Packet
(with generic response tag = 0xA0) and a list of parameters (defined in the next section). The parameter count field in the header is always set to 2, for status code and command tag parameters. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 253 Descripton 0 - 3 Status code The status of the associated Read Memory command. 4 - 7 Data byte count The number of bytes sent in the data phase. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 254: Flashloader Command Api
Flashloader, see Table 13-35. The 32-bit property tag is the only parameter required for GetProperty command. Table 13-16. Parameters for GetProperty Command Byte # Command 0 - 3 Property tag K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 255 0, followed by the property value(s). The next table shows an example of a GetPropertyResponse packet. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 256: Setproperty Command
The property tag and the new value to set are the 2 parameters required for the SetProperty command. Table 13-19. Parameters for SetProperty Command Byte # Command 0 - 3 Property tag 4 - 7 Property value K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 257 The SetProperty command has no data phase. Response: The target (Kinetis Flashloader) will return a GenericResponse packet with one of following status codes: Table 13-21. SetProperty Response Status Codes Status Code kStatus_Success kStatus_ReadOnly kStatus_UnknownProperty kStatus_InvalidArgument K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 258: Flasheraseall Command
0x5A packetType 0xA4, kFramingPacketType_Command length 0x04 0x00 crc16 0xC4 0x2E Command packet commandTag 0x01 - FlashEraseAll flags 0x00 reserved 0x00 parameterCount 0x00 The FlashEraseAll command has no data phase. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 259: Flasheraseregion Command
Response: The target (Kinetis Flashloader ) will return a GenericResponse packet with one of following error status codes. Table 13-24. FlashEraseRegion Response Status Codes Status Code kStatus_Success (0) kStatus_MemoryRangeInvalid (10200) kStatus_FlashAlignmentError (101) kStatus_FlashAddressError (102) kStatus_FlashAccessError (103) kStatus_FlashProtectionViolation (104) kStatus_FlashCommandFailure (105) K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 260: Fillmemory Command
Generic Response: 0x5a a4 0c 00 97 04 a0 00 00 02 00 00 00 00 05 00 00 00 ACK: 0x5a a1 Figure 13-10. Protocol Sequence for FillMemory Command K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 261: Writememory Command
When writing to RAM, the start address need not be aligned, and the data will not be padded. The start address and number of bytes are the 2 parameters required for WriteMemory command. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 262 Generic Response 0x5a a4 0c 00 23 72 a0 00 00 02 00 00 00 00 04 00 00 00 ACK: 0x5a a1 Figure 13-11. Protocol Sequence for WriteMemory Command K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 263: Read Memory Command
Table 13-29. Parameters for read memory command Byte Parameter Description Start address Start address of memory to read from Byte count Number of bytes to read and return to caller K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 264 Flashloader) works in slave mode, the host need pull data packets until the number of bytes of data specified in the byteCount parameter of ReadMemory command are received by host. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 265: Flashsecuritydisable Command
Table 13-32. FlashSecurityDisable Command Packet Format (Example) FlashSecurityDisable Parameter Value Framing packet start byte 0x5A packetType 0xA4, kFramingPacketType_Command length 0x0C 0x00 crc16 0x43 0x7B Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 266: Execute Command
Response: The target (Kinetis Flashloader) will return a GenericResponse packet with status code either set to kStatus_Success for successful execution of the command, or set to an appropriate error status code. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 267: Reset Command
Response: The target (Kinetis Flashloader) will return a GenericResponse packet with a status code either set to kStatus_Success upon successful execution of the command, or set to an appropriate error status code. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 268: Flashloader Exit State
• UART and UART clock source (SIM_SOPT2_PLLFLLSEL = 3) • SPI • I2C You must re-configure the corresponding register to the expected value, instead of relying on the default value. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 269: Peripherals Supported
Read 1 byte of ping response packet from target Read 1 byte 0x5A 0x7A Report Error received? received? from target Figure 13-15. Host reads ping response from target via I2C K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 270: Spi Peripheral
Figure 13-17. Host reads response from target via I2C 13.4.2 SPI Peripheral The Kinetis Flashloader supports loading data into flash via the SPI peripheral, where the SPI peripheral serves as a SPI slave. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 271 Send 0x00 to 0x5A 0xA7 Report Error shift out 1 byte received? received? from target Figure 13-18. Host reads ping packet from target via SPI K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 272: Uart Peripheral
Figure 13-20. Host reads response from target via SPI 13.4.3 UART Peripheral The Kinetis Flashloader integrates an autobaud detection algorithm for the UART peripheral, thereby providing flexible baud rate choices. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 273 • How the host detects an ACK from the target • How the host detects a ping response from the target • How the host detects a command response from the target K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 274 0x5A 0xA7 Wait for 1 byte Report Error received? received? from target Figure 13-22. Host reads a ping response from target via UART K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 275: Get/Setproperty Command Properties
VerifyWrites feature is enabled by default. 0 - No verification is done. 1 - Enable verification. MaxPacketSize Maximum supported packet size for the currently active peripheral interface. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 276: Property Definitions
Table 13-36. Bit ranges for the version components: Bits [31:24] [23:16] [15:8] [7:0] Field Name = 'K' (0x4B) Major version Minor version Bugfix version The Kinetis Codebase Version number returned for the flashloader is 1.1.0. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 277: Kinetis Flashloader Status Error Codes
= 1 << (tag - 1) Table 13-38. Command bits: [31:11] [10] 13.6 Kinetis Flashloader Status Error Codes This section describes the status error codes that the Kinetis Flashloader returns to the host. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 278 Memory range conflicts with a protected region. kStatus_UnknownProperty 10300 The requested property value is undefined. kStatus_ReadOnlyProperty 10301 The requested property value cannot be written. kStatus_InvalidPropertyValue 10302 The specified property value is invalid. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 279: Chapter 14 Reset Control Module (Rcm)
System Reset Status Register 1 (RCM_SRS1) 14.2.2/281 4007_F004 Reset Pin Filter Control register (RCM_RPFC) 14.2.3/283 4007_F005 Reset Pin Filter Width register (RCM_RPFW) 14.2.4/284 Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 280: System Reset Status Register 0 (Rcm_Srs0)
Indicates a reset has been caused by an active-low level on the external RESET pin. Reset not caused by external reset pin Reset caused by external reset pin Watchdog WDOG Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 281: System Reset Status Register 1 (Rcm_Srs1)
• POR (including LVD) — 0x00 • LVD (without POR) — 0x00 • VLLS mode wakeup — 0x00 • Other reset — a bit is set if its corresponding reset source caused the reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 282 JTAG Generated Reset JTAG Indicates a reset has been caused by JTAG selection of certain IR codes: EXTEST, HIGHZ, and CLAMP. Reset not caused by JTAG Reset caused by JTAG K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 283: Reset Pin Filter Control Register (Rcm_Rpfc)
Selects how the reset pin filter is enabled in run and wait modes. All filtering disabled Bus clock filter enabled for normal operation LPO clock filter enabled for normal operation Reserved K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 284: Reset Pin Filter Width Register (Rcm_Rpfw)
Bus clock filter count is 22 10110 Bus clock filter count is 23 10111 Bus clock filter count is 24 11000 Bus clock filter count is 25 Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 285: Sticky System Reset Status Register 0 (Rcm_Ssrs0)
Sticky Watchdog SWDOG Indicates a reset has been caused by the watchdog timer timing out.This reset source can be blocked by disabling the watchdog. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 286: Sticky System Reset Status Register 1 (Rcm_Ssrs1)
VLLS Wakeup that have not been cleared by software. Software can clear the status flags by writing a logic one to a flag. Address: 4007_F000h base + 9h offset = 4007_F009h Read SSACKERR SMDM_AP SLOCKUP SJTAG Write Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 287 Sticky JTAG Generated Reset SJTAG Indicates a reset has been caused by JTAG selection of certain IR codes: EXTEST, HIGHZ, and CLAMP. Reset not caused by JTAG Reset caused by JTAG K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 288 Reset memory map and register descriptions K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 289: Chapter 15 System Mode Controller (Smc)
The WFI or WFE instruction is used to invoke Sleep and Deep Sleep modes. Run, Wait, and Stop are the common terms used for the primary operating modes of Freescale microcontrollers. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 290 The core, system, bus, and flash clock maximum frequencies are restricted in this mode. See the Power Management chapter for details about the maximum allowable frequencies. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 291: Memory Map And Register Descriptions
For more information about the types of reset on this chip, refer to the Reset section details. NOTE The SMC registers can be written only in supervisor mode. Write accesses in user mode are blocked and will result in a bus error. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 292: Power Mode Protection Register (Smc_Pmprot)
Chip Reset not VLLS. See the Reset section details for more information. Address: 4007_E000h base + 0h offset = 4007_E000h Read AHSRUN AVLP ALLS AVLLS Write Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 293: Power Mode Control Register (Smc_Pmctrl)
(PMPROT) register. NOTE This register is reset on Chip POR not VLLS and by reset types that trigger Chip POR not VLLS. It is unaffected by reset types K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 294 NOTE: When set to STOP, the PSTOPO bits in the STOPCTRL register can be used to select a Partial Stop mode if desired. Normal Stop (STOP) Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 295: Stop Control Register (Smc_Stopctrl)
PSTOP2 - Partial Stop with system clock disabled and bus clock enabled Reserved POR Power Option PORPO This bit controls whether the POR detect circuit is enabled in VLLS0 mode. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 296: Power Mode Status Register (Smc_Pmstat)
Address: 4007_E000h base + 3h offset = 4007_E003h Read PMSTAT Write Reset SMC_PMSTAT field descriptions Field Description 7–0 Power Mode Status PMSTAT NOTE: When debug is enabled, the PMSTAT will not update to STOP or VLPS K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 297: Functional Description
15.4.1 Power mode transitions The following figure shows the power mode state transitions available on the chip. Any reset always brings the MCU back to the normal RUN state. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 298 WAIT Sleep-now or sleep-on-exit modes entered with SLEEPDEEP clear, controlled in System Control Register in ARM core. See note. WAIT Interrupt or Reset Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 299 VLLSx PMPROT[AVLLS]=1, PMCTRL[STOPM]=100, STOPCTRL[VLLSM]=x (VLLSx), Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 300: Power Mode Entry/Exit Sequencing
WFI instruction. After the instruction is executed, the following sequence occurs: 1. The CPU clock is gated off immediately. 2. Requests are made to all non-CPU bus masters to enter Stop mode. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 301: Stop Mode Exit Sequence
For wait modes (WAIT and VLPW), the CPU clock is gated off while all other clocking continues, as in RUN and VLPR mode operation. Some modules that support stop-in- wait functionality have their clocks disabled in these configurations. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 302: Transition From Stop Modes To Debug Mode
• The MCG must be configured in a mode which is supported during VLPR. See the Power Management details for information about these MCG modes. • All clock monitors in the MCG must be disabled. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 303: High Speed Run (Hsrun) Mode
RUN mode. • Stop mode entry is not supported from HSRUN. • Modifications to clock gating control bits are prohibited. • Flash programming/erasing is not allowed. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 304: Wait Modes
SIM. VLPR mode restrictions also apply to VLPW. When an interrupt from VLPW occurs, the device returns to VLPR mode to execute the interrupt service routine. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 305: Stop Modes
STOP mode is entered via the sleep-now or sleep-on-exit with the SLEEPDEEP bit set in the System Control Register in the ARM core. The MCG module can be configured to leave the reference clocks running. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 306: Very-Low-Power Stop (Vlps) Mode
In LLS, the on-chip voltage regulator is in stop regulation. Most of the peripherals are put in a state-retention mode that does not allow them to operate while in LLS. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 307: Very-Low-Leakage Stop (Vllsx) Modes
Before entering VLLS mode, the user should configure the Low-Leakage Wake-up (LLWU) module to enable the desired wakeup sources. The available wake-up sources in VLLS are detailed in the chip configuration details for this device. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 308: Debug In Low Power Modes
Reset Controller logic to hold the system in reset after the next recovery from a VLLS mode. This bit allows the debugger time to reinitialize the debug module before the debug session continues. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 309 The VLLDBGACK bit is cleared by the debugger (or can be left set as is) or clears automatically due to the reset generated as part of the next VLLS recovery. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 310 Functional description K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 311: Chapter 16 Power Management Controller (Pmc)
(V ) or low (V ). The trip voltage is selected by LVDH LVDL LVDSC1[LVDV]. The LVD is disabled upon entering VLPx, LLS, and VLLSx modes. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 312: Lvd Reset Operation
LVD voltage. The LVW also has an interrupt, which is enabled by setting LVDSC2[LVWIE]. If enabled, an LVW interrupt request occurs when LVDSC2[LVWF] is set. LVDSC2[LVWF] is cleared by writing 1 to LVDSC2[LVWACK]. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 313: I/O Retention
Width Section/ address Register name Access Reset value (in bits) page (hex) Low Voltage Detect Status And Control 1 register 4007_D000 16.5.1/314 (PMC_LVDSC1) Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 314: Low Voltage Detect Status And Control 1 Register (Pmc_Lvdsc1)
PMC_LVDSC1 field descriptions Field Description Low-Voltage Detect Flag LVDF This read-only status field indicates a low-voltage detect event. Low-voltage event not detected Low-voltage event detected Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 315: Low Voltage Detect Status And Control 2 Register (Pmc_Lvdsc2)
LVWV is reset solely on a POR Only event. The other fields of the register are reset on Chip Reset Not VLLS. For more information about these reset types, refer to the Reset section details. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 316: Regulator Status And Control Register (Pmc_Regsc)
CMP and ADC. The internal regulator provides a status bit (REGONS) indicating the regulator is in run regulation. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 317 Regulator is in stop regulation or in transition to/from it Regulator is in run regulation This field is reserved. Reserved NOTE: This reserved bit must remain cleared (set to 0). Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 318 Memory map and register descriptions PMC_REGSC field descriptions (continued) Field Description Bandgap Buffer Enable BGBE Enables the bandgap buffer. Bandgap buffer not enabled Bandgap buffer enabled K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 319: Chapter 17 Low-Leakage Wakeup Unit (Llwu)
LLS or VLLS. See the chip configuration information for wakeup input sources for this device. • External pin wake-up inputs, each of which is programmable as falling-edge, rising- edge, or any change K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 320: Modes Of Operation
When the wake-up pin filters are enabled, filter operation begins immediately. If a low leakage mode is entered within five LPO clock cycles of an active edge, the edge event will be detected by the LLWU. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 321: Debug Mode
Synchronizer Pin filter 2 detect reset flow WUPE15 FILT2[FILTSEL] LLWU_P15 Edge wakeup occurred detect External pin sources LLWU_P0 wakeup occurred Edge detect WUPE0 Figure 17-1. LLWU block diagram K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 322: Llwu Signal Descriptions
LLWU registers are unaffected by reset types that do not trigger Chip Reset not VLLS. For more information about the types of reset on this chip, refer to the Introduction details. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 323: Llwu Pin Enable 1 Register (Llwu_Pe1)
External input pin enabled with any change detection 5–4 Wakeup Pin Enable For LLWU_P2 WUPE2 Enables and configures the edge detection for the wakeup pin. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 324: Llwu Pin Enable 2 Register (Llwu_Pe2)
Enables and configures the edge detection for the wakeup pin. External input pin disabled as wakeup input External input pin enabled with rising edge detection Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 325: Llwu Pin Enable 3 Register (Llwu_Pe3)
Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 2h offset = 4007_C002h Read WUPE11 WUPE10 WUPE9 WUPE8 Write Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 326: Llwu Pin Enable 4 Register (Llwu_Pe4)
This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 327: Llwu Module Enable Register (Llwu_Me)
LLWU_ME contains the bits to enable the internal module flag as a wakeup input source for inputs MWUF7–MWUF0. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 328 Enables an internal module as a wakeup source input. Internal module flag not used as wakeup source Internal module flag used as wakeup source Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 329: Llwu Flag 1 Register (Llwu_F1)
Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF6. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 330 Indicates that an enabled external wake-up pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF0. LLWU_P0 input was not a wakeup source LLWU_P0 input was a wakeup source K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 331: Llwu Flag 2 Register (Llwu_F2)
Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF13. LLWU_P13 input was not a wakeup source LLWU_P13 input was a wakeup source Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 332: Llwu Flag 3 Register (Llwu_F3)
CMP module, the flag from the associated peripheral is accessible as the MWUFx bit. The flag will need to be cleared in the peripheral instead of writing a 1 to the MWUFx bit. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 333 Module 3 input was not a wakeup source Module 3 input was a wakeup source Wakeup flag For module 2 MWUF2 Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 334: Llwu Pin Filter 1 Register (Llwu_Filt1)
Indicates that the filtered external wakeup pin, selected by FILTSEL, was a source of exiting a low-leakage power mode. To clear the flag write a one to FILTF. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 335: Llwu Pin Filter 2 Register (Llwu_Filt2)
Indicates that the filtered external wakeup pin, selected by FILTSEL, was a source of exiting a low-leakage power mode. To clear the flag write a one to FILTF. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 336: Functional Description
5 cycles of delay before the detect circuit alerts the system to the wakeup or reset event when the filter function is enabled. Two wakeup detect filters are available for selected external pins. Glitch filtering is not provided on the internal modules. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 337: Lls Mode
LLWU flag from being falsely set when PMC_REGSC[ACKISO] is cleared. The signal selected as a wake-up source pin must be a digital pin, as selected in the pin mux control. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 338 Functional description K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 339: Chapter 18 Miscellaneous Control Module (Mcm)
Crossbar Switch (AXBS) Slave Configuration E008_0008 000Fh 18.2.1/340 (MCM_PLASC) Crossbar Switch (AXBS) Master Configuration E008_000A 0017h 18.2.2/340 (MCM_PLAMC) E008_000C Crossbar Switch (AXBS) Control Register (MCM_PLACR) 0000_0000h 18.2.3/341 Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 340: Crossbar Switch (Axbs) Slave Configuration (Mcm_Plasc)
PLAMC is a 16-bit read-only register identifying the presence/absence of bus master connections to the device's crossbar switch. Address: E008_0000h base + Ah offset = E008_000Ah Read Write Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 341: Crossbar Switch (Axbs) Control Register (Mcm_Placr)
This read-only field is reserved and always has the value 0. Arbitration select Fixed-priority arbitration for the crossbar masters Round-robin arbitration for the crossbar masters 8–0 This field is reserved. Reserved K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 342: Interrupt Status And Control Register (Mcm_Iscr)
Address: E008_0000h base + 10h offset = E008_0010h Reserved Reset Reset MCM_ISCR field descriptions Field Description FPU input denormal interrupt enable FIDCE Disable interrupt Enable interrupt Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 343 FPU. Once set, this bit remains set until software clears the FPSCR[UFC] bit. No interrupt Interrupt occurred FPU overflow interrupt status FOFC Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 344 FPU. Once set, this bit remains set until software clears the FPSCR[IOC] bit. No interrupt Interrupt occurred 7–0 This field is reserved. Reserved This read-only field is reserved and always has the value 0. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 345: Compute Operation Control Register (Mcm_Cpo)
Compute operation entry has completed or compute operation exit has not completed. Compute Operation request CPOREQ This bit is auto-cleared by vector fetching if CPOWOI = 1. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 346: Functional Description
To determine the exact source of the interrupt qualify the interrupt status flags with the corresponding interrupt enable bits. 1. Form MCM_ISCR[31:16] && MCM_ISCR[15:0] 2. Search the result for asserted flags, which indicate the exact interrupt sources K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 347: Chapter 19 Crossbar Switch Lite (Axbs-Lite)
• Allows concurrent accesses from different masters to different slaves • 32-bit data bus • Operation at a 1-to-1 clock frequency with the bus masters • Programmable configuration for fixed-priority or round-robin slave port arbitration K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 348: Memory Map / Register Definition
The master can also lose control of the slave port if another higher-priority master makes a request to the slave port. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 349: Arbitration
The following table describes possible scenarios based on the requesting master port: K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 350: Round-Robin Priority Operation
(compared to fixed priority) as the fixed master priority does not affect the master selection. 19.4 Initialization/application information No initialization is required for the crossbar switch. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 351 Chapter 19 Crossbar Switch Lite (AXBS-Lite) See the AXBS section of the configuration chapter for the reset state of the arbitration scheme. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 352 Initialization/application information K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 353: Chapter 20 Peripheral Bridge (Aips-Lite)
The peripheral bridge performs a bus protocol conversion of the master transactions and generates the following as inputs to the peripherals: • Module enables • Module addresses K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 354: Functional Description
All accesses to the peripheral slots must be sized less than or equal to the designated peripheral slot size. If an access is attempted that is larger than the targeted port, an error response is generated. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 355: Chapter 21 Direct Memory Access Multiplexer (Dmamux)
21.1.1 Overview The Direct Memory Access Multiplexer (DMAMUX) routes DMA sources, called slots, to any of the four DMA channels. This process is illustrated in the following figure. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 356: Features
• Each channel router can be assigned to one of the possible peripheral DMA slots or to one of the always-on slots. 21.1.3 Modes of operation The following operating modes are available: K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 357: External Signal Description
Reset value (in bits) page (hex) 4002_1000 Channel Configuration register (DMAMUX_CHCFG0) 21.3.1/358 4002_1001 Channel Configuration register (DMAMUX_CHCFG1) 21.3.1/358 4002_1002 Channel Configuration register (DMAMUX_CHCFG2) 21.3.1/358 4002_1003 Channel Configuration register (DMAMUX_CHCFG3) 21.3.1/358 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 358: Channel Configuration Register (Dmamux_Chcfgn)
DMAMUX information for details about the peripherals and their slot numbers. 21.4 Functional description The primary purpose of the DMAMUX is to provide flexibility in the system's use of the available DMA channels. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 359: Dma Channels With Periodic Triggering Capability
Because of the dynamic nature of the system (due to DMA channel priorities, bus arbitration, interrupt service routine lengths, etc.), the number of clock cycles between a trigger and the actual DMA transfer cannot be guaranteed. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 360 This means that if a trigger is seen, but the peripheral is not requesting a transfer, then that trigger will be ignored. This situation is illustrated in the following figure. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 361: Dma Channels With No Triggering Capability
21.4.2 DMA channels with no triggering capability The other channels of the DMAMUX provide the normal routing functionality as described in Modes of operation. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 362: Always-Enabled Dma Sources
DMA registers after every minor loop. For this option, the DMA channel must be disabled in the DMA channel MUX. • Use an always-enabled DMA source. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 363: Initialization/Application Information
DMA channels that have triggering capability. To configure source #5 transmit for use with DMA channel 1, with periodic triggering capability: 1. Write 0x00 to CHCFG1 (base address + 0x01). K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 364 *CHCFG10= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000A); volatile unsigned char *CHCFG11= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000B); volatile unsigned char *CHCFG12= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000C); volatile unsigned char *CHCFG13= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000D); K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 365 *CHCFG12= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000C); volatile unsigned char *CHCFG13= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000D); volatile unsigned char *CHCFG14= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000E); volatile unsigned char *CHCFG15= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000F); K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 366 Initialization/application information In File main.c: #include "registers.h" *CHCFG8 = 0x00; *CHCFG8 = 0x87; K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 367: Chapter 22 Enhanced Direct Memory Access (Edma)
• Local memory containing transfer control descriptors for each of the 4 channels 22.1.1 eDMA system block diagram Figure 22-1 illustrates the components of the eDMA system, including the eDMA module ("engine"). K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 368: Block Parts
22.1.2 Block parts The eDMA module is partitioned into two major modules: the eDMA engine and the transfer-control descriptor local memory. The eDMA engine is further partitioned into four submodules: K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 369 As noted earlier, in the event of simultaneous accesses, the eDMA engine is given priority and the peripheral transaction is stalled. Memory array TCD storage for each channel's transfer profile. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 370: Features
• Optional error terminations per channel and logically summed together to form one error interrupt to the interrupt controller • Optional support for scatter/gather DMA processing • Support for complex data structures K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 371: Modes Of Operation
The channel descriptors are stored in the local memory in sequential order: channel 0, channel 1, ... channel 3. Each TCDn definition is presented as 11 registers of 16 or 32 bits. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 372: Tcd Initialization
Memory map/register definition 22.3.2 TCD initialization Prior to activating a channel, you must initialize its TCD with the appropriate transfer profile. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 373: Tcd Structure
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 The fields implemented in Word 2 depend on whether DMA_CR[EMLM] is 0 or 1. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 374: Reserved Memory And Bit Fields
Channel n Priority Register (DMA_DCHPRI3) See section 22.3.17/397 4000_8101 Channel n Priority Register (DMA_DCHPRI2) See section 22.3.17/397 4000_8102 Channel n Priority Register (DMA_DCHPRI1) See section 22.3.17/397 Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 375 4000_9034 Undefined 22.3.26/404 (DMA_TCD1_DOFF) TCD Current Minor Loop Link, Major Loop Count (Channel 4000_9036 Undefined 22.3.27/404 Linking Enabled) (DMA_TCD1_CITER_ELINKYES) 4000_9036 DMA_TCD1_CITER_ELINKNO Undefined 22.3.28/406 Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 376 TCD Signed Minor Loop Offset (Minor Loop Enabled and 4000_9068 Undefined 22.3.22/400 Offset Disabled) (DMA_TCD3_NBYTES_MLOFFNO) TCD Signed Minor Loop Offset (Minor Loop and Offset 4000_9068 Undefined 22.3.23/402 Enabled) (DMA_TCD3_NBYTES_MLOFFYES) Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 377: Control Register (Dma_Cr)
TCD. If the major loop is complete, the minor loop offset is ignored and the major loop address offsets (TCDn_SLAST and TCDn_DLAST_SGA) are used to compute the next TCDn_SADDR and TCDn_DADDR values. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 378 When minor loop mapping is disabled (EMLM is 0), all 32 bits of TCDn word2 are assigned to the NBYTES field. Address: 4000_8000h base + 0h offset = 4000_8000h Reserved Reset Reset * Notes: • x = Undefined at reset. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 379 Halt On Error Normal operation Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 380: Error Status Register (Dma_Es)
Address: 4000_8000h base + 4h offset = 4000_8004h Reset ERRCHN Reset DMA_ES field descriptions Field Description Logical OR of all ERR status bits Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 381 • TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or • TCDn_CITER[CITER] is equal to zero, or • TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 382: Enable Request Register (Dma_Erq)
Reset DMA_ERQ field descriptions Field Description 31–4 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 383: Enable Error Interrupt Register (Dma_Eei)
Reset DMA_EEI field descriptions Field Description 31–4 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 384: Clear Enable Error Interrupt Register (Dma_Ceei)
DMA_CEEI field descriptions Field Description No Op enable Normal operation No operation, ignore the other bits in this register Clear All Enable Error Interrupts CAEE Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 385: Set Enable Error Interrupt Register (Dma_Seei)
Set only the EEI bit specified in the SEEI field. Sets all bits in EEI 5–2 This field is reserved. Reserved 1–0 Set Enable Error Interrupt SEEI Sets the corresponding bit in EEI K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 386: Clear Enable Request Register (Dma_Cerq)
Clear only the ERQ bit specified in the CERQ field Clear all bits in ERQ 5–2 This field is reserved. Reserved 1–0 Clear Enable Request CERQ Clears the corresponding bit in ERQ. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 387: Set Enable Request Register (Dma_Serq)
Set only the ERQ bit specified in the SERQ field Set all bits in ERQ 5–2 This field is reserved. Reserved 1–0 Set Enable Request SERQ Sets the corresponding bit in ERQ. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 388 Clears only the TCDn_CSR[DONE] bit specified in the CDNE field Clears all bits in TCDn_CSR[DONE] 5–2 This field is reserved. Reserved 1–0 Clear DONE Bit CDNE Clears the corresponding bit in TCDn_CSR[DONE] K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 389 Set only the TCDn_CSR[START] bit specified in the SSRT field Set all bits in TCDn_CSR[START] 5–2 This field is reserved. Reserved 1–0 Set START Bit SSRT Sets the corresponding bit in TCDn_CSR[START] K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 390 Clear only the ERR bit specified in the CERR field Clear all bits in ERR 5–2 This field is reserved. Reserved 1–0 Clear Error Indicator CERR Clears the corresponding bit in ERR K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 391 Clear only the INT bit specified in the CINT field Clear all bits in INT 5–2 This field is reserved. Reserved 1–0 Clear Interrupt Request CINT Clears the corresponding bit in INT K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 392 Interrupt Request 2 INT2 The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active Interrupt Request 1 INT1 Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 393 The CERR is provided so the error indicator for a single channel can easily be cleared. Address: 4000_8000h base + 2Ch offset = 4000_802Ch Reset ERR3 ERR2 ERR1 ERR0 Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 394 These bits reflect the state of the request as seen by the arbitration logic. Therefore, this status is affected by the ERQ bits. Address: 4000_8000h base + 34h offset = 4000_8034h Reset HRS3 HRS2 HRS1 HRS0 Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 395 Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically cleared by hardware. A hardware service request for channel 0 is not present A hardware service request for channel 0 is present K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 396 Enable asynchronous DMA request for channel 1. Enable asynchronous DMA request in stop mode for channel 0. EDREQ_0 Disable asynchronous DMA request for channel 0. Enable asynchronous DMA request for channel 0. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 397 Channel priority when fixed-priority arbitration is enabled NOTE: Reset value for the channel priority field, CHPRI, is equal to the corresponding channel number for each priority register, that is, DCHPRI3[CHPRI] = 0b11. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 398 DMA_TCDn_SOFF field descriptions Field Description 15–0 Source address signed offset SOFF Sign-extended offset applied to the current source address to form the next-state value as each source read is completed. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 399 16-byte 32-byte burst (4 beats of 64 bits) Reserved Reserved 7–3 Destination Address Modulo DMOD See the SMOD definition 2–0 Destination data transfer size DSIZE See the SSIZE definition K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 400 Which register to use depends on whether minor loop mapping is disabled, enabled but not used for this channel, or enabled and used. TCD word 2 is defined as follows if: K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 401 After the minor count is exhausted, the SADDR and DADDR values are written back into the TCD memory, the major iteration count is decremented and restored to the TCD memory. If the major iteration count is completed, additional processing is performed. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 402 The minor loop offset is applied to the SADDR Destination Minor Loop Offset enable DMLOE Selects whether the minor loop offset is applied to the destination address upon minor loop completion. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 403 Reset * Notes: • x = Undefined at reset. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 404 Address: 4000_8000h base + 1016h offset + (32d × i), where i=0d to 3d Read ELINK LINKCH CITER Write Reset Read CITER Write Reset * Notes: • x = Undefined at reset. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 405 NOTE: When the CITER field is initially loaded by software, it must be set to the same value as that contained in the BITER field. NOTE: If the channel is configured to execute a single service request, the initial values of BITER and CITER should be 0x0001. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 406 NOTE: When the CITER field is initially loaded by software, it must be set to the same value as that contained in the BITER field. NOTE: If the channel is configured to execute a single service request, the initial values of BITER and CITER should be 0x0001. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 407 Address: 4000_8000h base + 101Ch offset + (32d × i), where i=0d to 3d Read MAJORLINKCH Write Reset Read MAJORELI DONE ACTIVE DREQ INTHALF INTMAJOR START Write Reset * Notes: • x = Undefined at reset. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 408 NOTE: To support the dynamic scatter/gather coherency model, this field is forced to zero when written to while the TCDn_CSR[DONE] bit is set. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 409 If this flag is set, the channel is requesting service. The eDMA hardware automatically clears this flag after the channel begins execution. The channel is not explicitly started. The channel is explicitly started via a software initiated service request. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 410 CITER field. As the major iteration count is exhausted, the contents of this field are reloaded into the CITER field. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 411 NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field; otherwise, a configuration error is reported. As the major iteration count is exhausted, the Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 412: Functional Description
Engine Program Model/ Read Data Channel Arbitration Read Data Address Path Control Data Path Write Data Address eDMA Peripheral eDMA Done Request Figure 22-98. eDMA operation, part 1 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 413 Engine Program Model/ Read Data Channel Arbitration Read Data Address Path Control Data Path Write Data Address eDMA Peripheral eDMA Done Request Figure 22-99. eDMA operation, part 2 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 414 En g in e Program Model/ Read Data Channel Arbitration Read Data Address Path Control Data Path Write Data Address eDMA Peripheral eDMA Done Request Figure 22-100. eDMA operation, part 3 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 415: Fault Reporting And Handling
If a bus error occurs on the last read prior to beginning the write sequence, the write executes using the K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 416: Channel Preemption
After a preempting channel begins execution, it cannot be preempted. Preemption is available only when fixed arbitration is selected. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 417: Performance
• All internal peripheral bus accesses are 32-bits in size This table compares peak transfer rates based on different possible system speeds. Specific chips/devices may not support all system speeds listed. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 418 TCDn word 7. Channel arbitration begins. Channel arbitration completes. The transfer control descriptor local memory read is initiated. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 419 Table 22-103. eDMA peak request rate (MReq/sec) Request rate Request rate System frequency (MHz) with zero wait states with wait states 66.6 83.3 100.0 11.1 133.3 14.8 11.6 150.0 16.6 13.0 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 420 The minimum number of cycles to perform a single read/write, zero wait states on the system bus, from a cold start where no channel is executing and eDMA is idle are: K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 421: Initialization/Application Information
5. Enable any hardware service requests via the ERQH and ERQL registers. 6. Request channel service via either: • Software: setting the TCDn_CSR[START] • Hardware: slave device asserting its eDMA peripheral request signal K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 422 CPU intervention. DMA arbitration can occur after each minor loop, and one level of minor loop DMA preemption is allowed. The number of minor loops in a major loop is specified by the beginning iteration count (BITER). K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 423: Programming Errors
The eDMA performs various tests on the transfer control descriptor to verify consistency in the descriptor data. Most programming errors are reported on a per channel basis with the exception of channel priority error (ES[CPE]). K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 424: Arbitration Mode Considerations
(TCDn_CITER = TCDn_BITER = 1). The data transfer begins after the channel service request is acknowledged and the channel is selected to execute. After the transfer is complete, the TCDn_CSR[DONE] bit is set and an interrupt generates if properly enabled. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 425 Write 32-bits to location 0x2008 → third iteration of the minor loop. g. Read byte from location 0x100C, read byte from location 0x100D, read byte from 0x100E, read byte from 0x100F. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 426: Multiple Requests
Write 32-bits to location 0x2004 → second iteration of the minor loop. e. Read byte from location 0x1008, read byte from location 0x1009, read byte from 0x100A, read byte from 0x100B. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 427 Write 32-bits to location 0x201C → last iteration of the minor loop → major loop complete. 14. eDMA engine writes: TCDn_SADDR = 0x1000, TCDn_DADDR = 0x2000, TCDn_CITER = 2 (TCDn_BITER). K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 428: Using The Modulo Feature
The first is to read the TCDn_CITER field and test for a change. Another method may be extracted from the sequence shown below. The second method is K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 429: Reading The Transfer Descriptors Of Active Channels
NBYTES are the values the eDMA engine currently uses in its internal register file and not the values in the TCD local memory for that channel. The addresses, SADDR and K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 430: Checking Channel Preemption Status
TCDn_CITER[E_LINK] = 1 TCDn_CITER[LINKCH] = 0xC TCDn_CITER[CITER] value = 0x4 TCDn_CSR[MAJOR_E_LINK] = 1 TCDn_CSR[MAJOR_LINKCH] = 0x7 executes as: 1. Minor loop done → set TCD12_CSR[START] bit K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 431: Dynamic Programming
This section provides recommended methods to change the programming model during channel execution. 22.5.7.1 Dynamically changing the channel priority The following two options are recommended for dynamically changing channel priority levels: K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 432: Dynamic Channel Linking
NOTE The user must clear the TCD.done bit before writing the TCD.major.e_link bit. The TCD.done bit is cleared automatically by the eDMA engine after a channel begins execution. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 433: Dynamic Scatter/Gather
1. When the descriptors are built, write a unique TCD ID in the TCD.major.linkch field for each TCD associated with a channel using dynamic scatter/gather. 2. Write 1b to the TCD.d_req bit. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 434 If e_sg = 0b, read the 32 bit TCD dlast_sga field. If e_sg = 0b and the dlast_sga did not change, the attempted dynamic link did not succeed (the channel was already retiring). K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 435 Chapter 22 Enhanced Direct Memory Access (eDMA) If e_sg = 0b and the dlast_sga changed, the dynamic link attempt was successful (the new TCD’s e_sg value cleared the e_sg bit). K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 436 Initialization/application information K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 437: Chapter 23 External Watchdog Monitor (Ewm)
23.1.1 Features Features of EWM module include: • Independent LPO clock source • Programmable time-out period specified in terms of number of EWM LPO clock cycles. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 438: Modes Of Operation
15 (EWM_service_time) peripheral bus clocks after exiting from stop mode. User must mask all interrupts prior to executing EWM service instructions. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 439: Wait Mode
EWM enable Counter >Compare High EWM Out Counter < Compare Low Logic EWM_out ((EWM_in ^ assert_in) || ~EWM_in_enable) Compare High > Counter > Compare Low Figure 23-1. EWM Block Diagram K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 440: Ewm Signal Descriptions
INEN, ASSIN and EWMEN bits can be written once after a CPU reset. Modifying these bits more than once, generates a bus transfer error. Address: 4006_1000h base + 0h offset = 4006_1000h Read INTEN INEN ASSIN EWMEN Write Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 441: Service Register (Ewm_Serv)
23.3.3 Compare Low Register (EWM_CMPL) The CMPL register is reset to zero after a CPU reset. This provides no minimum time for the CPU to service the EWM counter. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 442: Compare High Register (Ewm_Cmph)
7–0 To prevent runaway code from changing this field, software should write to this field after a CPU reset COMPAREH even if the (default) maximum service time is required. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 443: Clock Prescaler Register (Ewm_Clkprescaler)
The EWM_out signal remains deasserted when the EWM is being regularly serviced by the CPU within the programmable service window, indicating that the application code is executed as expected. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 444: The Ewm_In Signal
(setting the CTRL[INEN] bit), the EWM_in signal must be in the deasserted state prior to the CPU servicing the EWM. This ensures that the EWM_out stays in the deasserted state; otherwise, the EWM_out pin is asserted. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 445: Ewm Counter
EWM Service Register. The CPU must access the EWM service register with correct write of unique data within the windowed time frame as determined by the CMPL and CMPH registers. Therefore, three possible conditions can occur: K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 446: Ewm Interrupt
CLKPRESCALER[CLK_DIV]. This divided clock is used to run the EWM counter. NOTE The divided clock used to run the EWM counter must be no more than half the frequency of the bus clock. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 447: Chapter 24 Watchdog Timer (Wdog)
• External system clock • Unlock sequence for allowing updates to write-once WDOG control/configuration bits. • All WDOG control/configuration bits are writable once only within 256 bus clock cycles of being unlocked. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 448 • Count of WDOG resets as they occur. • Configurable interrupt on time-out to provide debug breadcrumbs. This is followed by a reset after 256 bus clock cycles. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 449: Functional Overview
CPU clock stopping or a run-away condition in code execution. In its simplest form, the watchdog timer runs continuously off a clock source and expects K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 450: Unlocking And Updating The Watchdog
After the update window closes, the watchdog timer restarts and the watchdog functions according to the new configuration. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 451: Watchdog Configuration Time (Wct)
2xWCT + 20 bus clock cycles. Therefore, it must be ensured that the time-out value for the watchdog is always greater than 2xWCT time + 20 bus clock cycles. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 452: Refreshing The Watchdog
In this mode, the watchdog timer cannot be refreshed–there is no requirement to do so while the timer is disabled. However, the watchdog still generates a reset, or interrupt-then-reset if enabled, on a non- K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 453: Debug Modes Of Operation
After it is set, this test-disable bit can only be cleared by a reset. These two tests achieve the overall aim of testing the counter functioning and the compare and reset logic. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 454: Quick Test
The following figure explains the splitting concept: K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 455: Backup Reset Generator
Two successive timer time-outs without an intervening system reset result in the backup reset generator routing out the time-out signal as a reset to the system. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 456: Generated Resets And Interrupts
Also, jobs such as counting the number of watchdog resets would not be done. 24.7 Memory map and register definition This section consists of the memory map and register descriptions. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 457: Watchdog Status And Control Register High (Wdog_Stctrlh)
This 2-bit field selects the byte to be tested when the watchdog is in the byte test mode. BYTESEL[1:0] Byte 0 selected Byte 1 selected Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 458 A change in the value of this bit must be held for more than one WDOG_CLK cycle for the WDOG to be enabled or disabled. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 459: Watchdog Status And Control Register Low (Wdog_Stctrll)
Field Description 15–0 Defines the upper 16 bits of the 32-bit time-out value for the watchdog timer. It is defined in terms of cycles TOVALHIGH of the watchdog clock. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 460: Watchdog Time-Out Value Register Low (Wdog_Tovall)
A refresh outside this window resets the system or if IRQRSTEN is set, it interrupts and then resets the system. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 461: Watchdog Window Register Low (Wdog_Winl)
20 bus cycles, resets the system, or if IRQRSTEN is set, it interrupts and then resets the system. 24.7.8 Watchdog Unlock register (WDOG_UNLOCK) Address: 4005_2000h base + Eh offset = 4005_200Eh Read WDOGUNLOCK Write Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 462: Watchdog Timer Output Register High (Wdog_Tmrouth)
Address: 4005_2000h base + 12h offset = 4005_2012h Read TIMEROUTLOW Write Reset WDOG_TMROUTL field descriptions Field Description 15–0 Shows the value of the lower 16 bits of the watchdog timer. TIMEROUTLOW K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 463: Watchdog Reset Count Register (Wdog_Rstcnt)
When performing 8-bit accesses to the watchdog's 16-bit registers where the intention is to access both the bytes of a register, place the two 8-bit accesses one after the other in your code. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 464: Refresh And Unlock Operations With 8-Bit Access
16-bit value is correctly written, write4. Hence, the requirement of writing value2 of the sequence within 20 bus clock cycles of value1 is checked by measuring the gap between write2 and write4. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 465: Restrictions On Watchdog Operation
• The time-out value of the watchdog should be set to a minimum of four watchdog clock cycles. This is to take into account the delay in new settings taking effect in the watchdog clock domain. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 466 If the second refresh value is not written within 20 bus cycles of the first value, the system is reset, or interrupt-then- reset if enabled. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 467: Chapter 25 Multipurpose Clock Generator (Mcg)
• Option to program and maximize DCO output frequency for a low frequency external reference clock source. • Option to prevent FLL from resetting its current locked frequency when switching clock modes if FLL reference frequency is not changed. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 468 • Reference dividers for the FLL are provided • Reference dividers for the Fast Internal Reference Clock are provided • MCG FLL Clock (MCGFLLCLK) is provided as a clock source for other on-chip peripherals K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 469 Clock Valid BUSCLK Multipurpose Clock Generator (MCG) Figure 25-1. Multipurpose Clock Generator (MCG) block diagram NOTE Refer to the chip configuration chapter to identify the oscillator used in this MCU. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 470: Modes Of Operation
4006_400D MCG Control 8 Register (MCG_C8) See section 25.3.11/479 25.3.1 MCG Control 1 Register (MCG_C1) Address: 4006_4000h base + 0h offset = 4006_4000h Read CLKS FRDIV IREFS IRCLKEN IREFSTEN Write Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 471 Internal reference clock is disabled in Stop mode. Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 472: Mcg Control 2 Register (Mcg_C2)
In any other MCG mode, LP bit has no affect. FLL is not disabled in bypass modes. FLL is disabled in bypass modes (lower power) Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 473: Mcg Control 3 Register (Mcg_C3)
If an SCTRIM value stored in nonvolatile memory is to be used, it is your responsibility to copy that value from the nonvolatile memory location to this register. 1. A value for SCTRIM is loaded during reset from a factory programmed location. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 474: Mcg Control 4 Register (Mcg_C4)
DRST field does not update immediately after a write to the DRS field due to internal synchronization between clock domains. See the DCO Frequency Range table for more details. Encoding 0 — Low range (reset default). Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 475: Mcg Control 6 Register (Mcg_C6)
VLPW power modes if the MCG is in BLPE mode. External clock monitor is disabled. Generate a reset request on loss of external clock. 4–0 Reserved Reserved Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 476: Mcg Status Register (Mcg_S)
MCG being in a mode that uses the IRC or by setting the C1[IRCLKEN] bit . Source of internal reference clock is the slow clock (32 kHz IRC). Source of internal reference clock is the fast clock (4 MHz IRC). K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 477: Mcg Status And Control Register (Mcg_Sc)
31.25 kHz to 4 MHz (Note: Changing the divider when the Fast IRC is enabled is not supported). Divide Factor is 1 Divide Factor is 2. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 478: Mcg Auto Trim Compare Value High Register (Mcg_Atcvh)
MCG_ATCVL field descriptions Field Description 7–0 ATM Compare Value Low ATCVL Values are used by Auto Trim Machine to compare and adjust Internal Reference trim values during ATM SAR conversion. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 479: Mcg Control 7 Register (Mcg_C7)
Interrupt request is generated on a loss of RTC external reference clock. Generate a reset request on a loss of RTC external reference clock Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 480: Functional Description
25.4.1 MCG mode state diagram The seven states of the MCG are shown in the following figure and are described in Table 25-13. The arrows indicate the permitted MCG mode transitions. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 481: Mcg Modes Of Operation
Internal Reference Clock (IRC). The FLL loop will lock the DCO frequency to the FLL factor, as selected by C4[DRST_DRS] and C4[DMX32] bits, times the internal reference frequency. See the C4[DMX32] bit description for more details. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 482 • 1 is written to C1[IREFS]. • 1 is written to C2[LP]. In BLPI mode, MCGOUTCLK is derived from the internal reference clock. The FLL is disabled Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 483: Mcg Mode Switching
DCO clock. After switching to the new DCO (indicated by the updated C4[DRST_DRS] read bits), the FLL remains unlocked for several reference cycles. The FLL lock time is provided in the device data sheet as fll_acquire K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 484: Low-Power Bit Usage
MCGOUTCLK frequency if the MCG is in FEI mode. Additionally, this clock can be enabled in Stop mode by setting C1[IRCLKEN] and C1[IREFSTEN], otherwise this clock is disabled in Stop mode. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 485: External Reference Clock
The MCG Auto Trim (ATM) is a MCG feature that when enabled, it configures the MCG hardware to automatically trim the MCG Internal Reference Clocks using an external clock as a reference. The selection between which MCG IRC clock gets tested and K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 486 128 before storing it in the ATCV register. Therefore, the ATCV Expected Count Value for trimming the 4 MHz IRC is calculated using the following formula. (128) K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 487: Initialization / Application Information
• If entering FBE, clear C1[IREFS] to switch to the external reference and change C1[CLKS] to 2'b10 so that the external reference clock is selected as the system clock source. The C1[FRDIV] bits should also be set appropriately here K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 488 32.768 kHz reference is desired, set C4[DRST_DRS] bits to 2'b01 and set C4[DMX32] bit to 1. The resulting DCO output (MCGOUTCLK) frequency with the new multiplier of 1464 will be 48 MHz. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 489: Using A 32.768 Khz Reference
62.91 MHz at mid high-range. If C4[DRST_DRS] bits are set to 2'b11, the multiplication factor is set to 2560, and the resulting DCO output frequency is 83.89 MHz at high-range. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 490: Mcg Mode Switching
1. FLL_R is the reference divider selected by the C1[FRDIV] bits, F is the FLL factor selected by C4[DRST_DRS] and C4[DMX32] bits. This section will include three mode switching examples using an MHz external crystal. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 491 Loop until S[CLKST] is 2'b10, indicating that the external reference clock is selected to feed MCGOUTCLK. 2. Then, transition to BLPE: a. Set C2[LP] to 1. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 492 S[IREFST] = 0? CHECK S[CLKST] = %10? C2 = 0x1E (C2[LP] = 1) Continue in BLPE mode Figure 25-14. Flowchart of FEI to BLPE mode transition using a 4 MHz crystal K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 493: Example 2: Moving From Blpe To Blpi Mode: Mcgoutclk Frequency = 2 Mhz
C1[IREFS] bit is set. They can remain set, or be cleared at this point. b. Loop until S[IRCST] is 1, indicating the internal reference clock is the fast clock. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 494 S[IREFST] = 0? CHECK S[CLKST] = %01? C2 = 0x23 CHECK S[IRCST] = 1? CONTINUE IN BLPI MODE Figure 25-15. Flowchart of BLPE to BLPI mode transition using an MHz crystal K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 495: Example 3: Moving From Blpi To Fee Mode
At this point, by default, the C4[DRST_DRS] bits are set to 2'b00 and C4[DMX32] is cleared to 0. If the MCGOUTCLK frequency of 40 MHz is desired instead, set the C4[DRST_DRS] bits to 0x01 to switch the FLL K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 496 S[CLKST] = %00? C1 = 0x10 CONTINUE IN FEE MODE CHECK S[OSCINIT] = 1 ? Figure 25-16. Flowchart of BLPI to FEE mode transition using an 4 MHz crystal K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 497: Chapter 26 Oscillator (Osc)
• Optionally external input bypass clock from EXTAL signal directly • One clock for MCU clock system • Two clocks for on-chip peripherals that can work in Stop modes Functional Description describes the module's operation in more detail. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 498: Block Diagram
OSCCLK OSC clock selection logic STOP Figure 26-1. OSC Module Block Diagram 26.4 OSC Signal Descriptions The table found here shows the user-accessible signals available for the OSC module. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 499: External Crystal / Resonator Connections
2. With the low-power mode, the oscillator has the internal feedback resistor R . Therefore, the feedback resistor must not be externally with the Connection 3. XTAL EXTAL Crystal or Resonator Figure 26-2. Crystal/Ceramic Resonator Connections - Connection 1 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 500: External Clock Connections
In external clock mode, the pins can be connected as shown in the figure found here. NOTE XTAL can be used as a GPIO when the GPIO alternate function is configured for it. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 501: Memory Map/Register Definitions
Address: 4006_5000h base + 0h offset = 4006_5000h Read ERCLKEN EREFSTEN SC2P SC4P SC8P SC16P Write Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 502 Add 8 pF capacitor to the oscillator load. Oscillator 16 pF Capacitor Load Configure SC16P Configures the oscillator load. Disable the selection. Add 16 pF capacitor to the oscillator load. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 503: Functional Description
26.8.1 OSC module states The states of the OSC module are shown in the following figure. The states and their transitions between each other are described in this section. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 504 MCU, refer to the chip configuration details. The EXTAL and XTAL pins are also decoupled from all other oscillator circuitry in this state. The OSC module circuitry is configured to draw minimal current. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 505: Oscillator Startup
(MCG, Timer, and so on) is configured to use the oscillator output clock (OSC_CLK_OUT). Table 26-6. Oscillator modes Mode Frequency Range Low-frequency, high-gain (32.768 kHz) up to f (39.0625 kHz) osc_lo osc_lo Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 506: Low-Frequency, High-Gain Mode
(not sensitive to the DC level of EXTAL). Also in this mode, all external components except for the resonator itself are integrated, which includes the load capacitors and feeback resistor that biases EXTAL. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 507: High-Frequency, High-Gain Mode
There is no reset state associated with the OSC module. The counter logic is reset when the OSC is not configured to generate clocks. There are no sources of reset requests for the OSC module. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 508: Low Power Modes Operation
OSC is still functional in these modes. After waking up from Very Low Leakage Stop (VLLSx) modes, all OSC register bits are reset and initialization is required through software. 26.11 Interrupts The OSC module does not generate any interrupts. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 509: Chapter 27 Flash Memory Controller (Fmc)
64-bit flash memory location, and both a 4-way, 8-set cache and a single-entry 64-bit buffer can store previously accessed flash memory data for quick access times. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 510: Modes Of Operation
The programming model consists of the FMC control registers and the program visible cache (data and tag/valid entries). NOTE Program the registers only while the flash controller is idle (for example, execute from RAM). Changing configuration settings K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 511 [63:32] of data entry way 1, and U and L represent upper and set 0, and DATAW1S0L lower word, respectively. represents bits [31:0] of data entry way 1, set 0. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 512 Cache Data Storage (upper word) (FMC_DATAW0S0U) 0000_0000h 27.4.8/527 4001_F204 Cache Data Storage (lower word) (FMC_DATAW0S0L) 0000_0000h 27.4.9/528 4001_F208 Cache Data Storage (upper word) (FMC_DATAW0S1U) 0000_0000h 27.4.8/527 Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 513 4001_F26C Cache Data Storage (lower word) (FMC_DATAW1S5L) 0000_0000h 27.4.10/ 4001_F270 Cache Data Storage (upper word) (FMC_DATAW1S6U) 0000_0000h 27.4.11/ 4001_F274 Cache Data Storage (lower word) (FMC_DATAW1S6L) 0000_0000h Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 514 4001_F2C4 Cache Data Storage (lower word) (FMC_DATAW3S0L) 0000_0000h 27.4.14/ 4001_F2C8 Cache Data Storage (upper word) (FMC_DATAW3S1U) 0000_0000h 27.4.15/ 4001_F2CC Cache Data Storage (lower word) (FMC_DATAW3S1L) 0000_0000h Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 515 4001_F2FC Cache Data Storage (lower word) (FMC_DATAW3S7L) 0000_0000h 27.4.1 Flash Access Protection Register (FMC_PFAPR) Address: 4001_F000h base + 0h offset = 4001_F000h Reserved Reset M7AP[1:0] M6AP[1:0] M5AP[1:0] M4AP[1:0] M3AP[1:0] M2AP[1:0] M1AP[1:0] M0AP[1:0] Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 516 This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits. Prefetching for this master is enabled. Prefetching for this master is disabled. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 517 No access may be performed by this master Only read accesses may be performed by this master Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 518 Only read accesses may be performed by this master Only write accesses may be performed by this master Both read and write accesses may be performed by this master K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 519 Cache way is unlocked and may be displaced Cache way is locked and its contents are not displaced 23–20 Cache Invalidate Way x CINV_WAY[3:0] Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 520 Do not cache data references. Cache data references. Bank 0 Instruction Cache Enable B0ICE This bit controls whether instruction fetches are loaded into the cache. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 521 1's cache. A high-to-low transition of this enable forces the page buffer to be invalidated. Single entry buffer is disabled. Single entry buffer is enabled. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 522 This read-only field is reserved and always has the value 0. 18–17 Bank 1 Memory Width B1MW[1:0] This read-only field defines the width of the bank 1 memory. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 523 0's cache. A high-to-low transition of this enable forces the page buffer to be invalidated. Single entry buffer is disabled. Single entry buffer is enabled. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 524 14-bit tag for cache entry tag[18:5] 4–1 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 1-bit valid for cache entry valid K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 525 14-bit tag for cache entry tag[18:5] 4–1 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 1-bit valid for cache entry valid K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 526 14-bit tag for cache entry tag[18:5] 4–1 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 1-bit valid for cache entry valid K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 527 This section represents data for the upper word (bits [63:32]) of all sets in the indicated way. Address: 4001_F000h base + 200h offset + (8d × i), where i=0d to 7d data[63:32] Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 528 This section represents data for the upper word (bits [63:32]) of all sets in the indicated way. Address: 4001_F000h base + 240h offset + (8d × i), where i=0d to 7d data[63:32] Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 529 This section represents data for the upper word (bits [63:32]) of all sets in the indicated way. Address: 4001_F000h base + 280h offset + (8d × i), where i=0d to 7d data[63:32] Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 530 This section represents data for the upper word (bits [63:32]) of all sets in the indicated way. Address: 4001_F000h base + 2C0h offset + (8d × i), where i=0d to 7d data[63:32] Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 531: Functional Description
27.5.1 Default configuration Upon system reset, the FMC is configured to provide a significant level of buffering for transfers from the flash memory: K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 532: Configuration Options
0, while the single-entry buffer can be enabled for bank 1 only. This configuration is ideal for applications that use bank 0 for program space and bank 1 for data space. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 533: Speculative Reads
4. Reading the fourth longword, like the second longword, takes only 1 clock due to the 64-bit flash memory data bus. 27.6 Initialization and application information The FMC does not require user initialization. Flash acceleration features are enabled by default. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 534 FMC's cache might need to be disabled and/or flushed to prevent the possibility of returning stale data. Use the PFB0CR[CINV_WAY] field to invalidate the cache in this manner. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 535: Chapter 28 Flash Memory Module (Ftfa)
('1') states and/or programmed ('0') states. Therefore, it is recommended that each flash block or sector be re-erased immediately prior to factory programming to ensure that the full data retention capability is achieved. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 536: Program Flash Memory Features
• Supports MCU security mechanisms which prevent unauthorized access to the flash memory contents 28.1.2 Block Diagram The block diagram of the flash memory module is shown in the following figure. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 537 Longword — 32 bits of data with an aligned longword having byte-address[1:0] = 00. NVM — Nonvolatile memory. A memory technology that maintains stored data during power-off. The flash array is an NVM using NOR-type flash memory technology. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 538: External Signal Description
This section describes the memory map and registers for the flash memory module. Data read from unimplemented memory space in the flash memory module is undefined. Writes to unimplemented or reserved memory space (registers) in the flash memory module are ignored. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 539: Flash Configuration Field Description
0x00 – 0x9F Reserved 0xA0 – 0xA3 Program Once XACCH-1 Field (index = 0x10) 0xA4 – 0xA7 Program Once XACCL-1 Field (index = 0x10) Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 540: Program Once Field
CCIF. During this initialization period the user may write any register. All register writes are also disabled (except for registers FCNFG and FSTAT) whenever an erase suspend request is active (FCNFG[ERSSUSP]=1). K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 541 Undefined 28.33.6/ 4002_0013 Program Flash Protection Registers (FTFA_FPROT0) Undefined 28.33.7/ 4002_0018 Execute-only Access Registers (FTFA_XACCH3) Undefined 28.33.7/ 4002_0019 Execute-only Access Registers (FTFA_XACCH2) Undefined Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 542 MGSTAT0 bit is read only. The unassigned bits read 0 and are not writable. NOTE When set, the Access Error (ACCERR) and Flash Protection Violation (FPVIOL) bits in this register prevent the launch of K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 543 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Memory Controller Command Completion Status Flag MGSTAT0 Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 544 ERSAREQ sets when an erase all request is triggered external to the flash memory module and CCIF is set (no command is currently being executed). ERSAREQ is cleared by the flash memory module when the operation completes. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 545 = Undefined at reset. FTFA_FSEC field descriptions Field Description 7–6 Backdoor Key Security Enable KEYEN Enables or disables backdoor key access to the flash memory module. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 546 NVM at reset. The function of the bits is defined in the device's Chip Configuration details. All bits in the register are read-only . K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 547 FCCOB parameter fields and they cannot be changed by the user until the command completes (CCIF returns to 1). No command buffering or queueing is provided; the next command can be loaded only after the current command completes. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 548 KB of program flash where each assigned bit protects 1 KB . For configurations with 24 KB of program flash memory or less, FPROT0 is not used. For configurations with 16 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 549 1 and protected regions use a 0, only writes changing 1s to 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with 0-to-1 transitions are ignored. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 550 Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 551 SACCL3 SA[7:0] During the reset sequence, the SACC registers are loaded with the logical AND of Program Flash IFR addresses A and B as indicated in the following table. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 552 All bits in the register are read-only. The contents of this register are loaded during the reset sequence. Address: 4002_0000h base + 28h offset = 4002_0028h Read SGSIZE Write Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 553 Number of Segments Indicator NUMSG The NUMSG field indicates the number of equal-sized segments in the program flash. 0x20 Program flash memory is divided into 32 segments (64 Kbytes, 128 Kbytes) K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 554: Functional Description
FPROT0[PROT31] Last program flash address Figure 28-44. Program flash protection NOTE Flash protection features are discussed further in AN4507: Using the Kinetis Security and Flash Protection Features . Not K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 555: Flash Access Protection
Figure 28-45. Program flash access control (64KB or 128KB of program flash) • FSACC — • For 2 program flash sizes 128KB or less, four registers control 32 segments of the program flash memory as shown in the following figure K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 556 Some devices also generate a bus error response as a result of a Read Collision Error event. See the chip configuration information to determine if a bus error response is also supported. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 557: Flash Operation In Low-Power Modes
Chip Configuration details of this device for how to activate each mode. 28.4.6 Flash Reads and Ignored Writes The flash memory module requires only the flash address to execute a flash memory read. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 558: Read While Write (Rww)
Flash commands are specified using a command write sequence illustrated in Figure 28-47. The flash memory module performs various checks on the command (FCCOB) content and continues with command execution if all requirements are fulfilled. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 559: Load The Fccob Registers
Program and erase commands also check the address to determine if the operation is requested to execute on protected areas. If the protection check fails, FSTAT[FPVIOL] (protection error) flag is set. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 560 More Parameters? Clear the CCIF to launch the command Write 0x80 to FSTAT register EXIT Figure 28-47. Generic flash command write sequence flowchart K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 561: Flash Commands
28.4.9.3 Flash Commands by Mode The following table shows the flash commands that can be executed in each flash operating mode. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 562: Margin Read Commands
The 'user' and 'factory' levels become, in effect, a minimum safety margin; i.e. if the reads pass at the tighter tolerances of the 'user' and 'factory' margins, then the 'normal' reads have at least this much safety margin before they experience data loss. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 563: Flash Command Description
MCU with the collision error flag (FSTAT[RDCOLERR]) set. CAUTION Flash data must be in the erased state before being programmed. Cumulative programming of bits (adding more zeros) is not allowed. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 564: Read 1S Section Command
An invalid flash address is supplied. FSTAT[ACCERR] Flash address is not phrase aligned. FSTAT[ACCERR] The requested section crosses a Flash block boundary. FSTAT[ACCERR] The requested number of phrases is 0. FSTAT[ACCERR] Read-1s fails. FSTAT[MGSTAT0] K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 565: Program Check Command
Table 28-50. Margin Level Choices for Program Check Read Margin Choice Margin Level Description 0x01 Read at 'User' margin-1 and 'User' margin-0 0x02 Read at 'Factory' margin-1 and 'Factory' margin-0 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 566: Read Resource Command
Resource Size Local Address Range Select Code 0x00 Program Flash 0 IFR 256 Bytes 0x00_0000–0x00_00FF 0x01 Version ID 8 Bytes 0x00_0000–0x00_0007 1. Located in program flash 0 reserved space. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 567: Program Longword Command
Flash address [7:0] Byte 0 program value Byte 1 program value Byte 2 program value Byte 3 program value 1. Must be longword aligned (Flash address [1:0] = 00). K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 568: Erase Flash Sector Command
Flash address [15:8] in the flash sector to be erased Flash address [7:0] in the flash sector to be erased 1. Must be phrase aligned (flash address [2:0] = 000). K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 569: Suspending An Erase Flash Sector Operation
CCIF and leaves the ERSSUSP bit set. While CCIF is set, the ERSSUSP bit can only be cleared to prevent the withdrawal of a suspend request before the flash memory module has acknowledged it. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 570: Resuming A Suspended Erase Flash Sector Operation
Data in this sector is not reliable until a new erase command fully completes. The following figure shows how to suspend and resume the Erase Flash Sector operation. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 571 ERSSCR Suspended Resume Erase? ERSSUSP: Bit in FCNFG register No, Abort SUSPACK: Internal Suspend Acknowledge Clear ERSSUSP User Cmd Interrupt/Suspend Figure 28-48. Suspend and Resume of Erase Flash Sector Operation K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 572: Read 1S All Blocks Command
Apply the 'Factory' margin to the normal read-1 level Table 28-61. Read 1s All Blocks Command Error Handling Error Condition Error Bit An invalid margin choice is specified FSTAT[ACCERR] Read-1s fails FSTAT[MGSTAT0] K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 573: Read Once Command
The Read Once command can be executed any number of times. Table 28-63. Read Once Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid record index is supplied FSTAT[ACCERR] K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 574: Program Once Command
Command not available in current mode/security FSTAT[ACCERR] An invalid record index is supplied FSTAT[ACCERR] The requested record has already been programmed to a non-FFFF value FSTAT[ACCERR] Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 575: Erase All Blocks Command
Error Bit Command not available in current mode/security FSTAT[ACCERR] Any region of the program flash memory is protected FSTAT[FPVIOL] Any errors have been encountered during the verify operation FSTAT[MGSTAT0] K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 576: Triggering An Erase All External To The Flash Memory Module
Key Byte 1 0x0_0002 Key Byte 2 0x0_0001 Key Byte 3 0x0_0000 Key Byte 4 0x0_0007 Key Byte 5 0x0_0006 Key Byte 6 0x0_0005 Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 577 Flash Configuration Field (see Flash Configuration Field Description). The following fields are available in the FSEC register. The settings are described in the Flash Security Register (FTFA_FSEC) details. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 578: Flash Memory Access By Mode And Security
8-byte backdoor key value stored in the Flash Configuration Field (see Flash Configuration Field Description). If the FSEC[KEYEN] bits are in the enabled state, the Verify Backdoor Access Key command (see Verify K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 579: Reset Sequence
28.4.13 Reset Sequence On each system reset the flash memory module executes a sequence which establishes initial values for the flash block configuration parameters, FPROT, FOPT, and FSEC registers. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 580 If a reset occurs while any flash command is in progress, that command is immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. Commands and operations do not automatically resume after exiting reset. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 581: Chapter 29 Cyclic Redundancy Check (Crc)
• Option for inversion of final CRC result • 32-bit CPU register programming interface 29.1.2 Block diagram The following is a block diagram of the CRC. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 582: Modes Of Operation
Register name Access Reset value (in bits) page (hex) 4003_2000 CRC Data register (CRC_DATA) FFFF_FFFFh 29.2.1/583 4003_2004 CRC Polynomial register (CRC_GPOLY) 0000_1021h 29.2.2/584 4003_2008 CRC Control register (CRC_CTRL) 0000_0000h 29.2.3/584 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 583 When CTRL[WAS] is 1, values written to this field are part of the seed value. When CTRL[WAS] is 0, data written to this field is used for CRC checksum generation. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 584 CRC calculation. A new CRC calculation is initialized by asserting CTRL[WAS] and then writing the seed into the CRC data register. Address: 4003_2000h base + 8h offset = 4003_2008h TOTR FXOR WAS Reset Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 585: Functional Description
Width of CRC protocol. TCRC 16-bit CRC protocol. 32-bit CRC protocol. 23–0 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 29.3 Functional description K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 586: Crc Initialization/Reinitialization
8. When all values have been written, read the final CRC result from CRC_DATA[LU:LL]. Transpose and complement operations are performed on the fly while reading or writing values. See Transpose feature CRC result complement for details. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 587: Transpose Feature
CTRL[TOT] or CTRL[TOTR] fields, according to the CRC calculation being used. The following types of transpose functions are available for writing to and reading from the CRC data register: 1. CTRL[TOT] or CTRL[TOTR] is 00. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 588 = {reg[0:7], reg[8:15],reg[16:23], reg[24:31]} Figure 29-6. Transpose type 10 4. CTRL[TOT] or CTRL[TOTR] is 11. Bytes are transposed, but bits are not transposed. reg[31:0] becomes {reg[7:0], reg[15:8], reg[23:16], reg[31:24]} K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 589: Crc Result Complement
CRC data register every time the CRC data register is read. When CTRL[FXOR] is cleared, reading the CRC data register accesses the raw checksum value. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 590 Functional description K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 591: Chapter 30 Analog-To-Digital Converter (Adc)
• Output format in 2's complement 16-bit sign extended for differential modes • Output in right-justified unsigned format for single-ended • Single or continuous conversion, that is, automatic return to idle after single conversion K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 592 • Temperature sensor • Hardware average function • Selectable voltage reference: external or alternate • Self-Calibration mode 30.1.2 Block diagram The following figure is the ADC module block diagram. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 593: Adc Signal Descriptions
Each differential pair requires two inputs, DADPx and DADMx. The ADC also requires four supply/reference/ground connections. NOTE Refer to ADC configuration section in chip configuration chapter for the number of channels supported on this device. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 594: Analog Power
ALTL depending on MCU configuration. See the chip configuration information on the Voltage References specific to this MCU. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 595: Analog Channel Inputs (Adx)
30.3.4/602 4003_B014 ADC Data Result Register (ADC0_RB) 0000_0000h 30.3.4/602 4003_B018 Compare Value Registers (ADC0_CV1) 0000_0000h 30.3.5/603 4003_B01C Compare Value Registers (ADC0_CV2) 0000_0000h 30.3.5/603 Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 596 To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC can have more than one status and control register: one for each conversion. The SC1B–SC1n registers indicate potentially multiple SC1 registers for use only in hardware K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 597 Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Conversion Complete Flag COCO Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 598 When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved. 01011 When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 599 The configuration Register 1 (CFG1) selects the mode of operation, clock source, clock divide, and configuration for low power or long sample time. Address: 4003_B000h base + 8h offset = 4003_B008h Reset ADIV MODE ADICLK Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 600 In this case, there is an associated clock startup delay each time the clock source is re-activated. Bus clock Alternate clock 2 (ALTCLK2) Alternate clock (ALTCLK) Asynchronous clock (ADACK) K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 601 Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active. Asynchronous clock and clock output is enabled regardless of the state of the ADC. High-Speed Configuration ADHSC Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 602 16-bit single- Unsigned right ended justified 13-bit differential S Sign-extended 2's complement 12-bit single- Unsigned right- ended justified 11-bit differential S Sign-extended 2's complement Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 603 Therefore, the compare function uses only the CVn fields that are related to the ADC mode of operation. The compare value 2 register (CV2) is used only when the compare range function is enabled, that is, SC2[ACREN]=1. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 604 The status and control register 2 (SC2) contains the conversion active, hardware/software trigger select, compare function, and voltage reference select of the ADC module. Address: 4003_B000h base + 20h offset = 4003_B020h Reset REFSEL Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 605 REFSEL Selects the voltage reference source used for conversions. Default voltage reference pin pair, that is, external pins V and V REFH REFL Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 606 Reset ADCx_SC3 field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 607 Hardware Average Select AVGS Determines how many ADC conversions will be averaged to create the ADC average result. 4 samples averaged. 8 samples averaged. 16 samples averaged. 32 samples averaged. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 608 ADPG15 and ADPG14. This register must be written by the user with the value described in the calibration procedure. Otherwise, the gain error specifications may not be met. Address: 4003_B000h base + 2Ch offset = 4003_B02Ch Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 609 CLP4[9:0], CLPS[5:0], and CLPD[5:0]. CLPx are automatically set when the self- calibration sequence is done, that is, CAL is cleared. If these registers are written by the user after calibration, the linearity error specifications may not be met. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 610 Calibration Value CLPS Calibration Value 30.3.13 ADC Plus-Side General Calibration Value Register (ADCx_CLP4) For more information, see CLPD register description. Address: 4003_B000h base + 3Ch offset = 4003_B03Ch CLP4 Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 611 Reset ADCx_CLP2 field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 612 Reset ADCx_CLP0 field descriptions Field Description 31–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 5–0 Calibration Value CLP0 Calibration Value K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 613 Reset ADCx_CLMS field descriptions Field Description 31–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 5–0 Calibration Value CLMS Calibration Value K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 614 Reset ADCx_CLM3 field descriptions Field Description 31–9 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 8–0 Calibration Value CLM3 Calibration Value K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 615 Reset ADCx_CLM1 field descriptions Field Description 31–7 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 6–0 Calibration Value CLM1 Calibration Value K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 616: Functional Description
The ADC module has the capability of automatically comparing the result of a conversion with the contents of the CV1 and CV2 registers. The compare function is enabled by setting SC2[ACFE] and operates in any of the conversion modes and configurations. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 617: Clock Select And Divide Control
If the available clocks are too fast, the clock must be divided to the appropriate frequency. This divider is specified by CFG1[ADIV] and can be divide-by 1, 2, 4, or 8. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 618: Voltage Reference Selection
ADHWT signal to trigger a new conversion. The channel and status fields selected for the conversion depend on the active trigger select signal: • ADHWTSA active selects SC1A. • ADHWTSn active selects SC1n. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 619: Conversion Control
SC2[ADTRG]=1, and a hardware trigger select event, ADHWTSn, has occurred. The channel and status fields selected depend on the active trigger select signal: • ADHWTSA active selects SC1A. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 620: Completing Conversions
SC1n[COCO] sets only if the last of the selected number of conversions is completed and the compare condition is true. An interrupt is generated if the respective SC1n[AIEN] is high at the time that the respective SC1n[COCO] is set. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 621: Aborting Conversions
CFG2[ADACKEN]=1, it remains active regardless of the state of the ADC or the MCU power mode. Power consumption when the ADC is active can be reduced by setting CFG1[ADLPC]. This results in a lower maximum value for f ADCK K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 622: Sample Time And Total Conversion Time
3. The result of the conversion is transferred to Rn upon completion of the conversion algorithm. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 623 27 ADCK cycles 10b single-ended 20 ADCK cycles 11b differential 30 ADCK cycles 12b single-ended 20 ADCK cycles 13b differential 30 ADCK cycles Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 624: Conversion Time Examples
• 10-bit mode, with the bus clock selected as the input clock source • The input clock divide-by-1 ratio selected • Bus frequency of 8 MHz • Long sample time disabled • High-speed conversion disabled K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 625: Long Conversion Time Configuration
Figure 30-62. Table 30-76. Typical conversion time Variable Time SFCAdder 3 ADCK cycles + 5 bus clock cycles AverageNum 34 ADCK cycles LSTAdder 20 ADCK cycles HSCAdder K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 626: Short Conversion Time Configuration
When hardware averaging is selected, the completion of a single conversion will not set SC1n[COCO]. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 627: Automatic Compare Function
CV2. Greater than Outside range, inclusive Compare true if the result is greater than or equal to CV1 Or the result is less than or equal to CV2. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 628: Calibration Function
Prior to calibration, the user must configure the ADC's clock source and frequency, low power configuration, voltage reference selection, sample time, and high speed configuration according to the application's clock source availability and needs. If the K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 629 When calibration is complete, the user may reconfigure and use the ADC as desired. A second calibration may also be performed, if desired, by clearing and again setting SC3[CAL]. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 630: User-Defined Offset Function
ADC error specifications may not be met. Storing the value generated by the calibration function in memory before overwriting with a user- specified value is recommended. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 631: Temperature Sensor
• m is referred as temperature sensor slope in the device data sheet. It is the hot or cold voltage versus temperature slope in V/°C. For temperature calculations, use the V and temperature sensor slope values from TEMP25 the ADC Electricals table. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 632: Mcu Wait Mode Operation
30.4.10 MCU Normal Stop mode operation Stop mode is a low-power consumption Standby mode during which most or all clock sources on the MCU are disabled. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 633: Normal Stop Mode With Bus Clock Selected
Therefore, the module must be re-enabled and re-configured following exit from Low-Power Stop mode. NOTE For the chip specific modes of operation, see the power management information for the device. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 634: Initialization Information
5. Update SC1:SC1n registers to select whether conversions will be single-ended or differential and to enable or disable conversion complete interrupts. Also, select the input channel which can be used to perform conversions. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 635: Pseudo-Code Example
Bit 4:0 ADCH 00001 Input channel 1 selected as ADC input channel. RA = 0xxx Holds results of conversion. CV = 0xxx Holds compare value when compare function enabled. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 636: Application Information
30.6.1 External pins and routing 30.6.1.1 Analog supply pins Depending on the device, the analog power and ground supplies, V and V , of the ADC module are available as: K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 637: Analog Voltage Reference Pins
V and V loop. The REFH REFL best external component to meet this current demand is a 0.1 μF capacitor with good K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 638: Analog Input Pins
RAS + RADIN =SC / (FMAX * NUMTAU * CADIN) Figure 30-65. Sampling equation Where: RAS = External analog source resistance SC = Number of ADCK cycles used during sample window K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 639: Pin Leakage Error
REFL plane. • Operate the MCU in Wait or Normal Stop mode before initiating (hardware-triggered conversions) or immediately after initiating (hardware- or software-triggered conversions) the ADC conversion. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 640: Code Width And Quantization Error
12-bit modes. As a consequence, however, the code width of the first (0x000) conversion is only 1/2 LSB and the code width of the last (0xFF or 0x3FF) is 1.5 LSB. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 641: Linearity Errors
However, even small amounts of system noise can cause the converter to be indeterminate, between two codes, for a range of input voltages around the transition voltage. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 642 • Missing codes: Missing codes are those values never converted for any input value. In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and have no missing codes. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 643: Chapter 31 Comparator (Cmp)
31.1.1 CMP features The CMP has the following features: • Operational over the entire supply range • Inputs may range from rail to rail • Programmable hysteresis control K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 644: 6-Bit Dac Key Features
• 6-bit resolution • Selectable supply reference source • Power Down mode to conserve power when not in use • Option to route the output to internal comparator input K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 645: Anmux Key Features
• Two 8-to-1 channel mux • Operational over the entire supply range 31.1.4 CMP, DAC and ANMUX diagram The following figure shows the block diagram for the High-Speed Comparator, DAC, and ANMUX modules. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 646: Cmp Block Diagram
ANMUX and filter control CMPO MSEL[2:0] Figure 31-1. CMP, DAC and ANMUX block diagram 31.1.5 CMP block diagram The following figure shows the block diagram for the CMP module. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 647 CR0[FILTER_CNT] is set greater than 0x01. • If CR1[SE] = 1, the external SAMPLE input is used as sampling clock • If CR1[SE] = 0, the divided bus clock is used as sampling clock K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 648 Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. 6–4 Filter Sample Count FILTER_CNT Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 649 WE is cleared. However, avoid writing 1s to both field locations because this "11" case is reserved and may change in future implementations. Sampling mode is not selected. Sampling mode is selected. Windowing Enable Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 650 When the user selects the same input from analog mux to the positive and negative port, the comparator is disabled automatically. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 651 Enables the DMA transfer triggered from the CMP module. When this field is set, a DMA request is asserted when CFR or CFF is set. DMA is disabled. DMA is enabled. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 652 CMPx_DACCR field descriptions Field Description DAC Enable DACEN Enables the DAC. When the DAC is disabled, it is powered down to conserve power. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 653 MSEL Determines which input is selected for the minus input of the comparator. For INx inputs, see CMP, DAC, and ANMUX block diagrams. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 654: Functional Description
The external sample input is enabled using CR1[SE]. When set, the output of the comparator is sampled only on rising edges of the sample input. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 655 SAMPLE=1 to generate COUTA, which is then resampled and filtered to generate COUT. See the Windowed/Filtered mode (#7). All other combinations of CR1[EN], CR1[WE], CR1[SE], CR0[FILTER_CNT], and FPR[FILT_PER] are illegal. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 656 CMPO COUT To other system functions WINDOW/SAMPLE bus clock Clock COUTA CMPO to prescaler divided FILT_PER CGMUX clock Figure 31-21. Comparator operation in Continuous mode K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 657 In Sampled, Non-Filtered mode, the analog comparator block is powered and active. The path from analog inputs to COUTA is combinational unclocked. Windowing control is completely bypassed. COUTA is sampled whenever a rising-edge is detected on the filter block clock input. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 658 COUTA is sampled whenever a rising edge is detected on the filter block clock input. The only difference in operation between Sampled, Non-Filtered (# 3A) and Sampled, Filtered (# 4A) is that, now, CR0[FILTER_CNT]>1, which activates filter operation. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 659 CMPO COUT To other SOC functions WINDOW/SAMPLE bus clock Clock COUTA CMPO to prescaler divided FILT_PER CGMUX clock SE=1 Figure 31-24. Sampled, Filtered (# 4A): sampling point externally driven K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 660 WINDOW signal is high. In actual operation, COUTA may lag the analog inputs by up to one bus clock cycle plus the combinational path delay through the comparator and polarity select logic. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 661 COUTA CMPO to divided prescaler FILT_PER CGMUX clock SE=0 Figure 31-27. Windowed mode For control configurations which result in disabling the filter block, see Filter Block Bypass Logic diagram. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 662 Configuration for this mode is virtually identical to that for the Windowed/Filtered Mode shown in the next section. The only difference is that the value of CR0[FILTER_CNT] must be 1. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 663: Power Modes
Figure 31-29. Windowed/Filtered mode 31.3.2 Power modes 31.3.2.1 Wait mode operation During Wait and VLPW modes, the CMP, if enabled, continues to operate normally and a CMP interrupt can wake the MCU. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 664: Stop Mode Operation
The filter delay is specified in the Low-pass filter. • During operation, the propagation delay of the selected data paths must always be considered. It may take many bus clock cycles for COUT and SCR[CFR]/SCR[CFF] K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 665: Low Pass Filter
In other words, SCR[COUT] will be 0 for some initial period, even when COUTA is at logic 1. Setting both CR1[SE] and FPR[FILT_PER] to 0 disables the filter and eliminates switching current associated with the filtering process. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 666: Latency Issues
Sampled, Filtered mode + (CR0[FILTER_CNT] * ) + T SAMPLE > 0x01 > 0x00 + (CR0[FILTER_CNT] * FPR[FILT_PER] x T ) + T Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 667: Cmp Interrupts
DMA transfer request and clears the flag to allow a subsequent change on comparator output to occur and force another DMA request. The comparator can remain functional in STOP modes. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 668: Cmp Asynchronous Dma Support
STOP modes. After the data transfer has finished, system will go back to STOP modes. Refer to DMA chapters in the device reference manual for the asynchronous DMA function for details. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 669: Digital-To-Analog Converter
31.8.1 Voltage reference source select • V connects to the primary voltage source as supply reference of 64 tap resistor ladder • V connects to an alternate voltage source K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 670: Dac Resets
This module has a single reset input, corresponding to the chip-wide peripheral reset. 31.10 DAC clocks This module has a single clock input, the bus clock. 31.11 DAC interrupts This module has no interrupts. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 671: Block Diagram
• Static operation in Normal Stop mode • 16-word data buffer supported with configurable watermark and multiple operation modes • DMA support 32.3 Block diagram The block diagram of the DAC module is as follows: K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 672: Memory Map/Register Definition
DACBBIEN DACBFMD DACTRGSE Figure 32-1. DAC block diagram 32.4 Memory map/register definition The DAC has registers to control analog comparator and programmable voltage divider to perform the digital-to-analog functions. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 673 DAC Data High Register (DAC0_DAT15H) 32.4.2/674 4003_F020 DAC Status Register (DAC0_SR) 32.4.3/675 4003_F021 DAC Control Register (DAC0_C0) 32.4.4/676 4003_F022 DAC Control Register 1 (DAC0_C1) 32.4.5/677 4003_F023 DAC Control Register 2 (DAC0_C2) 32.4.6/678 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 674 When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage based on the following formula. V * (1 + DACDAT0[11:0])/4096 When the DAC buffer is enabled, DATA[11:0] is mapped to the 16-word buffer. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 675 DAC trigger making the DAC read pointer increase. Write to this bit is ignored in FIFO mode. The DAC buffer read pointer is not equal to C2[DACBFUP]. The DAC buffer read pointer is equal to C2[DACBFUP]. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 676 The DAC buffer read pointer top flag interrupt is disabled. The DAC buffer read pointer top flag interrupt is enabled. DAC Buffer Read Pointer Bottom Flag Interrupt Enable DACBBIEN Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 677 Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 678: Dac Data Buffer Operation
When both the DAC and the buffer are enabled, the DAC converts the data in the data buffer to analog output voltage. The data buffer read pointer advances to the next word whenever any hardware or software trigger event occurs. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 679: Dac Data Buffer Interrupts
NOTE: If the software set the read pointer to the upper limit, the read pointer will not advance in this mode. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 680: Dma Operation
The status register flags are still set and are cleared automatically when the DMA completes. 32.5.3 Resets During reset, the DAC is configured in the default mode and is disabled. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 681: Low-Power Mode Operation
In low-power stop modes, the DAC is fully shut down. NOTE The assignment of module modes to core modes is chip- specific. For module-to-core mode assignments, see the chapter that describes how modules are configured. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 682 Functional description K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 683: Chapter 33 Voltage Reference (Vrefv1)
ADC, DAC, or CMP. The voltage reference has three operating modes that provide different levels of supply rejection and power consumption.. The following figure is a block diagram of the Voltage Reference. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 684 The Voltage Reference has the following features: • Programmable trim register with 0.5 mV steps, automatically loaded with factory trimmed value upon reset • Programmable buffer mode selection: • Off K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 685: Modes Of Operation
The following table shows the Voltage Reference signals properties. Table 33-1. VREF Signal Descriptions Signal Description VREF_OUT Internally-generated Voltage Reference output NOTE When the VREF output buffer is disabled, the status of the VREF_OUT signal is high-impedence. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 686: Memory Map And Register Definition
NOTE: Min = minimum and max = maximum voltage reference output. For minimum and maximum voltage reference output values, refer to the Data Sheet for this chip. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 687 Internal 1.75 V regulator is enabled. Second order curvature compensation enable ICOMPEN This bit should be written to 1 to achieve the performance stated in the data sheet. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 688 100 nF capacitor is required. Voltage Reference enabled, VREF_OUT available for low power buffer on internal and external use. 100 nF capacitor is required. Reserved Reserved K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 689 (Tstup) and the value is specified in the appropriate device data sheet. If this mode is entered when the VREF module is enabled then you must wait the longer of K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 690: Internal Voltage Regulator
1. Enable the chop oscillator (VREF_TRM[CHOPEN] = 1) 2. Configure the VREF_SC register to the desired settings with the internal regulator disabled, VREF_SC[REGEN] = 0 3. Wait > 300ns K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 691 The TRM[CHOPEN], SC[REGEN] and SC[ICOMPEN] bits must be written to 1 to achieve the performance stated in the device data sheet. NOTE See section "Internal voltage regulator" for details on the required sequence to enable the internal regulator. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 692 Initialization/Application Information K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 693: Chapter 34 Programmable Delay Block (Pdb)
• Trigger outputs can be enabled or disabled independently • One 16-bit delay register per pre-trigger output • Optional bypass of the delay registers of the pre-trigger outputs • Operation in One-Shot or Continuous modes K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 694 • y—Pulse-Out number, valid value is from 0 to Y-1. NOTE The number of module output triggers to core is chip-specific. For module to core output triggers implementation, see the chip configuration information. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 695: Back-To-Back Acknowledgment Connections
34.1.4 DAC External Trigger Input Connections The implementation of DAC external trigger inputs is chip-specific. See the chip configuration information for details. 34.1.5 Block diagram This diagram illustrates the major components of the PDB. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 696 In this diagram, only one PDB channel n, one DAC interval trigger x, and one Pulse-Out y are shown. The PDB-enabled control logic and the sequence error interrupt logic are not shown. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 697: Pdb Signal Descriptions
If the PDB is enabled and external trigger input source is selected, a positive edge on the EXTRG signal resets and starts the counter. 34.3 Memory map and register definition K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 698 DAC Interval n register (PDB0_DACINT0) 0000_0000h 34.3.11/ 4003_6190 Pulse-Out n Enable register (PDB0_POEN) 0000_0000h 34.3.12/ 4003_6194 Pulse-Out n Delay register (PDB0_PO0DLY) 0000_0000h 34.3.12/ 4003_6198 Pulse-Out n Delay register (PDB0_PO1DLY) 0000_0000h K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 699 Enables the PDB sequence error interrupt. When this field is set, any of the PDB channel sequence error flags generates a PDB sequence error interrupt. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 700 Trigger-In 11 is selected. 1100 Trigger-In 12 is selected. 1101 Trigger-In 13 is selected. 1110 Trigger-In 14 is selected. 1111 Software trigger is selected. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 701 1. It is automatically cleared when the values in buffers are loaded into the internal registers or the PDBEN is cleared. Writing 0 to it has no effect. 34.3.2 Modulus register (PDBx_MOD) Address: 4003_6000h base + 4h offset = 4003_6004h Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 702 Specifies the delay value to schedule the PDB interrupt. It can be used to schedule an independent interrupt at some point in the PDB cycle. If enabled, a PDB interrupt is generated, when the counter is Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 703 PDB Channel Pre-Trigger Enable These bits enable the PDB ADC pre-trigger outputs. Only lower M pre-trigger bits are implemented in this MCU. PDB channel's corresponding pre-trigger disabled. PDB channel's corresponding pre-trigger enabled. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 704 Specifies the delay value for the channel's corresponding pre-trigger. The pre-trigger asserts when the counter is equal to DLY. Reading this field returns the value of internal register that is effective for the current PDB cycle. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 705 1. DAC external trigger input enabled. DAC interval counter is bypassed and DAC external trigger input triggers the DAC interval trigger. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 706 This read-only field is reserved and always has the value 0. 7–0 PDB Pulse-Out Enable POEN Enables the pulse output. Only lower Y bits are implemented in this MCU. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 707: Functional Description
1. For each channel, a delay m determines the time between assertion of the trigger input event to the time at which changes in the pre-trigger m output signal are started. The time is defined as: K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 708 2 peripheral cycles after the acknowledgment m is received. The acknowledgment connections in this MCU are described in Back-to-back acknowledgment connections. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 709: Pdb Trigger Input Source Selection
PDB can generate pulse outputs of configurable width. When PDB counter reaches the value set in POyDLY[DLY1], the Pulse-Out goes high; when the counter reaches POyDLY[DLY2], it goes low. POyDLY[DLY2] can be set either greater or less than POyDLY[DLY1]. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 710: Updating The Delay Registers
The following diagrams show the cases of the internal registers being updated with SC[LDMOD] is 00 and x1. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 711 SC[PDBEIE] = 1 34.4.6 DMA If SC[DMAEN] is set, PDB can generate a DMA transfer request when SC[PDBIF] is set. When DMA is enabled, the PDB interrupt is not issued. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 712: Application Information
If the applications need a really long delay value and use a prescaler set to 128, then the resolution would be limited to 128 peripheral clock cycles. Therefore, use the lowest possible prescaler and multiplication factor for a given application. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 713: Chapter 35 Flextimer Module (Ftm)
All of the features common with the TPM have fully backwards compatible register assignments. The FlexTimer can also use code on the same core platform without change to perform the same functions. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 714 • It can be a free-running counter or a counter with initial and final value • The counting can be up or up-down • Each channel can be configured for input capture, output compare, or edge-aligned PWM mode • In Input Capture mode: K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 715: Modes Of Operation
FTM is effectively disabled until clocks resume. During Wait mode, the FTM continues to operate normally. If the FTM does not need to produce a K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 716: Block Diagram
The following figure shows the FTM structure. The central component of the FTM is the 16-bit counter with programmable initial and final values and its counting can be up or up-down. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 717 7 mode logic input DECAPEN CH7F channel 7 COMBINE3 channel 7 interrupt CPWMS CH7TRIG match trigger CH7IE MS7B:MS7A ELS7B:ELS7A Figure 35-1. FTM block diagram K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 718: Ftm Signal Descriptions
This section presents a high-level summary of the FTM registers and how they are mapped. The registers and bits of an unavailable function in the FTM remain in the memory map and in the reset value, but they have no active function. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 719 Features Mode Selection (FTM0_MODE) 0000_0004h 35.3.11/ 4003_8058 Synchronization (FTM0_SYNC) 0000_0000h 35.3.12/ 4003_805C Initial State For Channels Output (FTM0_OUTINIT) 0000_0000h 35.3.13/ 4003_8060 Output Mask (FTM0_OUTMASK) 0000_0000h Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 720 4003_902C Channel (n) Status And Control (FTM1_C4SC) 0000_0000h 35.3.6/727 4003_9030 Channel (n) Value (FTM1_C4V) 0000_0000h 35.3.7/730 4003_9034 Channel (n) Status And Control (FTM1_C5SC) 0000_0000h 35.3.6/727 Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 721 0000_0000h 35.3.24/ 4003_908C Synchronization Configuration (FTM1_SYNCONF) 0000_0000h 35.3.25/ 4003_9090 FTM Inverting Control (FTM1_INVCTRL) 0000_0000h 35.3.26/ 4003_9094 FTM Software Output Control (FTM1_SWOCTRL) 0000_0000h 35.3.27/ 4003_9098 FTM PWM Load (FTM1_PWMLOAD) 0000_0000h K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 722 4003_A06C FTM External Trigger (FTM2_EXTTRIG) 0000_0000h 35.3.17/ 4003_A070 Channels Polarity (FTM2_POL) 0000_0000h 35.3.18/ 4003_A074 Fault Mode Status (FTM2_FMS) 0000_0000h 35.3.19/ 4003_A078 Input Capture Filter Control (FTM2_FILTER) 0000_0000h Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 723 0000_0000h 35.3.24/ 4003_A08C Synchronization Configuration (FTM2_SYNCONF) 0000_0000h 35.3.25/ 4003_A090 FTM Inverting Control (FTM2_INVCTRL) 0000_0000h 35.3.26/ 4003_A094 FTM Software Output Control (FTM2_SWOCTRL) 0000_0000h 35.3.27/ 4003_A098 FTM PWM Load (FTM2_PWMLOAD) 0000_0000h K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 724 TOF remains set indicating an overflow has occurred. In this case, a TOF interrupt request is not lost due to the clearing sequence for a previous TOF. FTM counter has not overflowed. FTM counter has overflowed. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 725 Reset clears the CNT register. Writing any value to COUNT updates the counter with its initial value, CNTIN. When BDM is active, the FTM counter is frozen. This is the value that you may read. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 726 Address: Base address + 8h offset Reserved Reset FTMx_MOD field descriptions Field Description 31–16 This field is reserved. Reserved 15–0 Modulo Value K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 727 (set on channel (n) match, and clear on channel (n+1) match) Low-true pulses (clear on channel (n) match, and set on channel (n +1) match) Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 728 Enabled Falling edge Enabled Rising and falling edges Address: Base address + Ch offset + (8d × i), where i=0d to 7d Reset CHIE MSB MSA ELSB ELSA Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 729 FTM counter is not reset when the selected channel (n) input event is detected. FTM counter is reset when the selected channel (n) input event is detected. DMA Enable Enables DMA transfers for the channel. Disable DMA transfers. Enable DMA transfers. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 730 FTM clock, write the new value to the the CNTIN register and then initialize the FTM counter by writing any value to the CNT register. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 731 CHnF remains set indicating an event has occurred. In this case, a CHnF interrupt request is not lost due to the clearing sequence for a previous CHnF. Address: Base address + 50h offset Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 732 CH3F See the register description. No channel event has occurred. A channel event has occurred. Channel 2 Flag CH2F See the register description. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 733 • PWM synchronization • Write protection • Channel output initialization These controls relate to all channels within this module. Address: Base address + 54h offset Reset FAULTM INIT Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 734 The INIT bit is always read as 0. FTM Enable FTMEN This field is write protected. It can be written only when MODE[WPDIS] = 1. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 735 The synchronization event selection also depends on the PWMSYNC (MODE register) and SYNCMODE (SYNCONF register) bits. See synchronization. Address: Base address + 58h offset Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 736 The REINIT bit configures the synchronization when SYNCMODE is zero. FTM counter continues to count normally. FTM counter is updated with its initial value when the selected trigger is detected. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 737 Selects the value that is forced into the channel output when the initialization occurs. The initialization value is 0. The initialization value is 1. Channel 6 Output Initialization Value CH6OI Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 738 This feature is used for BLDC control where the PWM signal is presented to an electric motor at specific times to provide electronic commutation. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 739 Channel output is masked. It is forced to its inactive state. Channel 3 Output Mask CH3OM Defines if the channel output is masked or unmasked. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 740 Dual Edge Capture mode, Complementary, and Combine mode for each pair of channels (n) and (n+1), where n equals 0, 2, 4, and 6. Address: Base address + 64h offset Reset Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 741 The channel (n+1) output is the same as the channel (n) output. The channel (n+1) output is the complement of the channel (n) output. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 742 The Dual Edge Capture mode in this pair of channels is disabled. The Dual Edge Capture mode in this pair of channels is enabled. Complement Of Channel (n) For n = 4 COMP2 Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 743 Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in Dual Edge Capture mode according to Table 35-7. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 744 DECAP bit is cleared automatically by hardware if dual edge capture – one-shot mode is selected and when the capture of channel (n+1) event is made. The dual edge captures are inactive. The dual edge captures are active. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 745 Selects the division factor of the system clock. This prescaled clock is used by the deadtime counter. This field is write protected. It can be written only when MODE[WPDIS] = 1. Divide the system clock by 1. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 746 Several channels can be selected to generate multiple triggers in one PWM period. Channels 6 and 7 are not used to generate channel triggers. Address: Base address + 6Ch offset Reserved Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 747 Enables the generation of the channel trigger when the FTM counter is equal to the CnV register. The generation of the channel trigger is disabled. The generation of the channel trigger is enabled. Channel 5 Trigger Enable CH5TRIG Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 748 That is, the safe value of a channel is the value of its POL bit. Address: Base address + 70h offset Reserved Reset Reserved POL7 POL6 POL5 POL4 POL3 POL2 POL1 POL0 Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 749 Channel 1 Polarity POL1 Defines the polarity of the channel output. This field is write protected. It can be written only when MODE[WPDIS] = 1. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 750 35.3.18 Fault Mode Status (FTMx_FMS) This register contains the fault detection flags, write protection enable bit, and the logic OR of the enabled fault inputs. Address: Base address + 74h offset Reset Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 751 Writing a 1 to FAULTF2 has no effect. FAULTF2 bit is also cleared when FAULTF bit is cleared. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 752 Writing to the FILTER register has immediate effect and must be done only when the channels 0, 1, 2, and 3 are not in input modes. Failure to do this could result in a missing valid signal. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 753 35.3.20 Fault Control (FTMx_FLTCTRL) This register selects the filter value for the fault inputs, enables the fault inputs and the fault inputs filter. Address: Base address + 7Ch offset Reset FFVAL Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 754 Enables the fault input. This field is write protected. It can be written only when MODE[WPDIS] = 1. Fault input is disabled. Fault input is enabled. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 755 Fault Input 0 Enable FAULT0EN Enables the fault input. This field is write protected. It can be written only when MODE[WPDIS] = 1. Fault input is disabled. Fault input is enabled. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 756 CH0FVAL field of FILTER. The phase A filter is also disabled when CH0FVAL is zero. Phase A input filter is disabled. Phase A input filter is enabled. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 757 The Quadrature Decoder mode has precedence over the other modes. See Table 35-7. This field is write protected. It can be written only when MODE[WPDIS] = 1. Quadrature Decoder mode is disabled. Quadrature Decoder mode is enabled. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 758 Selects the FTM behavior in BDM mode. See mode. This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 759 Fault Input 2 Polarity FLT2POL Defines the polarity of the fault input. This field is write protected. It can be written only when MODE[WPDIS] = 1. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 760 Reset FTMx_SYNCONF field descriptions Field Description 31–21 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 761 The software trigger activates the FTM counter synchronization. Synchronization Mode SYNCMODE Selects the PWM Synchronization mode. Legacy PWM synchronization is selected. Enhanced PWM synchronization is selected. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 762 This register has a write buffer. The INVmEN bit is updated by the INVCTRL register synchronization. Address: Base address + 90h offset Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 763 • The CHnOCV bits select the value that is forced at the corresponding channel (n) output. This register has a write buffer. The fields are updated by the SWOCTRL register synchronization. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 764 The software output control forces 0 to the channel output. The software output control forces 1 to the channel output. Channel 0 Software Output Control Value CH0OCV Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 765 The channel output is affected by software output control. Channel 0 Software Output Control Enable CH0OC The channel output is not affected by software output control. The channel output is affected by software output control. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 766 Include the channel in the matching process. Channel 5 Select CH5SEL Do not include the channel in the matching process. Include the channel in the matching process. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 767: Functional Description
Include the channel in the matching process. 35.4 Functional description The notation used in this document to represent the counters and the generation of the signals is shown in the following figure. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 768: Counter Clock Source
Refer to the chip specific documentation for further information. Due to FTM hardware implementation limitations, the frequency of the fixed frequency clock must not exceed 1/2 of the system clock frequency. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 769 The FTM counter has these modes of operation: • Up counting • Up-down counting • Quadrature Decoder mode 35.4.3.1 Up counting Up counting is selected when: • QUADEN = 0, and • CPWMS = 0 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 770 FTM counting is up and signed. CNTIN[15] = 0 and CNTIN ≠ 0x0000 The initial value of the FTM counter is a positive number, so the FTM counting is up and unsigned. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 771 FTM operation difficult to comprehend. However, there is no restriction on this configuration, and an example is shown in the following figure. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 772: Up-Down Counting
The TOF bit is set when the FTM counter changes from MOD to (MOD – 1). If (CNTIN = 0x0000), the FTM counting is equivalent to TPM up-down counting, that is, up-down and unsigned counting. See the following figure. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 773: Free Running Counter
0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 TOF bit set TOF bit Figure 35-172. Example when the FTM counter is free running The FTM counter is also a free running counter when: K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 774: Counter Reset
FTM counter NUMTOF[4:0] 0x02 TOF counter 0x01 0x01 0x00 0x02 0x00 0x02 0x01 0x02 set TOF bit Figure 35-173. Periodic TOF when NUMTOF = 0x02 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 775: Input Capture Mode
While in BDM, the input capture function works as configured. When a selected edge event occurs, the FTM counter value, which is frozen because of BDM, is captured into the CnV register and the CHnF bit is set. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 776: Filter For Input Capture Mode
As long as the new state is stable on the input, the counter continues to increment. When the counter is equal to CHnFVAL[3:0], the state change of the input signal is validated. It is then transmitted as a pulse edge to the edge detector. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 777: Ftm Counter Reset In Input Capture Mode
The figure below shows the FTM counter reset when the selected input capture event is detected in a channel in input capture mode with ICRST = 1. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 778: Output Compare Mode
The CHnF bit is set and the channel (n) interrupt is generated if CHnIE = 1 at the channel (n) match (FTM counter = CnV). K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 779: Edge-Aligned Pwm (Epwm) Mode
CHnF bit is set and the channel (n) interrupt is generated if CHnIE = 1, however the channel (n) output is not modified and controlled by FTM. 35.4.6 Edge-Aligned PWM (EPWM) mode The Edge-Aligned mode is selected when: • QUADEN = 0 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 780 CNTIN register value is loaded into the FTM counter, and it is forced high at the channel (n) match (FTM counter = CnV). See the following figure. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 781: Center-Aligned Pwm (Cpwm) Mode
0x0001 to 0x7FFF because values outside this range can produce ambiguous results. In the CPWM mode, the FTM counter counts up until it reaches MOD and then counts down until it reaches CNTIN. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 782 If (ELSnB:ELSnA = X:1), then the channel (n) output is forced low at the channel (n) match (FTM counter = CnV) when counting down, and it is forced high at the channel (n) match when counting up. See the following figure. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 783: Combine Mode
(n) match (FTM counter = C(n)V). The CH(n+1)F bit is set and the channel (n +1) interrupt is generated, if CH(n+1)IE = 1, at the channel (n+1) match (FTM counter = C(n+1)V). K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 784 ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 Figure 35-189. Channel (n) output if (CNTIN < C(n)V < MOD) and (CNTIN < C(n+1)V < MOD) and (C(n)V < C(n+1)V) K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 785 (n) output with ELSnB:ELSnA = X:1 Figure 35-192. Channel (n) output if (CNTIN < C(n)V < MOD) and (C(n)V is Almost Equal to CNTIN) and (C(n+1)V = MOD) K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 786 ELSnB:ELSnA = 1:0 channel (n) output 100% duty cycle with ELSnB:ELSnA = X:1 Figure 35-194. Channel (n) output if C(n)V and C(n+1)V are not between CNTIN and MOD K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 787 (n) output 0% duty cycle with ELSnB:ELSnA = 1:0 channel (n) output 100% duty cycle with ELSnB:ELSnA = X:1 Figure 35-197. Channel (n) output if (C(n)V = C(n+1)V = MOD) K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 788 ELSnB:ELSnA = 1:0 channel (n) output 100% duty cycle with ELSnB:ELSnA = X:1 Figure 35-199. Channel (n) output if (C(n)V < CNTIN) and (CNTIN < C(n+1)V < MOD) K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 789 ELSnB:ELSnA = 1:0 channel (n) output 100% duty cycle with ELSnB:ELSnA = X:1 Figure 35-201. Channel (n) output if (C(n)V > MOD) and (CNTIN < C(n+1)V < MOD) K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 790: Asymmetrical Pwm
(n+1) match occurs, that is, FTM counter = C(n+1)V. So, Combine mode allows the generation of asymmetrical PWM signals. 35.4.9 Complementary mode The Complementary mode is selected when: K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 791: Registers Updated From Write Buffers
Figure 35-205. Channel (n+1) output in Complementary mode with (ELSnB:ELSnA = X:1) NOTE The complementary mode is not available in Output Compare mode. 35.4.10 Registers updated from write buffers K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 792: Cntin Register Update
Table 35-245. CnV register update When Then CnV register is updated CLKS[1:0] = 0:0 When CnV register is written, independent of FTMEN bit. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 793: Pwm Synchronization
The PWM synchronization with hardware trigger is initiated when a rising edge is detected at the enabled hardware trigger inputs. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 794: Software Trigger
PWMSYNC and REINIT bits. In this case if (PWMSYNC = 1) or (PWMSYNC = 0 and REINIT = 0) then SWSYNC bit is cleared at the next selected loading point after that the K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 795: Boundary Cycle And Loading Points
For both counting modes, if neither CNTMIN nor CNTMAX are 1, then the boundary cycles are not used as loading points for registers updates. See the register synchronization descriptions in the following sections for details. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 796: Mod Register Synchronization
= 0). However, it is expected that the MOD register be synchronized only by the enhanced PWM synchronization. In the case of enhanced PWM synchronization, the MOD register synchronization depends on SWWRBUF, SWRSTCNT, HWWRBUF, and HWRSTCNT bits according to this flowchart: K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 797 If the trigger event was a software trigger, then the SWSYNC bit is cleared on the next selected K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 798 SWSYNC bit is cleared according to the following example. If the trigger event was a hardware trigger, then the TRIGn bit is cleared according to Hardware trigger. Examples with software and hardware triggers follow. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 799 1 to SWSYNC bit SWSYNC bit software trigger event selected loading point MOD register is updated Figure 35-214. MOD synchronization with (SYNCMODE = 0) and (PWMSYNC = 1) K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 800: Cntin Register Synchronization
SYNCMODE = 0). However, it is expected that the OUTMASK register be synchronized only by the enhanced PWM synchronization. In the case of enhanced PWM synchronization, the OUTMASK register synchronization depends on SWOM and HWOM bits. See the following flowchart: K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 801 Figure 35-215. OUTMASK register synchronization flowchart In the case of legacy PWM synchronization, the OUTMASK register synchronization depends on PWMSYNC bit according to the following description. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 802 If (SYNCMODE = 0), (SYNCHOM = 1), and (PWMSYNC = 1), then this synchronization is made on the next enabled hardware trigger. The TRIGn bit is cleared according to Hardware trigger. An example with a hardware trigger follows. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 803: Invctrl Register Synchronization
PWM synchronization (INVC = 1 and SYNCMODE = 1) according to the following flowchart. In the case of enhanced PWM synchronization, the INVCTRL register synchronization depends on SWINVC and HWINVC bits. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 804: Swoctrl Register Synchronization
HWTRIGMODE bit ? clear TRIGn bit Figure 35-219. INVCTRL register synchronization flowchart 35.4.11.9 SWOCTRL register synchronization The SWOCTRL register synchronization updates the SWOCTRL register with its buffer value. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 805 ? wait hardware trigger n update SWOCTRL with its buffer value update SWOCTRL with its buffer value HWTRIGMODE bit ? clear TRIGn bit Figure 35-220. SWOCTRL register synchronization flowchart K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 806: Ftm Counter Synchronization
= 0). However, the FTM counter must be synchronized only by the enhanced PWM synchronization. In the case of enhanced PWM synchronization, the FTM counter synchronization depends on SWRSTCNT and HWRSTCNT bits according to the following flowchart. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 807 SWSYNC bit is cleared according to the following example. If the trigger event was a hardware trigger then the TRIGn bit is cleared according to Hardware trigger. Examples with software and hardware triggers follow. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 808 Figure 35-225. FTM counter synchronization with (SYNCMODE = 0), (HWTRIGMODE = 0), (REINIT = 1), (PWMSYNC = 1), and a hardware trigger was used K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 809 INV(m) bit selects the inverting to the pair channels (n) and (n+1). Figure 35-226. Channels (n) and (n+1) outputs after the inverting in High-True (ELSnB:ELSnA = 1:0) Combine mode K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 810: Software Output Control
PWM generation. The software output control is selected when: • QUADEN = 0 • DECAPEN = 0, and • CHnOC = 1 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 811 Software output control forces the following values on channels (n) and (n+1) when the COMP bit is one. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 812: Deadtime Insertion
(FTM counter = C(n)V) occurs, the channel (n) output remains at the high value until the end of the deadtime delay when the channel (n) output is cleared. Similarly, K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 813 Figure 35-230. Deadtime insertion with ELSnB:ELSnA = X:1, POL(n) = 0, and POL(n+1) = NOTE • The deadtime feature must be used only in Complementary mode. • The deadtime feature is not available in Output Compare mode. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 814: Deadtime Insertion Corner Cases
Figure 35-231. Example of the deadtime insertion (ELSnB:ELSnA = 1:0, POL(n) = 0, and POL(n+1) = 0) when the deadtime delay is comparable to channel (n+1) duty cycle K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 815: Output Mask
If CHnOM = 1, then the channel (n) output is forced to its inactive state (POLn bit value). If CHnOM = 0, then the channel (n) output is unaffected by the output mask. See the following figure. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 816: Fault Control
When there is a state change in the fault input n signal, the 5-bit counter is reset and starts counting up. As long as the new state is stable on the fault input n, the K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 817 1 value FAULTIN fault input 2 value fault input 3 value FAULTIE fault interrupt FAULTF0 FAULTF1 FAULTF FAULTF2 FAULTF3 Figure 35-235. FAULTF and FAULTIN bits and fault interrupt K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 818: Automatic Fault Clearing
FAULTF bit is cleared NOTE The channel (n) output is after the fault control with automatic fault clearing and POLn = 0. Figure 35-236. Fault control with automatic fault clearing K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 819: Manual Fault Clearing
• If FLTjPOL = 1, the fault j input polarity is low, so the logical zero at the fault input j indicates a fault. 35.4.17 Polarity control The POLn bit selects the channel (n) output polarity: K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 820: Features Priority
See the description of the CLKS field in the Status and Control register. 35.4.19 Features priority The following figure shows the priority of the features used at the generation of channels (n) and (n+1) outputs signals. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 821: Channel Trigger Output
If CHjTRIG = 1, where j = 0, 1, 2, 3, 4, or 5, then the FTM generates a trigger when the channel (j) match occurs (FTM counter = C(j)V). The channel trigger output provides a trigger signal that is used for on-chip modules. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 822: Initialization Trigger
• The FTM counter is automatically updated with the CNTIN register value by the selected counting mode. • When there is a write to CNT register. • When there is the FTM counter synchronization. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 823 0x04 0x05 0x06 0x07 0x00 0x01 0x02 0x03 0x04 0x05 FTM counter FTM counter synchronization initialization trigger Figure 35-242. Initialization trigger is generated when there is the FTM counter synchronization K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 824: Capture Test Mode
FTM counter and CnV registers. In this test mode, all channels must be configured for Input Capture mode and FTM counter must be configured to the counting. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 825 The channel interrupt is generated if (CHnF = 1). generated. The channel DMA transfer request is not The channel interrupt is not generated. generated. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 826: Dual Edge Capture Mode
* Filtering function for dual edge capture mode is only available in the channels 0 and 2 Figure 35-246. Dual Edge Capture mode block diagram The MS(n)A bit defines if the Dual Edge Capture mode is one-shot or continuous. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 827: One-Shot Capture Mode
The edge captures are enabled while DECAP bit is set. For each new measurement in One-Shot Capture mode, first the CH(n)F and CH(n+1) bits must be cleared, and then the DECAP bit must be set. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 828: Continuous Capture Mode
The DECAPEN bit selects the Dual Edge Capture mode, so it remains set. The DECAP bit is set to enable the measurement of next K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 829 The CH(n)F bit is set when the first edge of the positive polarity pulse is detected, that is, the edge selected by ELS(n)B:ELS(n)A bits. The CH(n+1)F bit K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 830: Period Measurement
If both channels (n) and (n+1) are configured to capture falling edges (ELS(n)B:ELS(n)A = 1:0 and ELS(n+1)B:ELS(n+1)A = 1:0), then the period between two consecutive falling edges is measured. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 831 - Problem 3: channel (n) input = 1, set DECAP, not clear CH(n)F, and not clear CH(n+1)F. Figure 35-249. Dual Edge Capture – One-Shot mode to measure of the period between two consecutive rising edges K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 832: Read Coherency Mechanism
The Dual Edge Capture mode implements a read coherency mechanism between the FTM counter value captured in C(n)V and C(n+1)V registers. The read coherency mechanism is illustrated in the following figure. In this example, the channels (n) and (n K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 833: Quadrature Decoder Mode
The Quadrature Decoder mode is selected if (QUADEN = 1). The Quadrature Decoder mode uses the input signals phase A and B to control the FTM counter increment and decrement. The following figure shows the quadrature decoder block diagram. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 834 An edge at phase A must not occur together an edge at phase B and vice-versa. The PHAPOL bit selects the polarity of the phase A input, and the PHBPOL bit selects the polarity of the phase B input. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 835 • there is a rising edge at phase B signal and phase A signal is at logic zero; • there is a rising edge at phase A signal and phase B signal is at logic one. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 836 FTM counter changes from CNTIN to MOD, TOF bit is set and TOFDIR bit is cleared. TOF bit indicates the FTM counter overflow occurred. TOFDIR indicates the counting was down when the FTM counter overflow occurred. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 837: Quadrature Decoder Boundary Conditions
FTM counter CNTIN 0x0000 Time Figure 35-257. Motor position jittering in a mid count value The following figure shows motor jittering produced by the phase B and A pulses respectively: K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 838: Bdm Mode
The channels outputs are frozen Writes to these registers bypass the registers when the chip enters in BDM buffers mode Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 839: Intermediate Load
In this case, it is not required to use the PWM synchronization. There are multiple possible loading points for intermediate load: K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 840 Table 35-255. Conditions for loads occurring at the next enabled loading point When a new value was written Then To the MOD register The MOD register is updated with its write buffer value. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 841: Global Time Base (Gtb)
FTM module B FTM counter GTBEEN bit FTM counter enable enable logic gtb_in gtb_in example glue logic gtb_out GTBEOUT bit gtb_out Figure 35-260. Global time base (GTB) block diagram K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 842: Enabling The Global Time Base (Gtb)
5. Reset the FTM counter: Write any value to the CNT register. To initiate the GTB feature in the configuration described in the preceding figure, write 1 to CONF[GTBEOUT] in the FTM module used as the time base. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 843: Reset Overview
The next step is to select the FTM counter clock by the CLKS[1:0] bits (item 4). It is important to highlight that the pins are only controlled by FTM when CLKS[1:0] bits are different from zero (See the table in the description of CnSC register). K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 844: Ftm Interrupts
– Channel (n) is in output compare and the channel (n) output is toggled when there is a match – C(n)V = 0x0014 Figure 35-262. FTM behavior after reset when the channel (n) is in Output Compare mode 35.6 FTM Interrupts K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 845: Timer Overflow Interrupt
• Do not use the Inverting without SW synchronization (see item 6). • Do not use the Initialization. • Do not change the polarity control. • Do not configure the HW synchronization K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 846 • Generate the Software Trigger Write to SYNC (SWSYNC = 1, TRIG2 = 0, TRIG1 = 0, TRIG0 = 0, SYNCHOM = 1, REINIT = 0, CNTMAX = 0, CNTMIN = 0) K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 847: Chapter 36 Periodic Interrupt Timer (Pit)
The PIT module is an array of timers that can be used to raise interrupts and trigger DMA channels. 36.1.1 Block diagram The following figure shows the block diagram of the PIT module. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 848: Signal Description
• Ability of timers to generate DMA trigger pulses • Ability of timers to generate interrupts • Maskable interrupts • Independent timeout periods for each timer 36.2 Signal description The PIT module has no external pins. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 849: Memory Map/Register Description
36.3.1 PIT Module Control Register (PIT_MCR) This register enables or disables the PIT timer clocks and controls the timers when the PIT enters the Debug mode. Access: User read/write K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 850: Pit_Mcr Field Descriptions
Clock for standard PIT timers is disabled. Freeze Allows the timers to be stopped when the device enters the Debug mode. Timers continue to run in Debug mode. Timers are stopped in Debug mode. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 851 • If the timer is disabled, do not use this field as its value is unreliable. • The timer uses a downcounter. The timer values are frozen in Debug mode if MCR[FRZ] is set. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 852 Timer Enable Enables or disables the timer. Timer n is disabled. Timer n is enabled. 36.3.5 Timer Flag Register (PIT_TFLGn) These registers hold the PIT interrupt flags. Access: User read/write K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 853: Functional Description
Each time a timer reaches 0, it will generate a trigger pulse and set the interrupt flag. All interrupts can be enabled or masked by setting TCTRLn[TIE]. A new interrupt can be generated only after the previous one is cleared. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 854 LDVAL with the new load value. This value will then be loaded after the next trigger event. See the following figure. Timer enabled New start Value p2 set Start value = p1 Trigger event Figure 36-25. Dynamically setting a new load value K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 855: Debug Mode
5.12 ms/20 ns = 256,000 cycles and Timer 3 every 30 ms/20 ns = 1,500,000 cycles. The value for the LDVAL register trigger is calculated as: LDVAL trigger = (period / clock period) -1 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 856: Example Configuration For Chained Timers
The interrupt for Timer 2 is enabled by setting TCTRL2[TIE], the Chain mode is activated by setting TCTRL2[CHN], and the timer is started by writing a 1 to TCTRL2[TEN]. TCTRL1[TEN] needs to be set, and TCTRL1[CHN] and TCTRL1[TIE] are cleared. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 857 PIT_TCTRL2 |= TEN; // start Timer 2 // Timer 1 PIT_LDVAL1 = 0x23C345FF; // setup Timer 1 for 600 000 000 cycles PIT_TCTRL1 = TEN; // start Timer 1 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 858 Example configuration for chained timers K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 859: Chapter 37 Low-Power Timer (Lptmr)
• Configurable clock source for prescaler/glitch filter • Configurable input source for pulse counter • Rising-edge or falling-edge 37.1.2 Modes of operation The following table describes the operation of the LPTMR module in various modes. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 860: Lptmr Signal Descriptions
CNR to increment. Timing Assertion or deassertion may occur at any time; input may assert asynchronously to the bus clock. 37.3 Memory map and register definition K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 861 LPTMR is disabled. The input connections vary by device. See the chip configuration details for information on the connections to these inputs. Pulse counter input 0 is selected. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 862 LPTMR is disabled and internal logic is reset. LPTMR is enabled. 37.3.2 Low Power Timer Prescale Register (LPTMRx_PSR) Address: 4004_0000h base + 4h offset = 4004_0004h Reset PRESCALE PBYP Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 863 LPTMR is disabled. The clock connections vary by device. NOTE: See the chip configuration details for information on the connections to these inputs. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 864 Address: 4004_0000h base + Ch offset = 4004_000Ch COUNTER Reset LPTMRx_CNR field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 15–0 Counter Value COUNTER K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 865: Lptmr Power And Reset
37.4.3 LPTMR prescaler/glitch filter The LPTMR prescaler and glitch filter share the same logic which operates as a prescaler in Time Counter mode and as a glitch filter in Pulse Counter mode. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 866: Prescaler Enabled
CNR can increment is once every 2 to 2 prescaler clock edges. When first enabled, the glitch filter will wait an additional one or two prescaler clock edges due to synchronization logic. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 867: Glitch Filter Bypassed
When reading the CNR, the bus clock must be at least two times faster than the rate at which the LPTMR counter is incrementing, otherwise incorrect data may be returned. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 868: Lptmr Hardware Trigger
The LPTMR interrupt is generated asynchronously to the system clock and can be used to generate a wakeup from any low-power mode, including the low-leakage modes, provided the LPTMR is enabled as a wakeup source. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 869: Chapter 38 Serial Peripheral Interface (Spi)
The serial peripheral interface (SPI) module provides a synchronous serial bus for communication between an MCU and an external peripheral device. 38.1.1 Block Diagram The block diagram of this module is as follows: K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 870 • Buffered receive operation using the receive FIFO (RX FIFO) with depth of 4 entries • TX and RX FIFOs can be disabled individually for low-latency updates to SPI queues K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 871 • Global interrupt request line • Modified SPI transfer formats for communication with slower peripheral devices • Power-saving architectural features: • Support for Stop mode • Support for Doze mode K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 872: Interface Configurations
Figure 38-2. SPI with queues and DMA 38.1.4 Modes of Operation The module supports the following modes of operation that can be divided into two categories: • Module-specific modes: • Master mode K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 873: Master Mode
The Module Disable mode can be used for MCU power management. The clock to the non-memory mapped logic in the module can be stopped while in the Module Disable mode. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 874: External Stop Mode
Master mode: Peripheral Chip Select 0 (O)—Selects an SPI slave to receive data transmitted from the module. Slave mode: Slave Select (I)—Selects the module to receive data transmitted from an SPI master. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 875: Pcs5/Pcss-Peripheral Chip Select 5/Peripheral Chip Select Strobe
Slave mode: Serial Clock (I)—Supplies a clock signal to the module from an SPI master. 38.2.6 SIN—Serial Input Master mode: Serial Input (I)—Receives serial data. Slave mode: Serial Input (I)—Receives serial data. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 876: Sout-Serial Output
(SPI0_PUSHR_SLAVE) 4002_C038 POP RX FIFO Register (SPI0_POPR) 0000_0000h 38.3.9/895 38.3.10/ 4002_C03C Transmit FIFO Registers (SPI0_TXFR0) 0000_0000h 38.3.10/ 4002_C040 Transmit FIFO Registers (SPI0_TXFR1) 0000_0000h Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 877 0000_0000h 38.3.11/ 4002_C07C Receive FIFO Registers (SPI0_RXFR0) 0000_0000h 38.3.11/ 4002_C080 Receive FIFO Registers (SPI0_RXFR1) 0000_0000h 38.3.11/ 4002_C084 Receive FIFO Registers (SPI0_RXFR2) 0000_0000h 38.3.11/ 4002_C088 Receive FIFO Registers (SPI0_RXFR3) 0000_0000h K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 878 Enables either Master mode (if supported) or Slave mode (if supported) operation. Enables Slave mode Enables Master mode Continuous SCK Enable CONT_SCKE Enables the Serial Communication Clock (SCK) to run continuously. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 879 Provides support for an externally controlled Doze mode power-saving mechanism. Doze mode has no effect on the module. Doze mode disables the module. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 880 Reserved 7–3 This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved. Reserved Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 881 38.3.3 Clock and Transfer Attributes Register (In Master Mode) (SPIx_CTARn) CTAR registers are used to define different transfer attributes. Do not write to the CTAR registers while the module is in the Running state. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 882 Phase bit as listed in the following table. See the BR field description for details on how to compute the baud rate. Table 38-40. SPI SCK Duty Cycle CPHA SCK Duty Cycle 50/50 50/50 33/66 40/60 43/57 50/50 66/33 60/40 57/43 Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 883 ASC field description for information on how to compute the After SCK Delay. Refer After SCK Delay for more details. Delay after Transfer Prescaler value is 1. Delay after Transfer Prescaler value is 3. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 884 Table 38-39. Delay Scaler Encoding Field Value Delay Scaler Value 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1024 1010 2048 1011 4096 1100 8192 Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 885 The following table lists the baud rate scaler values. Table 38-38. Baud Rate Scaler CTARn[BR] Baud Rate Scaler Value 0000 0001 0010 0011 0100 0101 0110 0111 Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 886 The number of bits transfered per frame is equal to the FMSZ field value plus 1. Note that the minimum valid value of frame size is 4. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 887 Data is changed on the leading edge of SCK and captured on the following edge. 24–23 This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved. Reserved 21–0 This field is reserved. Reserved K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 888 Transmit and receive operations are disabled (The module is in Stopped state). Transmit and receive operations are enabled (The module is in Running state). Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 889 No Rx FIFO overflow. Rx FIFO overflow has occurred. This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 890 Pop Next Pointer POPNXTPTR Contains a pointer to the RX FIFO entry to be returned when the POPR is read. The POPNXTPTR is updated when the POPR is read. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 891 EOQF interrupt requests are enabled. Transmit FIFO Underflow Request Enable TFUF_RE Enables the TFUF flag in the SR to generate an interrupt request. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 892 RFDF_RE bit in the RSER is set, the RFDF_DIRS bit selects between generating an interrupt request or a DMA request. Interrupt request. DMA request. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 893 Selects a continuous selection format. The bit is used in SPI Master mode. The bit enables the selected PCS signals to remain asserted between transfers. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 894 38.3.8 PUSH TX FIFO Register In Slave Mode (SPIx_PUSHR_SLAVE) Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access to PUSHR transfers all 32 bits to the TX FIFO. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 895 Address: 4002_C000h base + 38h offset = 4002_C038h RXDATA Reset SPIx_POPR field descriptions Field Description 31–0 Received Data RXDATA Contains the SPI data from the RX FIFO entry to which the Pop Next Data Pointer points. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 896 Address: 4002_C000h base + 7Ch offset + (4d × i), where i=0d to 3d RXDATA Reset SPIx_RXFRn field descriptions Field Description 31–0 Receive Data RXDATA Contains the received SPI data. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 897: Functional Description
Shift Register(SR) is set to indicate a completed frame transfer. SPI Master SPI Slave SOUT SOUT Shift Register Shift Register Baud Rate Generator PCSx Figure 38-47. Serial protocol overview K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 898: Start And Stop Of Module Transfers
• MCR[HALT] bit is set State transitions from Running to Stopped occur on the next frame boundary if a transfer is in progress, or immediately if no transfers are in progress. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 899: Serial Peripheral Interface (Spi) Configuration
SPI master. The SPI Slave mode transfer attributes are set in the CTAR0. The data is shifted out with MSB first. Shifting out of LSB is not supported in this mode. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 900: Fifo Disable Operation
PUSHR. When the TX FIFO is not full, the TX FIFO Fill Flag (TFFF) in the SR is set. The TFFF bit is cleared when TX FIFO is full and the DMA controller K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 901: Draining The Tx Fifo
POPNXTPTR field is incremented every time the POPR is read. The maximum value of the field is equal to the maximum implemented RXFR number and it rolls over after reaching the maximum. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 902: Filling The Rx Fifo
The following figure shows conceptually how the SCK signal is generated. System Clock 1+DBR Prescaler Scaler Figure 38-48. Communications clock prescalers and scalers K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 903: Baud Rate Generator
The clock frequency mentioned in the preceding table is given as an example. Refer to the clocking chapter for the frequency used to drive this module in the device. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 904: After Sck Delay
When in Non-Continuous Clock mode the t delay is configured according to the equation specified in the CTAR[DT] field description. When in Continuous Clock mode, the delay is fixed at 1 SCK period. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 905: Peripheral Chip Select Strobe Enable (Pcss )
Table 38-71. Peripheral Chip Select Strobe Negate computation example PASC Prescaler Delay after Transfer 100 MHz 0b11 70.0 ns The PCSS signal is not supported when Continuous Serial Communication SCK mode is enabled. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 906: Transfer Formats
MCR selects between Classic SPI Format and Modified Transfer Format. In the interface configurations, the module provides the option of keeping the PCS signals asserted between frames. See Continuous Selection Format for details. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 907: Classic Spi Transfer Format (Cpha = 0)
PCS signals. A delay of t is inserted before a new frame transfer can be initiated by the master. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 908: Classic Spi Transfer Format (Cpha = 1)
After the last clock edge occurs, a delay of t is inserted before the master negates the PCS signal. A delay of t is inserted before a new frame transfer can be initiated by the master. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 909: Continuous Selection Format
The Delay between Transfers (t ) is not inserted between the transfers. The following figure shows the timing diagram for two four-bit transfers with CPHA = 1 and CONT = 1. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 910 TX FIFO is completely transmitted, that is, the corresponding TCF flag is asserted and TXFIFO is empty, the slave is deselected for any further serial communication; otherwise, an underflow error occurs. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 911: Continuous Serial Communications Clock
Continuous SCK format with Continuous Selection disabled. NOTE In Continuous SCK mode, for the SPI transfer CTAR0 should always be used, and the TX FIFO must be cleared using the MCR[CLR_TXF] field before initiating transfer. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 912 The following figure shows timing diagram for Continuous SCK format with Continuous Selection enabled. SCK (CPOL = 0) SCK (CPOL = 1) Master SOUT Master SIN transfer 1 transfer 2 Figure 38-55. Continuous SCK timing diagram (CONT=1) K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 913: Slave Mode Operation Constraints
DMA requests depending on configuration of RSER register. The module also provides a global interrupt request line, which is asserted when any of individual interrupt requests lines is asserted. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 914 FIFO has occurred. The transmit underflow condition is detected only for the module operating in Slave mode and SPI configuration . The TFUF bit is set when the TX FIFO K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 915: Power-Saving Features
. While the clocks are shut off, this module's memory-mapped logic is not K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 916: Initialization/Application Information
1. When module executes last command word from a queue, the EOQ bit in the command word is set to indicate it that this is the last entry in the queue. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 917: Switching Master And Slave Mode
2. Clear the transmit and receive FIFOs by writing a 1 to the CLR_TXF and CLR_RXF bits in MCR. 3. Set the appropriate mode in MCR[MSTR] and enable it by clearing MCR[HALT]. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 918: Initializing Module In Master/Slave Modes
39.1k 27.9k 1024 48.8k 32.6k 19.5k 14.0k 2048 24.4k 16.3k 9.77k 6.98k 4096 12.2k 8.14k 4.88k 3.49k 8192 6.10k 4.07k 2.44k 1.74k 16384 3.05k 2.04k 1.22k 32768 1.53k 1.02k K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 919: Delay Settings
Transmit Next Pointer (TXNXTPTR). For the RX FIFO the first-in pointer is the Pop Next Pointer (POPNXTPTR). The following figure illustrates the concept of first-in and last-in FIFO entries along with the FIFO Counter. The TX K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 920 TX FIFO Base - Base address of TX FIFO TXCTR - TX FIFO Counter TXNXTPTR - Transmit Next Pointer TX FIFO Depth - Transmit FIFO depth, implementation specific K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 921 RX FIFO Base - Base address of RX FIFO RXCTR - RX FIFO counter POPNXTPTR - Pop Next Pointer RX FIFO Depth - Receive FIFO depth, implementation specific K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 922 Initialization/application information K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 923: Chapter 39 Inter-Integrated Circuit (I2C)
• Arbitration-lost interrupt with automatic mode switching from master to slave • Calling address identification interrupt • START and STOP signal generation and detection • Repeated START signal generation and detection • Acknowledge bit generation and detection K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 924: Modes Of Operation
Stop mode. The STOP instruction does not affect the I2C module's register states. 39.1.3 Block diagram The following figure is a functional block diagram of the I2C module. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 925: I 2 C Signal Descriptions
C are shown in the table found here. Table 39-1. I C signal descriptions Signal Description Bidirectional serial clock line of the I C system. Bidirectional serial data line of the I C system. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 926: I2C Address Register 1 (I2Cx_A1)
Contains the primary slave address used by the I2C module when it is addressed as a slave. This field is used in the 7-bit address scheme and the lower seven bits in the 10-bit address scheme. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 927: I2C Frequency Divider Register (I2Cx_F)
For example, if the I2C module clock speed is 8 MHz, the following table shows the possible hold time values with different ICR and MULT selections to achieve an I C baud rate of 100 kbit/s. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 928: I2C Control Register 1 (I2Cx_C1)
When this bit changes from 1 to 0, a STOP signal is generated and the mode of operation changes from master to slave. Slave mode Master mode Transmit Mode Select Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 929 In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 930: I2C Status Register (I2Cx_S)
This bit is set by hardware when the arbitration procedure is lost. The ARBL bit must be cleared by software, by writing 1 to it. Standard bus operation. Loss of arbitration. Range Address Match Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 931: I2C Data I/O Register (I2Cx_D)
Acknowledge signal was received after the completion of one byte of data transmission on the bus No acknowledge signal detected 39.3.5 I2C Data I/O register (I2Cx_D) Address: 4006_6000h base + 4h offset = 4006_6004h Read DATA Write Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 932: I2C Control Register 2 (I2Cx_C2)
Controls the number of bits used for the slave address. 7-bit address scheme 10-bit address scheme High Drive Select HDRS Controls the drive capability of the I2C pads. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 933: I2C Programmable Input Glitch Filter Register (I2Cx_Flt)
6. After receiving the I2C module's acknowledgment of the request to enter stop mode, the MCU determines whether to shut off the I2C module's clock. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 934: I2C Range Address Register (I2Cx_Ra)
Filter glitches up to width of n I2C module clock cycles, where n=1-15d 39.3.8 I2C Range Address register (I2Cx_RA) Address: 4006_6000h base + 7h offset = 4006_6007h Read Write Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 935: I2C Smbus Control And Status Register (I2Cx_Smb)
Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK. SMBus Alert Response Address Enable ALERTEN Enables or disables SMBus alert response address matching. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 936 No SCL high and SDA low timeout occurs SCL high and SDA low timeout occurs SHTF2 Interrupt Enable SHTF2IE Enables SCL high and SDA low timeout interrupt. SHTF2 interrupt is disabled SHTF2 interrupt is enabled K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 937: I2C Address Register 2 (I2Cx_A2)
Most significant byte of SCL low timeout value that determines the timeout period of SCL low. 39.3.12 I2C SCL Low Timeout Register Low (I2Cx_SLTL) Address: 4006_6000h base + Bh offset = 4006_600Bh Read SSLT[7:0] Write Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 938: Functional Description
2. Slave address transmission 3. Data transfer 4. STOP signal The STOP signal should not be confused with the CPU STOP instruction. The following figure illustrates I2C bus system communication. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 939: Start Signal
Only the slave with a calling address that matches the one transmitted by the master responds by sending an acknowledge bit. The slave sends the acknowledge bit by pulling SDA low at the ninth clock. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 940: Data Transfers
A STOP signal is defined as a low-to-high transition of SDA while SCL is asserted. The master can generate a STOP signal even if the slave has generated an acknowledgement, at which point the slave must release the bus. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 941: Repeated Start Signal
Afterward there is no difference between the device clocks and the state of SCL, and all devices start counting their high periods. The first device to complete its high period pulls SCL low again. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 942: Clock Stretching
These potentially varying SCL divider values are highlighted in the following table. For the actual SCL divider values for your device, see the chip-specific details about the I2C module. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 943 (hex) value value (clocks) value value 1024 1152 1280 1536 1920 1280 1536 1792 2048 1022 1025 2304 1150 1153 2560 1278 1281 3072 1534 1537 3840 1918 1921 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 944: Master-Transmitter Addresses A Slave-Receiver
A3. The slave-transmitter remains addressed until it receives a STOP condition (P) or a repeated START condition (Sr) followed by a different slave address. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 945: Address Matching
When the I2C module responds to one of these addresses, it acts as a slave-receiver and the IAAS bit is set after the address cycle. Software must read the Data register after the first byte transfer to determine that the address is matched. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 946: System Management Bus Specification
When the I2C module is a slave, if it detects the condition, it resets its communication and is then able to receive a new TIMEOUT,MIN START condition. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 947: Scl High Timeout
START to the STOP. When CSMBCLK LOW:SEXT TIMEOUT SEXT occurs, SEXT rises and also triggers SLTF. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 948: Fast Ack And Nack
NACK to the bus, so FACK must be switched off before the last byte transmits. 39.4.5 Resets The I2C module is disabled after a reset. The I2C module cannot cause a core reset. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 949: Byte Transfer Interrupt
GCAEN bit is set and a general call is received, the IAAS bit in the Status Register is set. The CPU is interrupted, provided the IICIE bit is set. The CPU must check the SRW bit and set its Tx mode accordingly. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 950: Stop Detect Interrupt
4. A repeated START cycle is requested in slave mode. 5. A STOP condition is detected when the master did not request it. The ARBL bit must be cleared (by software) by writing 1 to it. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 951: Timeout Interrupt In Smbus
MCU wakes from a low power mode where no peripheral bus is running. After the address matching IAAS bit is set, an interrupt is sent at the end of address matching to wake the core. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 952 2–3 bytes. During this transfer period, the DMA must be disabled because the C1 register is written to send a repeat start or to change the transfer direction. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 953: Initialization/Application Information
Data register. An example of an I2C driver which implements many of the steps described here is available in AN4342: Using the Inter-Integrated Circuit on ColdFire+ and Kinetis K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 954 2. When 10-bit addressing addresses a slave, the slave sees an interrupt following the first byte of the extended address. Ensure that for this interrupt, the contents of the Data register are ignored and not treated as a valid data transfer. Figure 39-30. Typical I2C interrupt routine K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 955 (in worst case) of the 9th SCL cycle. 3. This read is a dummy read in order to reset the SMBus receiver state machine. Figure 39-31. Typical I2C SMBus interrupt routine K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 956 Initialization/application information K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 957: Chapter 40 Universal Asynchronous Receiver/Transmitter (Uart)
• Programmable 8-bit or 9-bit data format • Separately enabled transmitter and receiver • Programmable transmitter output polarity • Programmable receive input polarity • Up to 14-bit break character transmission. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 958: Modes Of Operation
• 1/16 bit-time noise detection • DMA interface 40.1.2 Modes of operation The UART functions in the same way in all the normal modes. It has the following low power modes: K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 959: Uart Signal Descriptions
Stop mode. Bringing the CPU out of Stop mode by reset aborts any ongoing transmission or reception and resets the UART. 40.2 UART signal descriptions The UART signals are shown in the following table. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 960 Timing Driven at the beginning or within a bit time according to the bit encoding method along with other configuration settings. Otherwise, transmissions are independent of reception timing. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 961 UART FIFO Control Register (UART0_CFIFO) 40.3.18/ 4006_A012 UART FIFO Status Register (UART0_SFIFO) 40.3.19/ 4006_A013 UART FIFO Transmit Watermark (UART0_TWFIFO) 40.3.20/ 4006_A014 UART FIFO Transmit Count (UART0_TCFIFO) Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 962 UART FIFO Status Register (UART1_SFIFO) 40.3.19/ 4006_B013 UART FIFO Transmit Watermark (UART1_TWFIFO) 40.3.20/ 4006_B014 UART FIFO Transmit Count (UART1_TCFIFO) 40.3.21/ 4006_B015 UART FIFO Receive Watermark (UART1_RWFIFO) 40.3.22/ 4006_B016 UART FIFO Receive Count (UART1_RCFIFO) K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 963 SBR = 0. • Writing to BDH has no effect without writing to BDL, because writing to BDH puts the data in a temporary location until BDL is written. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 964 When LOOPS is set, the RxD pin is disconnected from the UART and the transmitter output is internally connected to the receiver input. The transmitter and the receiver must be enabled to use the loop function. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 965 Enables the parity function. When parity is enabled, parity function inserts a parity bit in the bit position immediately preceding the stop bit. Parity function disabled. Parity function enabled. Parity Type Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 966 Idle Line Interrupt Enable ILIE Enables the idle line flag, S1[IDLE], to generate interrupt requests IDLE interrupt requests disabled. IDLE interrupt requests enabled. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 967 I/O is not compromised, but the order of operations is important for flag clearing. When a flag is configured to trigger a DMA request, assertion of the associated DMA done signal from the DMA controller clears the flag. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 968 • Queuing a break character by writing 1 to SBK in C2. Transmitter active (sending data, a preamble, or a break). Transmitter idle (transmission activity complete). Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 969 1 then there may be data in the receiver buffer that was received with noise. At least one dataword was received with noise detected since the last time the flag was cleared. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 970 RXINV bits, which should be changed by the user only between transmit and receive packets. Address: Base address + 5h offset Read LBKDIF RXEDGIF MSBF RXINV RWUID BRK13 LBKDE Write Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 971 The detection of a framing error is not affected by this field. Transmitting break characters Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 972 To correctly transmit the 9th bit, write UARTx_C3[T8] to the desired value, then write the UARTx_D register with the remaining data. Transmitter Pin Data Direction in Single-Wire mode TXDIR Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 973 40.3.8 UART Data Register (UARTx_D) This register is actually two separate registers. Reads return the contents of the read-only receive data register and writes go to the write-only transmit data register. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 974 Address: Base address + 7h offset Read Write Reset UARTx_D field descriptions Field Description 7–0 Reads return the contents of the read-only receive data register and writes go to the write-only transmit data register. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 975 Read Write Reset UARTx_MA2 field descriptions Field Description 7–0 Match Address 40.3.11 UART Control Register 4 (UARTx_C4) Address: Base address + Ah offset Read MAEN1 MAEN2 BRFA Write Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 976 • If C2[TIE] and TDMAS are both set, then C2[TCIE] must be cleared, and D must not be written unless a DMA request is being serviced. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 977 • If S1[NF] and S1[PF] have not been set since the last time the receive buffer was empty, the NOISY and PARITYE fields will be zero. Address: Base address + Ch offset Read NOISY PARITYE Write Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 978 RTS will remain negated in the active low state unless TXRTSE is set. Transmitter RTS is active low. Transmitter RTS is active high. Transmitter request-to-send enable TXRTSE Controls RTS before and after a transmission. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 979 Enables/disables the infrared modulation/demodulation. IR disabled. IR enabled. 1–0 Transmitter narrow pulse Enables whether the UART transmits a 1/16, 3/16, 1/32, or 1/4 narrow pulse. 3/16. 1/16. 1/32. 1/4. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 980 Transmit FIFO/Buffer depth = 32 datawords. Transmit FIFO/Buffer depth = 64 datawords. Transmit FIFO/Buffer depth = 128 datawords. Reserved. Receive FIFO Enable RXFE Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 981 Writing to this field causes all data that is stored in the transmit FIFO/buffer to be flushed. This does not affect data that is in the transmit shift register. No flush operation occurs. All data in the transmit FIFO/Buffer is cleared out. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 982 Asserts when there is no data in the Transmit FIFO/buffer. This field does not take into account data that is in the transmit shift register. Table continues on the next page... K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 983 C2[TE] is not set. Changing the value of the watermark will not clear the S1[TDRE] flag. Address: Base address + 13h offset Read TXWATER Write Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 984 C2[RE] is not asserted. Changing the value in this register will not clear S1[RDRF]. Address: Base address + 15h offset Read RXWATER Write Reset K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 985: Functional Description
CPU and remote devices, including other CPUs. The UART transmitter and receiver operate independently, although they use the same baud rate generator. The CPU monitors the status of the UART, writes the data to be transmitted, and processes received data. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 986: Transmitter Character Length
• 10 logic 1s if C1[M] = 0 • 11 logic 1s if C1[M] = 1 and C4[M10] = 0 • 12 logic 1s if C1[M] = 1, C4[M10] = 1, C1[PE] = 1 K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 987: Transmitting Break Characters
1. The automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next character. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 988: Idle Characters
If CTS is deasserted in the middle of a transmission with characters remaining in the receiver data buffer, the character in the shift register is sent and TXD remains in the mark state until CTS is reasserted. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 989: Transceiver Driver Enable
The following figure shows the functional timing information for the transmitter. Along with the actual character itself, TXD shows the start bit. The stop bit is also indicated, with a dashed line if necessary. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 990: Receiver Character Length
LSB for the dataword. All necessary bit ordering is handled automatically by the module. Therefore, the format of the data read from receive data buffer is completely independent of S2[MSBF]. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 991: Character Reception
To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7 . The following table summarizes the results of the start bit verification samples. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 992 To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. The following table summarizes the results of the stop bit samples. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 993 In the following figure, verification sample at RT3 is high. The RT3 sample sets the noise flag. Although the perceived bit time is misaligned, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 994 The following figure shows the effect of noise early in the start bit time. Although this noise does not affect proper synchronization with the start bit time, it does set the noise flag. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 995 In the following figure, a noise burst makes the majority of data samples RT8, RT9, and RT10 high. This sets the noise flag but does not reset the RT clock. In start bits only, the RT8, RT9, and RT10 data samples are ignored. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 996: Framing Errors
The detection threshold for a break character can be adjusted when using an internal oscillator in a LIN system by setting S2[LBKDE]. The UART break character detection threshold depends on C1[M], C1[PE], S2[LBKDE] and C4[M10]. See the following table. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 997 The following figure shows receiver hardware flow control functional timing. Along with the actual character itself, RXD shows the start bit. The stop bit can also indicated, with a dashed line, if necessary. The watermark is set to 2. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 998: Infrared Decoder
40.4.2.8.3 Low-bit detection During the second half of the decoder count, a rising edge is decoded as a 0, which is sent to the receiver. The decoder counter is also reset. K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 999: High-Bit Detection
Figure 40-78. Slow data For an 8-bit data character, data sampling of the stop bit takes the receiver 154 RT cycles (9 bit times × 16 RT cycles + 10 RT cycles). K02F Sub-Family Reference Manual , Rev. 1, 7/2014 Freescale Semiconductor, Inc.
Page 1000: Fast Data Tolerance
The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is: ((154 − 160) ÷ 154) × 100 = 3.90% K02F Sub-Family Reference Manual , Rev. 1, 7/2014 1000 Freescale Semiconductor, Inc.

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