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Freescale Semiconductor KV31F Reference Manual

Freescale Semiconductor KV31F Reference Manual

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KV31F Sub-Family Reference Manual

Supports: MKV31F512VLL12, MKV31F512VLH12

Document Number: KV31P100M120SF7RM

Rev. 3, 7/2014

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Page 1 KV31F Sub-Family Reference Manual Supports: MKV31F512VLL12, MKV31F512VLH12 Document Number: KV31P100M120SF7RM Rev. 3, 7/2014...
Page 2 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 3: Table Of Contents
Memories and Memory Interfaces.......................47 2.2.4 Clocks................................48 2.2.5 Security and Integrity modules........................48 2.2.6 Analog modules............................49 2.2.7 Timer modules.............................49 2.2.8 Communication interfaces...........................50 2.2.9 Human-machine interfaces..........................51 Orderable part numbers..............................51 Chapter 3 Chip Configuration Introduction...................................53 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 4 3.3.3 PMC Configuration............................64 3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................65 3.3.5 MCM Configuration............................66 3.3.6 Crossbar-Light Switch Configuration......................67 3.3.7 Peripheral Bridge Configuration........................69 3.3.8 DMA request multiplexer configuration......................70 3.3.9 DMA Controller Configuration........................73 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 5 Flash Memory Configuration........................79 3.5.2 Flash Memory Controller Configuration.....................82 3.5.3 SRAM Configuration...........................83 3.5.4 System Register File Configuration......................84 3.5.5 EzPort Configuration...........................85 3.5.6 FlexBus Configuration..........................86 Security..................................89 3.6.1 CRC Configuration............................89 3.6.2 RNG Configuration............................90 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 6 Alternate Non-Volatile IRC User Trim Description..................129 SRAM memory map..............................129 Peripheral bridge (AIPS-Lite) memory map.........................130 4.5.1 Read-after-write sequence and required serialization of memory operations..........130 4.5.2 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map..................130 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 7 Debug trace clock............................147 5.7.5 PORT digital filter clocking.........................147 5.7.6 LPTMR clocking............................148 5.7.7 CLKOUT32K clocking..........................148 5.7.8 UART clocking............................149 5.7.9 LPUART0 clocking.............................149 Chapter 6 Reset and Boot Introduction...................................151 Reset....................................152 6.2.1 Power-on reset (POR)..........................152 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 8 Power Modes Description.............................167 Entering and exiting power modes..........................169 Power mode transitions..............................170 Power modes shutdown sequencing..........................171 Flash Program Restrictions............................172 Module Operation in Low Power Modes........................172 Chapter 8 Security Introduction...................................177 Flash Security................................177 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 9 9.11 DWT.....................................192 9.12 Debug in Low Power Modes............................193 9.12.1 Debug Module State in Low Power Modes....................193 9.13 Debug & Security.................................194 Chapter 10 Signal Multiplexing and Signal Descriptions 10.1 Introduction...................................195 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 10 Memory map and register definition..........................217 11.5.1 Pin Control Register n (PORTx_PCRn).......................224 11.5.2 Global Pin Control Low Register (PORTx_GPCLR)..................226 11.5.3 Global Pin Control High Register (PORTx_GPCHR).................227 11.5.4 Interrupt Status Flag Register (PORTx_ISFR)....................228 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 11 System Clock Gating Control Register 7 (SIM_SCGC7)................258 12.2.13 System Clock Divider Register 1 (SIM_CLKDIV1)...................258 12.2.14 Flash Configuration Register 1 (SIM_FCFG1)...................261 12.2.15 Flash Configuration Register 2 (SIM_FCFG2)...................263 12.2.16 Unique Identification Register High (SIM_UIDH)..................264 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 12 Property Definitions.............................309 13.6 Kinetis Flashloader Status Error Codes........................311 Chapter 14 Reset Control Module (RCM) 14.1 Introduction...................................313 14.2 Reset memory map and register descriptions.......................313 14.2.1 System Reset Status Register 0 (RCM_SRS0)....................314 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 13 15.4.6 Debug in low power modes.........................342 Chapter 16 Power Management Controller (PMC) 16.1 Introduction...................................345 16.2 Features..................................345 16.3 Low-voltage detect (LVD) system..........................345 16.3.1 LVD reset operation.............................346 16.3.2 LVD interrupt operation..........................346 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 14 LLWU Flag 3 register (LLWU_F3)......................366 17.3.9 LLWU Pin Filter 1 register (LLWU_FILT1)....................368 17.3.10 LLWU Pin Filter 2 register (LLWU_FILT2)....................369 17.4 Functional description..............................370 17.4.1 LLS mode..............................371 17.4.2 VLLS modes..............................371 17.4.3 Initialization..............................371 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 15 19.3 Functional Description..............................382 19.3.1 General operation............................382 19.3.2 Arbitration..............................383 19.4 Initialization/application information...........................384 Chapter 20 Peripheral Bridge (AIPS-Lite) 20.1 Introduction...................................387 20.1.1 Features................................387 20.1.2 General operation............................387 20.2 Functional description..............................388 20.2.1 Access support.............................388 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 16 22.1.3 Features................................403 22.2 Modes of operation...............................405 22.3 Memory map/register definition...........................405 22.3.1 TCD memory...............................405 22.3.2 TCD initialization............................406 22.3.3 TCD structure...............................406 22.3.4 Reserved memory and bit fields........................408 22.3.1 Control Register (DMA_CR)........................418 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 17 TCD Last Source Address Adjustment (DMA_TCDn_SLAST)..............451 22.3.25 TCD Destination Address (DMA_TCDn_DADDR)...................452 22.3.26 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)..............452 22.3.27 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCDn_CITER_ELINKYES)......................453 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 18 Chapter 23 External Watchdog Monitor (EWM) 23.1 Introduction...................................485 23.1.1 Features................................485 23.1.2 Modes of Operation.............................486 23.1.3 Block Diagram.............................487 23.2 EWM Signal Descriptions............................488 23.3 Memory Map/Register Definition..........................488 23.3.1 Control Register (EWM_CTRL).........................488 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 19 Watchdog disabled mode of operation......................500 24.3.6 Debug modes of operation...........................501 24.4 Testing the watchdog..............................501 24.4.1 Quick test..............................502 24.4.2 Byte test................................502 24.5 Backup reset generator..............................503 24.6 Generated resets and interrupts.............................504 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 20 MCG Control 1 Register (MCG_C1)......................520 25.3.2 MCG Control 2 Register (MCG_C2)......................521 25.3.3 MCG Control 3 Register (MCG_C3)......................522 25.3.4 MCG Control 4 Register (MCG_C4)......................523 25.3.5 MCG Control 5 Register (MCG_C5)......................524 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 21 MCG mode switching..........................543 Chapter 26 Oscillator (OSC) 26.1 Introduction...................................553 26.2 Features and Modes..............................553 26.3 Block Diagram................................554 26.4 OSC Signal Descriptions..............................554 26.5 External Crystal / Resonator Connections........................555 26.6 External Clock Connections............................556 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 22 Cache Tag Storage (FMC_TAGVDW3Sn)....................583 27.4.8 Cache Data Storage (upper word) (FMC_DATAW0SnU)................583 27.4.9 Cache Data Storage (lower word) (FMC_DATAW0SnL)................584 27.4.10 Cache Data Storage (upper word) (FMC_DATAW1SnU)................584 27.4.11 Cache Data Storage (lower word) (FMC_DATAW1SnL)................585 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 23 28.4.3 Interrupts..............................612 28.4.4 Flash Operation in Low-Power Modes......................613 28.4.5 Functional Modes of Operation........................613 28.4.6 Flash Reads and Ignored Writes........................613 28.4.7 Read While Write (RWW)...........................614 28.4.8 Flash Program and Erase..........................614 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 24 30.1.1 Definition..............................655 30.1.2 Features................................655 30.2 Signal descriptions................................656 30.3 Memory Map/Register Definition..........................659 30.3.1 Chip Select Address Register (FB_CSARn)....................660 30.3.2 Chip Select Mask Register (FB_CSMRn)....................661 30.3.3 Chip Select Control Register (FB_CSCRn)....................662 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 25 Features................................701 31.1.2 Block diagram..............................701 31.1.3 Modes of operation............................702 31.2 Memory map and register descriptions.........................702 31.2.1 CRC Data register (CRC_DATA).......................703 31.2.2 CRC Polynomial register (CRC_GPOLY)....................704 31.2.3 CRC Control register (CRC_CTRL)......................704 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 26 Core engine / control logic...........................718 32.5 Initialization/application information...........................719 Chapter 33 Analog-to-Digital Converter (ADC) 33.1 Introduction...................................721 33.1.1 Features................................721 33.1.2 Block diagram..............................722 33.2 ADC signal descriptions...............................723 33.2.1 Analog Power (VDDA)..........................724 33.2.2 Analog Ground (VSSA)..........................724 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 27 ADC Minus-Side General Calibration Value Register (ADCx_CLM3).............745 33.3.22 ADC Minus-Side General Calibration Value Register (ADCx_CLM2).............746 33.3.23 ADC Minus-Side General Calibration Value Register (ADCx_CLM1).............746 33.3.24 ADC Minus-Side General Calibration Value Register (ADCx_CLM0).............747 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 28 CMP, DAC and ANMUX diagram......................777 34.1.5 CMP block diagram.............................778 34.2 Memory map/register definitions..........................780 34.2.1 CMP Control Register 0 (CMPx_CR0).......................780 34.2.2 CMP Control Register 1 (CMPx_CR1).......................781 34.2.3 CMP Filter Period Register (CMPx_FPR)....................783 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 29 DAC Data Low Register (DACx_DATnL)....................807 35.4.2 DAC Data High Register (DACx_DATnH)....................807 35.4.3 DAC Status Register (DACx_SR).......................808 35.4.4 DAC Control Register (DACx_C0)......................809 35.4.5 DAC Control Register 1 (DACx_C1)......................810 35.4.6 DAC Control Register 2 (DACx_C2)......................811 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 30 Chapter 37 Programmable Delay Block (PDB) 37.1 Introduction...................................825 37.1.1 Features................................825 37.1.2 Implementation............................826 37.1.3 Back-to-back acknowledgment connections....................827 37.1.4 DAC External Trigger Input Connections....................827 37.1.5 Block diagram..............................827 37.1.6 Modes of operation............................829 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 31 Application information..............................844 37.5.1 Impact of using the prescaler and multiplication factor on timing resolution..........844 Chapter 38 FlexTimer Module (FTM) 38.1 Introduction...................................845 38.1.1 FlexTimer philosophy..........................845 38.1.2 Features................................846 38.1.3 Modes of operation............................847 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 32 Quadrature Decoder Control And Status (FTMx_QDCTRL)..............889 38.3.22 Configuration (FTMx_CONF)........................891 38.3.23 FTM Fault Input Polarity (FTMx_FLTPOL)....................892 38.3.24 Synchronization Configuration (FTMx_SYNCONF)..................893 38.3.25 FTM Inverting Control (FTMx_INVCTRL)....................895 38.3.26 FTM Software Output Control (FTMx_SWOCTRL)..................896 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 33 Features priority............................953 38.4.20 Channel trigger output..........................954 38.4.21 Initialization trigger............................955 38.4.22 Capture Test mode............................957 38.4.23 DMA................................958 38.4.24 Dual Edge Capture mode..........................959 38.4.25 Quadrature Decoder mode...........................966 38.4.26 BDM mode..............................971 38.4.27 Intermediate load............................972 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 34 Functional description..............................987 39.4.1 General operation............................987 39.4.2 Interrupts..............................989 39.4.3 Chained timers.............................989 39.5 Initialization and application information........................989 39.6 Example configuration for chained timers........................990 Chapter 40 Low-Power Timer (LPTMR) 40.1 Introduction...................................993 40.1.1 Features................................993 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 35 Module signal descriptions............................1008 41.2.1 PCS0/SS—Peripheral Chip Select/Slave Select..................1008 41.2.2 PCS1–PCS3—Peripheral Chip Selects 1–3....................1009 41.2.3 PCS4—Peripheral Chip Select 4........................1009 41.2.4 PCS5/PCSS—Peripheral Chip Select 5/Peripheral Chip Select Strobe............1009 41.2.5 SCK—Serial Clock............................1009 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 36 Power saving features..........................1049 41.5 Initialization/application information...........................1050 41.5.1 How to manage queues..........................1050 41.5.2 Switching Master and Slave mode.......................1051 41.5.3 Initializing Module in Master/Slave Modes....................1051 41.5.4 Baud rate settings............................1052 41.5.5 Delay settings...............................1052 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 37 I2C SCL Low Timeout Register Low (I2Cx_SLTL)...................1072 42.4 Functional description..............................1072 42.4.1 I2C protocol..............................1072 42.4.2 10-bit address...............................1077 42.4.3 Address matching............................1079 42.4.4 System management bus specification......................1080 42.4.5 Resets................................1082 42.4.6 Interrupts..............................1082 42.4.7 Programmable input glitch filter........................1085 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 38 UART Extended Data Register (UARTx_ED)....................1115 43.3.14 UART Modem Register (UARTx_MODEM).....................1116 43.3.15 UART Infrared Register (UARTx_IR)......................1117 43.3.16 UART FIFO Parameters (UARTx_PFIFO)....................1118 43.3.17 UART FIFO Control Register (UARTx_CFIFO)..................1119 43.3.18 UART FIFO Status Register (UARTx_SFIFO)...................1120 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 39 UART 7816 Wait Parameter Register C (UARTx_WP7816C_T1)............1134 43.4 Functional description..............................1135 43.4.1 Transmitter..............................1135 43.4.2 Receiver...............................1141 43.4.3 Baud rate generation............................1155 43.4.4 Data format (non ISO-7816)........................1157 43.4.5 Single-wire operation...........................1160 43.4.6 Loop operation.............................1161 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 40 Register definition.................................1182 44.2.1 LPUART Baud Rate Register (LPUARTx_BAUD)..................1183 44.2.2 LPUART Status Register (LPUARTx_STAT)....................1185 44.2.3 LPUART Control Register (LPUARTx_CTRL)..................1189 44.2.4 LPUART Data Register (LPUARTx_DATA).....................1194 44.2.5 LPUART Match Address Register (LPUARTx_MATCH).................1196 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 41 Port Data Input Register (GPIOx_PDIR).....................1219 45.2.6 Port Data Direction Register (GPIOx_PDDR).....................1220 45.3 Functional description..............................1220 45.3.1 General-purpose input..........................1220 45.3.2 General-purpose output..........................1220 Chapter 46 JTAG Controller (JTAGC) 46.1 Introduction...................................1223 46.1.1 Block diagram..............................1223 46.1.2 Features................................1224 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 42 46.4 Functional description..............................1229 46.4.1 JTAGC reset configuration..........................1229 46.4.2 IEEE 1149.1-2001 (JTAG) Test Access Port....................1229 46.4.3 TAP controller state machine........................1229 46.4.4 JTAGC block instructions..........................1231 46.4.5 Boundary scan..............................1234 46.5 Initialization/Application information..........................1234 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 43: About This Document
Hexadecimal number. For example, the hexadecimal equivalent of the number 60 is written 3Ch. In some cases, hexadecimal numbers are shown with the prefix 0x. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 44: Typographic Notation
Write 1 to clear: Refers to a register bitfield that must be written as 1 to be "cleared." KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 45: Introduction
Clocks • Multiple clock generation options available from internally- and externally- generated clocks • System oscillator to provide clock source for the MCU Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 46: Arm® Cortex®-M4 Core Modules
After clock restart, the NVIC observes the pending interrupt and performs the normal interrupt or event processing. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 47: System Modules
The WDOG monitors internal system operation and forces a reset in case of failure. It can run from an independent 1 KHz low power oscillator with a programmable refresh window to detect deviations in program flow or system frequency. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 48: Clocks
The system oscillator, in conjunction with an external crystal or resonator, generates a reference clock for the MCU. 2.2.5 Security and Integrity modules The following security and integrity modules are available on this device: KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 49: Analog Modules
ADC, DAC, or CMP. 2.2.7 Timer modules The following timer modules are available on this device: KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 50: Communication Interfaces
• 16-bit time or pulse counter with compare • Interrupt generated on Timer Compare • Hardware trigger generated on Timer Compare 2.2.8 Communication interfaces The following communication interfaces are available on this device: KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 51: Human-Machine Interfaces
Table 2-11. Orderable part numbers summary Freescale part number Pin count Package Program SRAM GPIO flash frequency MKV31F512VLL12 120 MHz LQFP 512 KB 96 KB MKV31F512VLH12 120 MHz LQFP 512 KB 96 KB KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 52 Orderable part numbers KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 53: Chip Configuration
3.2.1 ARM Cortex-M4 Core Configuration This section summarizes how the module has been configured in the chip. Full documentation for this module is provided by ARM and can be found at arm.com. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 54 Data code (DCODE) bus System bus The system bus is connected to a separate master port on the crossbar. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 55: Nested Vectored Interrupt Controller (Nvic) Configuration
3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration This section summarizes how the module has been configured in the chip. Full documentation for this module is provided by ARM and can be found at arm.com. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 56 The pin the NMI signal is multiplexed on, must be configured for the NMI function to generate the non-maskable interrupt request. 3.2.2.3 Interrupt channel assignments The interrupt source assignments are defined in the following table. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 57 DMA channel 8 transfer complete 0x0000_0064 DMA channel 9 transfer complete 0x0000_0068 DMA channel 10 transfer complete 0x0000_006C DMA channel 11 transfer complete Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 58 UART2 Single interrupt vector for UART status sources 0x0000_00D0 UART2 Single interrupt vector for UART error sources 0x0000_00D4 — — 0x0000_00D8 — — Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 59 — — 0x0000_0154 — — 0x0000_0158 — — 0x0000_015C FTM3 Single interrupt vector for all sources 0x0000_0160 DAC1 — 0x0000_0164 ADC1 — 1. Indicates the NVIC's interrupt source number. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 60 NVICIPR14 bitfield range is 20-23 Therefore, the following bitfield locations are used to configure the LPTMR interrupts: • NVICISER1[26] • NVICICER1[26] • NVICISPR1[26] • NVICICPR1[26] • NVICIABR1[26] • NVICIPR14[23:20] KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 61: Asynchronous Wake-Up Interrupt Controller (Awic) Configuration
Port Control Module - Any enabled pin interrupt is capable of waking the system ADCx The ADC is functional when using internal clock source Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 62: Fpu Configuration
3.2.5 JTAG Controller Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 63: System Modules
Figure 3-6. SIM configuration Table 3-10. Reference links to related information Topic Related module Reference Full description System memory map System memory map Clocking Clock distribution Power management Power management KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 64: System Mode Controller (Smc) Configuration
Table 3-12. Reference links to related information Topic Related module Reference Full description System memory map System memory map Power management Power management Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 65: Low-Leakage Wake-Up Unit (Llwu) Configuration
The device uses the following internal peripheral and external pin inputs as wakeup sources to the LLWU module. LLWU_Px are external pin inputs, and LLWU_M0IF- M7IF are connections to the internal peripheral interrupt flags. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 66: Mcm Configuration
After wakeup, the flags are cleared based on the peripheral clearing mechanism. 3.3.5 MCM Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 67: Crossbar-Light Switch Configuration
3.3.6 Crossbar-Light Switch Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 68 Crossbar switch master EzPort EzPort Crossbar switch slave Flash Flash Crossbar switch slave Peripheral bridges Peripheral bridge Crossbar switch slave GPIO controller GPIO controller Crossbar switch slave FlexBus/ FlexBus KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 69: Peripheral Bridge Configuration
3.3.7 Peripheral Bridge Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 70: Dma Request Multiplexer Configuration
3.3.8 DMA request multiplexer configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 71 Source description Async DMA number capable — Channel disabled Reserved Not used UART0 Receive UART0 Transmit UART1 Receive UART1 Transmit UART2 Receive UART2 Transmit Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 72 FTM3 Channel 5 FTM3 Channel 6 FTM3 Channel 7 ADC0 — ADC1 — CMP0 — CMP1 — Reserved — DAC0 — DAC1 — Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 73: Dma Controller Configuration
3.3.9 DMA Controller Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 74: External Watchdog Monitor (Ewm) Configuration
3.3.10 External Watchdog Monitor (EWM) Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 75 This table shows the EWM low-power modes and the corresponding chip low-power modes. Table 3-23. EWM low-power modes Module mode Chip mode Wait Wait, VLPW Stop Stop, VLPS, LLS KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 76: Watchdog Configuration
This table shows the WDOG module clocks and the corresponding chip clocks. Table 3-25. WDOG clock connections Module clock Chip clock LPO Oscillator 1 kHz LPO Clock Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 77: Clock Modules
3.4 Clock modules 3.4.1 MCG Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 78 Clock Distribution for more details on these clocks. NOTE The MCG chapter has many references to the RTC oscillator source. On this device that clock source is not available and KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 79: Osc Configuration
3.4.2.1 OSC modes of operation with MCG The MCG's C2 register bits configure the oscillator frequency range. See the OSC and MCG chapters for more details. 3.5 Memories and memory interfaces KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 80 The amounts of flash memory for the devices covered in this document are: Device Program flash (KB) Block 0 address range Block 1 address range MKV31F512VLL12 0x0000_0000–0x0003_FFFF 0x0004_0000–0x0007_FFFF MKV31F512VLH12 0x0000_0000–0x0003_FFFF 0x0004_0000–0x0007_FFFF KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 81 The flash memory operates in NVM normal and NVM special modes. The flash memory enters NVM special mode when the EzPort is enabled (EZP_CS asserted during reset). Otherwise, flash memory operates in NVM normal mode. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 82: Flash Memory Controller Configuration
Reference Full description Flash memory Flash memory controller controller System memory map System memory map Clocking Clock Distribution Transfers Flash memory Flash memory Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 83: Sram Configuration
Table 3-32. Reference links to related information Topic Related module Reference Full description SRAM SRAM System memory map System memory map Clocking Clock Distribution Transfers SRAM controller SRAM controller ARM Cortex-M4 core ARM Cortex-M4 core KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 84: System Register File Configuration
In VLLS1 and VLLS0 no SRAM is retained; however, the 32-byte register file available. 3.5.4 System Register File Configuration This section summarizes how the module has been configured in the chip. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 85: Ezport Configuration
3.5.5 EzPort Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 86: Flexbus Configuration
3.5.6 FlexBus Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 87 FlexBus or another module signals are available on the external pin, while the FlexBus's CSPMCR register configures which FlexBus signals are available from the modules. The control signals are grouped as illustrated: KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 88 Reserved FB_CS4 FB_TSIZ0 Group2 FB_BE_31_24 External Reserved Pins FB_CS5 FB_TSIZ1 Group3 FB_BE_23_16 Reserved FB_TBST FB_CS2 Group4 FB_BE_15_8 Reserved FB_TA FB_CS3 Group5 FB_BE_7_0 Reserved Figure 3-25. FlexBus control signal multiplexing KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 89: Security
3.6 Security 3.6.1 CRC Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 90: Rng Configuration
Figure 3-27. RNG configuration Table 3-37. Reference links to related information Topic Related module Reference Full description System memory map System memory map Clocking Clock distribution Power management Power management KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 91: Analog
The number of ADC channels present on the device is determined by the pinout of the specific device package. For details regarding the number of ADC channel available on a particular package, refer to the signal multiplexing chapter of this MCU. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 92 AD11 Reserved Reserved 01100 AD12 Reserved ADC0_SE12 01101 AD13 Reserved ADC0_SE13 01110 AD14 Reserved ADC0_SE14 01111 AD15 Reserved ADC0_SE15 10000 AD16 Reserved ADC0_SE16 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 93 DAD1 ADC1_DP1 and ADC1_DM1 ADC1_DP1 00010 DAD2 Reserved Reserved 00011 DAD3 ADC1_DP3 and ADC1_DM3 ADC1_DP3 00100 AD4a Reserved ADC1_SE4a 00101 AD5a Reserved ADC1_SE5a Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 94 9. This is the PMC bandgap 1V reference voltage and not the VREF module 1.2 V reference voltage. Prior to reading from this ADC channel, ensure that you enable the bandgap buffer by setting the PMC_REGSC[BGBE] bit. Refer to the device data sheet for the bandgap voltage (V ) specification. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 95 ADCx_SE7b Figure 3-29. ADCx_SEn channels a and b selection 3.7.1.5 ADC Hardware Interleaved Channels The AD8 and AD9 channels on ADCx are interleaved in hardware using the following configuration. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 96 ADC is the PDB. The PDB itself can be triggered by other peripherals. For example: LPTMR Output signal is connected to the PDB. The PDB input KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 97 ADCx_CFG1[ADICLK] bitfield. The following table shows the chip-specific clock assignments for this bitfield. NOTE The ALTCLK option is only usable when OSCERCLK is in the MHz range. A system with OSCERCLK in the kHz range has KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 98: Cmp Configuration
LLS, VLLS3, VLLS2, VLLS1, VLLS0 3.7.2 CMP Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 99 Bandgap 6b DAC0 Reference 6b DAC1 Reference 3.7.2.2 CMP external references The 6-bit DAC sub-block supports selection of two references. For this device, the references are connected as follows: KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 100: 12-Bit Dac Configuration
3.7.3 12-bit DAC Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 101 DACREF_2 input. Use DACx_C0[DACRFS] control bit to select between these two options. Be aware that if the DAC and ADC use the VREF_OUT reference simultaneously, some degradation of ADC accuracy is to be expected due to DAC switching. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 102: Vref Configuration
PMC_REGSC[BGEN] bit must be set if the VREF regulator is required to remain operating in VLPx modes. NOTE For either an internal or external reference if the VREF_OUT functionality is being used, VREF_OUT signal must be KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 103: Timers
3.8.1.1 PDB Instantiation 3.8.1.1.1 PDB Output Triggers Table 3-49. PDB output triggers Number of PDB channels for ADC trigger Number of pre-triggers per PDB channel Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 104 Channel 1 triggers ADC1 trigger and synchronous input 1 of FTM0 DAC triggers DAC0 and DAC1 trigger Pulse-out Pulse-out connected to each CMP module's sample/window input to control sample operation KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 105 3.8.1.5 DAC External Trigger Input Connections In this MCU, the following DAC external trigger inputs are implemented. • DAC external trigger input 0: ADC0SC1A_COCO • DAC external trigger input 1: ADC1SC1A_COCO KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 106: Flextimer Configuration
31:2 - Reserved 3.8.2 FlexTimer Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 107 Quadrature decoder or general purpose FTM2 Quadrature decoder or general purpose FTM3 3-phase motor + 2 general purpose or stepper motor 1. Only channels 0 and 1 are available. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 108 • FTM2 FAULT1 = CMP1 output • FTM3 FAULT0 = FTM3_FLT0 pin or CMP0 output 3.8.2.6 FTM Hardware Triggers The FTM synchronization hardware triggers are connected in the chip as follows: KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 109 This device has two 2- channel FTMs. (FTM1 and FTM2) and thus provides 4 input capture pins. To simplify KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 110 50% duty PWM signal and limit the start and modulus values for the free running counter. FTM2 has a similar restriction when FTM2_CH1 is used for modulating an FTM3 channel. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 111 Global time base (GTB)). FTM0 provides the only source for the FTM global time base. The other FTM modules can share the time base as shown in the following figure: KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 112: Pit Configuration
“debug halt mode". 3.8.3 PIT Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 113: Low-Power Timer Configuration
3.8.4 Low-power timer configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 114 LPO — 1 kHz clock (not available in VLLS0 mode) ERCLK32K — secondary external reference clock OSCERCLK_UNDIV — Undivided external reference clock (not available in VLLS0 mode) Clock Distribution for more details on these clocks. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 115: Communication Interfaces
Figure 3-42. SPI configuration Table 3-57. Reference links to related information Topic Related module Reference Full description System memory map System memory map Clocking Clock Distribution Signal Multiplexing Port control Signal Multiplexing KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 116 Transmit FIFO size SPI0 SPI1 3.9.1.5 RX FIFO Size SPI supports up to 16-bit frame size during reception. Table 3-59. SPI receive FIFO size SPI Module Receive FIFO size SPI0 SPI1 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 117 SPI host might not be received correctly. This is dependent on the transfer rate used for the SPI, the delay between chip select assertion and presentation of data, and the system interrupt latency. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 118 Writing a different 16-bit command word will cause all subsequent 8-bit or 16-bit writes to the transmit data word to be pushed to the TX FIFO with the new command word. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 119: I2C Configuration
3.9.3 UART Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 120 3. IrDA is available on all UARTs 4. UART0 contains the standard features plus ISO7816 5. UART0 contains 8-entry transmit and 8-entry receive FIFOs 6. All other UARTs contain a 1-entry transmit and receive FIFOs KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 121 Wait timer (ISO7816) — — Character wait timer — — (ISO7816) Block wait timer (ISO7816) — — Guard time violation — — (ISO7816) ATR duration timer — — (ISO7816) KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 122: Lpuart Configuration
The module can remain functional in Stop and VLPS mode provided the clock it is using remains enabled. This module supports LIN slave operation. 3.10 Human-machine interfaces KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 123: Gpio Configuration
PTD7, PTC3, and PTC4. All other GPIO support normal drive option only. PTA4 includes a passive input filter that is enabled or disabled by PORTA_PCR4[PFE] control. This reset default is to have this function disabled. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 124 Human-machine interfaces KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 125: Memory Map
32-bit word of the aliased address space to a unique bit in the underlying RAM or peripheral address space to support single-bit insert and extract operations from the processor. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 126 1. EzPort master port is statically muxed with DMA master port. Access rights to AIPS-Lite peripheral bridge and general purpose input/output (GPIO) module address space is limited to the core, DMA and EzPort. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 127: Aliased Bit-Band Regions
• a value of 0x0000_0000 to indicate the target bit is clear • a value of 0x0000_0001 to indicate the target bit is set Bit-band region Alias bit-band region Figure 4-1. Alias bit-band mapping KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 128: Flash Access Control Introduction
The flash memory and the flash registers are located at different base addresses as shown in the following figure. The base address for each is specified in System memory map. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 129: Alternate Non-Volatile Irc User Trim Description
The on-chip RAM is split in two regions: SRAM_L and SRAM_U. The RAM is implemented such that the SRAM_L and SRAM_U ranges form a contiguous block in the memory map. See SRAM Configuration for details. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 130: Peripheral Bridge (Aips-Lite) Memory Map
ACTLR[DISDEFWBUF]. However, disabling buffered writes is likely to degrade system performance much more than simply performing the required memory serialization for the situations that truly require it. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 131 0x4001_C000 — 0x4001_D000 — 0x4001_E000 — 0x4001_F000 Flash memory controller 0x4002_0000 Flash memory 0x4002_1000 DMA channel mutiplexer 0x4002_2000 — 0x4002_3000 — 0x4002_4000 — Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 132 SIM low-power logic 0x4004_8000 System integration module (SIM) 0x4004_9000 Port A multiplexing control 0x4004_A000 Port B multiplexing control 0x4004_B000 Port C multiplexing control Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 133 0x4006_9000 — 0x4006_A000 UART 0 0x4006_B000 UART 1 0x4006_C000 UART 2 0x4006_D000 — 0x4006_E000 — 0x4006_F000 — 0x4007_0000 — 0x4007_1000 — 0x4007_2000 — Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 134: Private Peripheral Bus (Ppb) Memory Map
0xE000_F000–0xE003_FFFF Reserved 0xE004_0000–0xE004_0FFF Trace Port Interface Unit (TPIU) 0xE004_1000–0xE004_1FFF Reserved 0xE004_2000–0xE004_2FFF Reserved 0xE004_3000–0xE004_3FFF Reserved 0xE004_4000–0xE007_FFFF Reserved 0xE008_0000–0xE008_0FFF Miscellaneous Control Module (MCM) 0xE008_1000–0xE008_1FFF Reserved Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 135 Chapter 4 Memory Map Table 4-3. PPB memory map (continued) System 32-bit Address Range Resource 0xE008_2000–0xE00F_EFFF Reserved 0xE00F_F000–0xE00F_FFFF ROM Table - allows auto-detection of debug components KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 136 Private Peripheral Bus (PPB) memory map KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 137: Clock Distribution
SIM module. Reference those sections for detailed register and bit descriptions. 5.3 High-Level device clocking diagram The following system oscillator, MCG, and module registers control the multiplexers, dividers, and clock gates shown in the below figure: KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 138: Clock Definitions
The following table describes the clocks in the previous block diagram. Clock name Description Core clock MCGOUTCLK divided by OUTDIV1 clocks the ARM Cortex- M4 core Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 139: Device Clock Summary
System oscillator 32kHz output ERCLK32K Clock source for some modules that is chosen as OSC32KCLK. PMC 1kHz output 5.4.1 Device clock summary The following table provides more information regarding the on-chip clocks. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 140 30-40 kHz or 4 30-40 kHz or 4 4 MHz only MCG_C1[IRCLKEN ] cleared, (MCGIRCLK) Stop or VLPS mode and MCG_C1[IREFSTE N] cleared, or LLS/VLLS mode Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 141: Internal Clocking Requirements
2. The bus clock frequency must be programmed to 60 MHz or less in HSRUN, 50 MHz or less in RUN, and an integer divide of the core clock. The core clock to bus clock ratio is limited to a max value of 8. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 142 26.67 MHz Option 3: High Speed Run Clock Frequency Core clock 120 MHz System clock 120 MHz Bus clock 60 MHz FlexBus clock 30 MHz Flash clock 24 MHz KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 143: Clock Divider Values After Reset
800 kHz or less. In this case, one example of correct configuration is MCG_SC[FCRDIV]=000b and SIM_CLKDIV1[OUTDIV4]=0100b, resulting in a divide by 5 setting. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 144: Clock Gating
— Watchdog timer Bus clock — Clocks Flash clock MCGOUTCLK, MCGPLLCLK, — MCGFLLCLK, MCGIRCLK, OSCCLK, IRC48MCLK Bus clock OSCERCLK, OSCCLK, — OSCERCLK_UNDIV, OSC32KCLK Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 145: Pmc 1-Khz Lpo Clock
The Power Management Controller (PMC) generates a 1-kHz clock that is enabled in all modes of operation, including all low power modes except VLLS0. This 1-kHz source is commonly referred to as LPO clock or 1-kHz LPO clock. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 146: Irc 48Mhz Clock
• an ADC alternate clock source • clock source for LPUART communications 5.7.3 WDOG clocking The WDOG may be clocked from two clock sources as shown in the following figure. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 147: Debug Trace Clock
The digital filters in the PORTD module can be clocked as shown in the following figure. NOTE In stop mode, the digital input filters are bypassed unless they are configured to run from the 1 kHz LPO clock source. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 148: Lptmr Clocking
SIM_SOPT1[OSC32KOUT], overriding the existing pin mux configuration for that pin. Except for VLLS0 mode, this function is available in all other modes of operation (including LLS3, LLS2, VLLS3, VLLS2, VLLS1 and System Reset). KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 149: Uart Clocking
The chosen clock must remain enabled if the LPUART0 is to continue operating in all required low-power modes. MCGIRCLK OSCERCLK LPUART0 clock MCGFLLCLK MCGPLLCLK IRC48MCLK SIM_SOPT2[PLLFLLSEL] SIM_SOPT2[LPUARTSRC] Figure 5-7. LPUART0 clock generation KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 150 Module clocks KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 151: Reset And Boot
The MCU exits reset in functional mode that is controlled by EZP_CS pin to select between the single chip (default) or serial flash programming (EzPort) modes. See Boot options for more details. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 152: Reset
During and following a reset, the JTAG pins have their associated input pins configured • TDI in pull-up (PU) • TCK in pull-down (PD) • TMS in PU and associated output pin configured as: • TDO with no pull-down or pull-up KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 153 The LVD can be configured to generate a reset upon detection of a low voltage condition by setting the PMC's LVDSC1[LVDRE] bit to 1. The low voltage detection threshold is determined by the PMC's LVDSC1[LVDV] field. After an LVD reset has occurred, the KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 154 , as controlled by the C2[RANGE] field loc_low loc_high in the MCG module, the MCU resets. The RCM's SRS0[LOC] bit is set to indicate this reset source. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 155 The LOCKUP gives immediate indication of seriously errant kernel software. This is the result of the core being locked because of an unrecoverable exception following the activation of the processor’s built in system state protection hardware. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 156: Mcu Resets
6.2.3.2 Chip POR not VLLS The Chip POR not VLLS reset asserts on POR and LVD reset sources. It resets parts of the SMC and SIM. It also resets the LPTMR. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 157: Reset Pin
For all reset sources except a VLLS Wakeup that does not occur via the RESET pin, the RESET pin is driven low by the MCU for at least 128 bus clock cycles and until flash initialization has completed. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 158: Debug Resets
• MDM-AP (MDM control and status registers) CDBGRSTREQ does not reset the debug-related registers within the following modules: • CM4 core (core debug registers: DHCSR, DCRSR, DCRDR, DEMCR) • FPB KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 159: Boot
Serial flash programming mode (EzPort) Single chip (default) 1. CDBGRSTREQ does not affect AHB resources so that debug resources on the private peripheral bus are available during System Reset. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 160 EzPort mode if the EZP_CS/NMI pin is used for its NMI function. EzPort operation is enabled. The state of EZP_CS pin during reset determines if device enters EzPort mode. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 161: Boot Sequence
(an indication of a slow rise time on the RESET pin or external drive in low), the system continues to be held in reset. Once the RESET pin is detected KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 162 NMI interrupt. The processor executes an Exception Entry and reads the NMI interrupt handler address from vector-table offset 8. The CPU begins execution at the NMI interrupt handler. Subsequent system resets follow this same reset flow. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 163: Power Management
If configured, a DMA request (using the asynchronous DMA wakeup) can also be used to exit Partial Stop for the duration of a DMA transfer before the device is transitioned back into PSTOP2. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 164: Dma Wakeup
Stop mode and then requesting bus slaves to enter Stop mode. In STOP and VLPS modes the MCG and PMC would then also enter their appropriate modes. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 165: Compute Operation
VLPS mode. The MCG, PMC, SRAM and Flash read port are not affected by Compute Operation, although the Flash register interface is disabled. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 166: Peripheral Doze
• The CPU is in Stop mode, including the entry sequence and for the duration of a DMA wakeup. • The CPU is in Compute Operation, including the entry sequence and for the duration of a DMA wakeup. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 167: Clock Gating
Stop mode entry is not supported directly from HSRUN and requires transition to Run prior to an attempt to enter a stop mode. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 168 LLS recovery. A portion of SRAM_U remains powered on (content retained and I/O states held). Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 169: Entering And Exiting Power Modes
Recovery from VLLSx is through the wake-up Reset event. The chip wake-ups from VLLSx by means of reset, an enabled pin or enabled module. See the table "LLWU inputs" in the LLWU configuration section for a list of the sources. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 170: Power Mode Transitions
VLPR and VLPW are limited in frequency. The LLS and VLLSx mode(s) are the lowest power stop modes based on amount of logic or memory that is required to be retained by the application. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 171: Power Modes Shutdown Sequencing
• System level wait and VLPW modes equate to: SLEEPING & SLEEPDEEP • All other low power modes equate to: SLEEPING & SLEEPDEEP When entering the non-wait modes, the chip performs the following sequence: KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 172: Flash Program Restrictions
• static = Module register states and associated memories are retained. • powered = Memory is powered to retain contents. • low power = Memory is powered to retain contents in a lower power state KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 173 Core clock 4 MHz max Platform clock 4 MHz max 4 MHz max System clock 4 MHz max 4 MHz max OFF in CPO Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 174 FF in PSTOP2 in CPO Security static static static static in CPO Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 175 VLLSx only supports low speed external pin to pin or external pin to DAC compares. Windowed, sampled & filtered modes of operation are not available while in stop, VLPS, LLSx, or VLLSx modes. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 176 Module Operation in Low Power Modes KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 177: Security
Further information regarding the flash security options and enabling/disabling flash security is available in the Flash Memory Module. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 178: Security Interactions With Other Modules
Erase in Progress bit in the MDM-AP Control register to trigger a mass erase (Erase All Blocks) command. A mass erase via the debugger is allowed even when some memory locations are protected. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 179 Chapter 8 Security When mass erase is disabled, mass erase via the debugger is blocked. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 180 Security Interactions with other Modules KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 181: Introduction
• ARM Real-Time Trace Interface(1-pin asynchronous mode only) The basic Cortex-M4 debug architecture is very flexible. The following diagram shows the topology of the core debug architecture and its components. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 182 Singlestep, Register Access, Run, Core Status S/W Instrumentation Messaging + Simple Data Trace Messaging + Watchpoint Messaging DWT (Data and Address Watchpoints) 4 data and address watchpoints Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 183: References
• ARM Debug Interface v5.1 • ARM CoreSight Architecture Specification 9.2 The Debug Port The configuration of the cJTAG module, JTAG controller, and debug port is illustrated in the following figure: KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 184: Jtag-To-Swd Change Sequence
3. Send more than 50 TCK cycles with TMS (SWDIO) =1 NOTE See the ARM documentation for the CoreSight DAP Lite for restrictions. 9.2.2 JTAG-to-cJTAG change sequence 1. Reset the debug port KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 185: Debug Port Pin Descriptions
TAPs (TDO) are muxed based on the IR code which is selected. This design is fully JTAG compliant and appears to the JTAG chain as a single TAP. At power on reset, ARM's IDCODE (IR=4'b1110) is selected. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 186: Ir Codes
JTAG, cJTAG, or SWD. The MDM-AP is accessible as Debug Access Port 1 with the available registers shown in the table below. Table 9-4. MDM-AP Register Summary Address Register Description Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 187: Mdm-Ap Control Register
SELECT[7:4] = 0xF selects the bank with IDR A[3:2] = 2’b11 selects the IDR Register See Control and Status Register (IDR register reads 0x001C_0000) Descriptions Figure 9-3. MDM AP Addressing KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 188 This bit is used by the debugger to clear the sticky LLS and VLLSx mode entry status bits. This bit is asserted and cleared by the debugger. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 189: Mdm-Ap Status Register
1 Mass erase is enabled Backdoor Access Key Enable Indicates if the MCU has the backdoor access key enabled. 0 Disabled 1 Enabled Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 190: Debug Resets
9.6 Debug Resets The debug system receives the following sources of reset: • JTAG_TRST_b from an external signal. This signal is optional and may not be available in all packages. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 191: Ahb-Ap
The ITM is an application-driven trace source that supports printf style debugging to trace Operating System (OS) and application events, and emits diagnostic system information. The ITM emits trace information as packets. There are four sources that can KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 192: Core Trace Connectivity
DWT_COMP1, can also be used as a data comparator. • The DWT contains counters for: • Clock cycles (CYCCNT) • Folded instructions • Load store unit (LSU) operations • Sleep cycles KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 193: Debug In Low Power Modes
HW, the MDM-AP Control register can be configured hold the system in reset on recovery so that the debugger can regain control and reconfigure debug logic prior to the system exiting reset and resuming operation. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 194: Debug & Security
MDM-AP Control Register. In the case of a secure device that has mass erase disabled (FSEC[MEEN] = 10), attempts to mass erase via the debug interface are blocked. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 195: Signal Multiplexing And Signal Descriptions
Table 10-1. Reference links to related information Topic Related module Reference Full description Port control Port control System memory map System memory map Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 196: Port Control And Interrupt Module Features
Drive strength PTB0/PTB1 only PTC3/PTC4 only PTD4/PTD5/PTD6/ enable control PTD7 only Drive strength Disabled Disabled Disabled Disabled Disabled enable at reset Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 197: Clock Gating
The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 198 VREFH VREFH VREFL VREFL VREFL VSSA VSSA VSSA VREF_OUT/ VREF_OUT/ VREF_OUT/ CMP1_IN5/ CMP1_IN5/ CMP1_IN5/ CMP0_IN5/ CMP0_IN5/ CMP0_IN5/ ADC1_SE18 ADC1_SE18 ADC1_SE18 DAC0_OUT/ DAC0_OUT/ DAC0_OUT/ CMP1_IN3/ CMP1_IN3/ CMP1_IN3/ ADC0_SE23 ADC0_SE23 ADC0_SE23 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 199 PTB0/ I2C0_SCL FTM1_CH0 FTM1_QD_ UART0_RX LLWU_P5 ADC1_SE8 ADC1_SE8 LLWU_P5 PTB1 ADC0_SE9/ ADC0_SE9/ PTB1 I2C0_SDA FTM1_CH1 FTM0_FLT2 EWM_IN FTM1_QD_ UART0_TX ADC1_SE9 ADC1_SE9 PTB2 ADC0_SE12 ADC0_SE12 PTB2 I2C0_SCL UART0_RTS_ FTM0_FLT1 FTM0_FLT3 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 200 ADC1_SE7b ADC1_SE7b PTC11/ I2C1_SDA FTM3_CH7 FB_RW_b LLWU_P11 LLWU_P11 — PTC12 DISABLED PTC12 FB_AD27 FTM3_FLT0 — PTC13 DISABLED PTC13 FB_AD26 — PTC14 DISABLED PTC14 FB_AD25 — PTC15 DISABLED PTC15 FB_AD24 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 201: Kv31F Pinouts
The following figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 202 PTE17 PTC0 PTE18 PTB19 PTE19 PTB18 ADC0_DP0/ADC1_DP3 PTB17 ADC0_DM0/ADC1_DM3 PTB16 ADC1_DP0/ADC0_DP3 PTB3 ADC1_DM0/ADC0_DM3 PTB2 VDDA PTB1 VREFH PTB0/LLWU_P5 VREFL RESET_b VSSA PTA19 Figure 10-2. KV31F 64 LQFP Pinout Diagram KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 203 PTB16 ADC0_DP1 ADC0_DM1 ADC1_DP1/ADC0_DP2 ADC1_DM1/ADC0_DM2 PTB11 PTB10 ADC0_DP0/ADC1_DP3 ADC0_DM0/ADC1_DM3 PTB9 PTB3 ADC1_DP0/ADC0_DP3 PTB2 ADC1_DM0/ADC0_DM3 PTB1 VDDA PTB0/LLWU_P5 VREFH RESET_b VREFL PTA19 VSSA Figure 10-3. KV31F 100 LQFP Pinout Diagram KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 204: Module Signal Description Tables
SWD_CLK Table 10-5. TPIU Signal Descriptions Chip signal name Module signal Description name TRACE_SWO JTAG_TDO/ Trace output data from the ARM CoreSight debug block over a TRACE_SWO single pin KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 205: System Modules
EZP_Q EzPort Serial Data Out Output Table 10-9. FlexBus Signal Descriptions Chip signal name Module signal Description name CLKOUT FB_CLK FlexBus Clock Output Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 206 The chip can extend this signal until the first positive clock edge after FB_CS asserts. See CSCR[EXTS] and Extended Transfer Start/Address Latch Enable. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 207 If bursting is used for a 32-bit write to an 8-bit port, FB_TSIZ1–FB_TSIZ0 are driven to 00b for the entire transfer. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 208: Analog
Chip signal name Module signal Description name ADC0_DP[3:0] DADP3–DADP0 Differential Analog Channel Inputs ADC0_DM[3:0] DADM3–DADM0 Differential Analog Channel Inputs ADC0_SEn Single-Ended Analog Channel Inputs Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 209 Module signal Description name CMP1_IN[5:0] IN[5:0] Analog voltage inputs CMP1_OUT CMPO Comparator output Table 10-14. DAC 0 Signal Descriptions Chip signal name Module signal Description name DAC0_OUT — DAC output KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 210: Timer Modules
External clock. FTM external clock can be selected to drive the FTM counter. FTM2_CH[1:0] FTM channel (n), where n can be 7-0 FTM2_FLT0 FAULTj Fault input (j), where j can be 3-0 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 211: Communication Interfaces
Peripheral Chip Selects 1–3 SPI0_PCS4 PCS4 Peripheral Chip Select 4 SPI0_PCS5 PCS5/ PCSS Peripheral Chip Select 5 /Peripheral Chip Select Strobe SPI0_SIN Serial Data In Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 212 Receive Data Table 10-28. UART 0 Signal Descriptions Chip signal name Module signal Description name UART0_CTS Clear to send UART0_RTS Request to send Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 213: Human-Machine Interfaces (Hmi)
PORTD31–PORTD0 General-purpose input/output PTE[31:0] PORTE31–PORTE0 General-purpose input/output 1. The available GPIO pins depends on the specific package. See the signal multiplexing section for which exact GPIO signals are available. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 214 Module Signal Description Tables KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 215: Port Control And Interrupts (Port)
• Support for interrupt or DMA request configured per pin • Asynchronous wake-up in low-power modes • Pin interrupt is functional in all digital pin muxing modes • Digital input filter on selected pins KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 216: Modes Of Operation
In Stop mode, the digital input filters are bypassed unless they are configured to run from the 1-kHz LPO clock source. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 217: External Signal Description
Any read or write access to the PORT memory space that is outside the valid memory map results in a bus error. All register accesses complete with zero wait states. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 218 11.5.2/226 reads 0) 4004_9084 Global Pin Control High Register (PORTA_GPCHR) (always 0000_0000h 11.5.3/227 reads 0) 4004_90A0 Interrupt Status Flag Register (PORTA_ISFR) 0000_0000h 11.5.4/228 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 219 See section 11.5.1/224 4004_A07C Pin Control Register n (PORTB_PCR31) See section 11.5.1/224 4004_A080 Global Pin Control Low Register (PORTB_GPCLR) (always 0000_0000h 11.5.2/226 reads 0) Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 220 Pin Control Register n (PORTC_PCR28) See section 11.5.1/224 4004_B074 Pin Control Register n (PORTC_PCR29) See section 11.5.1/224 4004_B078 Pin Control Register n (PORTC_PCR30) See section 11.5.1/224 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 221 4004_C064 Pin Control Register n (PORTD_PCR25) See section 11.5.1/224 4004_C068 Pin Control Register n (PORTD_PCR26) See section 11.5.1/224 4004_C06C Pin Control Register n (PORTD_PCR27) See section 11.5.1/224 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 222 4004_D058 Pin Control Register n (PORTE_PCR22) See section 11.5.1/224 4004_D05C Pin Control Register n (PORTE_PCR23) See section 11.5.1/224 4004_D060 Pin Control Register n (PORTE_PCR24) See section 11.5.1/224 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 223 4004_D0A0 Interrupt Status Flag Register (PORTE_ISFR) 0000_0000h 11.5.4/228 4004_D0C0 Digital Filter Enable Register (PORTE_DFER) 0000_0000h 11.5.5/228 4004_D0C4 Digital Filter Clock Register (PORTE_DFCR) 0000_0000h 11.5.6/229 4004_D0C8 Digital Filter Width Register (PORTE_DFWR) 0000_0000h 11.5.7/229 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 224: Pin Control Register N (Portx_Pcrn)
This read-only field is reserved and always has the value 0. Interrupt Status Flag The pin interrupt configuration is valid in all digital pin muxing modes. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 225 This read-only field is reserved and always has the value 0. Drive Strength Enable Drive strength configuration is valid in all digital pin muxing modes. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 226: Global Pin Control Low Register (Portx_Gpclr)
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 11.5.2 Global Pin Control Low Register (PORTx_GPCLR) Only 32-bit writes are supported to this register. Address: Base address + 80h offset GPWE GPWD Reset KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 227: Global Pin Control High Register (Portx_Gpchr)
Corresponding Pin Control Register is updated with the value in GPWD. 15–0 Global Pin Write Data GPWD Write value that is written to all Pin Control Registers bits [15:0] that are selected by GPWE. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 228: Interrupt Status Flag Register (Portx_Isfr)
The digital filter configuration is valid in all digital pin muxing modes. Address: Base address + C0h offset Reset PORTx_DFER field descriptions Field Description 31–0 Digital Filter Enable KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 229: Digital Filter Clock Register (Portx_Dfcr)
11.5.7 Digital Filter Width Register (PORTx_DFWR) This register is read only for ports that do not support a digital filter. The digital filter configuration is valid in all digital pin muxing modes. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 230: Functional Description
Pin Control register. For example, if an I C function is enabled on a pin, that does not override the pullup or open drain configuration for that pin. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 231: Global Pin Control
The external interrupt capability of the PORT module is available in all digital pin muxing modes provided the PORT module is enabled. Each pin can be individually configured for any of the following external interrupt modes: KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 232: Digital Filter
KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 233 The minimum latency through a digital filter equals two or three filter clock cycles plus the filter width configuration register. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 234 Functional description KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 235: System Integration Module (Sim)
• Architectural clock gating control • Flash and system RAM size configuration • FlexTimer external clock, hardware trigger, and fault source selection • UART0 and UART1 receive/transmit source selection/configuration KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 236: Memory Map And Register Definition
12.2.16/264 4004_8058 Unique Identification Register Mid-High (SIM_UIDMH) See section 12.2.17/264 4004_805C Unique Identification Register Mid Low (SIM_UIDML) See section 12.2.18/265 4004_8060 Unique Identification Register Low (SIM_UIDL) See section 12.2.19/265 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 237: System Options Register 1 (Sim_Sopt1)
ERCLK32K is output on PTE0. ERCLK32K is output on PTE26. Reserved. 15–12 RAM size RAMSIZE This field specifies the amount of system RAM available on the device. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 238: Sopt1 Configuration Register (Sim_Sopt1Cfg)
Reserved This read-only field is reserved and always has the value 0. 7–0 This field is reserved. Reserved This read-only field is reserved and always has the value 0. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 239: System Options Register 2 (Sim_Sopt2)
This read-only field is reserved and always has the value 0. This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 240 Reserved This read-only field is reserved and always has the value 0. 3–0 This field is reserved. Reserved This read-only field is reserved and always has the value 0. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 241: System Options Register 4 (Sim_Sopt4)
FTM1 channel match drives FTM0 hardware trigger 0 FlexTimer 3 External Clock Pin Select FTM3CLKSEL Selects the external pin used to drive the clock to the FTM3 module. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 242 FTM1CH0SRC Selects the source for FTM1 channel 0 input capture. NOTE: When the FTM is not in input capture mode, clear this field. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 243 NOTE: The pin source for fault 1 must be configured for the FTM module fault function through the appropriate pin control register in the port control module. FTM0_FLT1 pin CMP1 out FTM0 Fault 0 Select FTM0FLT0 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 244: System Options Register 5 (Sim_Sopt5)
UART1RXSRC Selects the source for the UART 1 receive data. UART1_RX pin CMP0 CMP1 Reserved 5–4 UART 1 transmit data source select UART1TXSRC Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 245: System Options Register 7 (Sim_Sopt7)
UART0_TX pin modulated with FTM1 channel 0 output UART0_TX pin modulated with FTM2 channel 0 output Reserved 12.2.6 System Options Register 7 (SIM_SOPT7) Address: 4004_7000h base + 1018h offset = 4004_8018h Reset ADC1TRGSEL ADC0TRGSEL Reset KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 246 This read-only field is reserved and always has the value 0. ADC0 pretrigger select ADC0PRETRGSEL Selects the ADC0 pre-trigger source when alternative triggers are enabled through ADC0ALTTRGEN. Pre-trigger A Pre-trigger B Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 247: System Options Register 8 (Sim_Sopt8)
12.2.7 System Options Register 8 (SIM_SOPT8) Address: 4004_7000h base + 101Ch offset = 4004_801Ch Reset Reset SIM_SOPT8 field descriptions Field Description FTM3 channel 7 output source FTM3OCH7SRC Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 248 FTM0_CH4 pin is output of FTM0 channel 4 output FTM0_CH4 pin is output of FTM0 channel 4 output, modulated by FTM1 channel 1 output FTM0 channel 3 output source FTM0OCH3SRC Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 249: System Device Identification Register (Sim_Sdid)
0 0 x* x* x* x* 1 1 x* x* x* x* Reset * Notes: • x = Undefined at reset. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 250 Pincount identification PINID Specifies the pincount of the device. 0000 Reserved 0001 Reserved 0010 32-pin 0011 Reserved 0100 48-pin 0101 64-pin 0110 80-pin Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 251: System Clock Gating Control Register 4 (Sim_Scgc4)
This bit controls the clock gate to the VREF module. Clock disabled Clock enabled Comparator Clock Gate Control This bit controls the clock gate to the comparator module. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 252 This read-only field is reserved and always has the value 0. EWM Clock Gate Control This bit controls the clock gate to the EWM module. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 253: System Clock Gating Control Register 5 (Sim_Scgc5)
Port D Clock Gate Control PORTD This bit controls the clock gate to the Port D module. Clock disabled Clock enabled Port C Clock Gate Control PORTC Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 254 This read-only field is reserved and always has the value 1. Low Power Timer Access Control LPTMR This bit controls software access to the Low Power Timer module. Access disabled Access enabled KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 255: System Clock Gating Control Register 6 (Sim_Scgc6)
This bit controls the clock gate to the FTM2 module. Clock disabled Clock enabled FTM1 Clock Gate Control FTM1 This bit controls the clock gate to the FTM1 module. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 256 This bit controls the clock gate to the SPI0 module. Clock disabled Clock enabled This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 257 This bit controls the clock gate to the flash memory. Flash reads are still supported while the flash memory is clock gated, but entry into low power modes and HSRUN mode is blocked. Clock disabled Clock enabled KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 258: System Clock Gating Control Register 7 (Sim_Scgc7)
The maximum divide ratio that can be programmed between core/system clock and the other divided clocks is divide by 8. When OUTDIV1 equals 0000 (divide by 1), the other dividers cannot be set higher than 0111 (divide by 8). KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 259 0000 or 0111 depending on FTF_FOPT[LPBOOT]. The bus clock frequency must be an integer divide of the core/system clock frequency. 0000 Divide-by-1. 0001 Divide-by-2. 0010 Divide-by-3. 0011 Divide-by-4. 0100 Divide-by-5. 0101 Divide-by-6. 0110 Divide-by-7. 0111 Divide-by-8. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 260 Divide-by-1. 0001 Divide-by-2. 0010 Divide-by-3. 0011 Divide-by-4. 0100 Divide-by-5. 0101 Divide-by-6. 0110 Divide-by-7. 0111 Divide-by-8. 1000 Divide-by-9. 1001 Divide-by-10. 1010 Divide-by-11. 1011 Divide-by-12. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 261: Flash Configuration Register 1 (Sim_Fcfg1)
12.2.14 Flash Configuration Register 1 (SIM_FCFG1) Address: 4004_7000h base + 104Ch offset = 4004_804Ch PFSIZE Reset Reset * Notes: • Reset value loaded during System Reset from Flash IFR. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 262 Flash accesses are disabled (and generate a bus error) and the Flash memory is placed in a low power state. This bit should not be changed during VLP modes. Relocate the interrupt vectors out of Flash memory before disabling the Flash. Flash is enabled Flash is disabled KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 263: Flash Configuration Register 2 (Sim_Fcfg2)
+ 0x4_0000. This would be the MAXADDR1 value for a device with 512 KB program flash memory across two flash blocks and no FlexNVM. 15–0 This field is reserved. Reserved This read-only field is reserved and always has the value 0. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 264: Unique Identification Register High (Sim_Uidh)
0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* Reset * Notes: • Reset value loaded during System Reset from Flash IFR. SIM_UIDMH field descriptions Field Description 31–0 Unique Identification Unique identification for the device. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 265: Unique Identification Register Mid Low (Sim_Uidml)
Reset value loaded during System Reset from Flash IFR. SIM_UIDL field descriptions Field Description 31–0 Unique Identification Unique identification for the device. 12.3 Functional description For more information about the functions of SIM, see the Introduction section. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 266 Functional description KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 267: Chip-Specific Information
The flashloader_loader program copies the contents of flashloader image from the flash to the on-chip RAM; the device then switches execution to the flashloader program to execute from RAM. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 268 Returns the contents of the IFR field or Flash firmware ID, by given offset, byte count and option WriteMemory Write data to memory ReadMemory Read data from memory Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 269: Functional Description
The following sub-sections describe the Kinetis Flashloader functionality. 13.3.1 Memory Maps While executing, the Kinetis Flashloader uses RAM memory. Available 0x2001_0000 Flashloader use 0x1FFF_8000 Figure 13-1. Kinetis Flashloader RAM Memory Map 13.3.2 Kinetis Flashloader KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 270: Start-Up Process
Property and Memory interfaces I2C1 entered Shutdown unused Enter flashloader Init UART1, interrupt state? Peripherals state machine SPI1, and I2C1 SPI1 entered interrupt state? Figure 13-2. Kinetis Flashloader Start-up Flowchart KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 271: Clock Configuration
The protocol for a command with no data phase contains: • Command packet (from host) • Generic response command packet (to host) Target Host Command Process command Response Figure 13-3. Command with No Data Phase KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 272 • Generic response command packet (to host) Target Host Command Process command Initial Response Data packet Process data Final data packet Process data Final Response Figure 13-4. Command with incoming data phase KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 273 The protocol for a command with an outgoing data phase contains: • Command packet (from host) • ReadMemory Response command packet (to host) (kCommandFlag_HasDataPhase set) • Outgoing data packets (to host) • Generic response command packet (to host) KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 274 • If the ReadMemory Response command packet prior to the start of the data phase does not contain the kCommandFlag_HasDataPhase flag, then the data phase is aborted. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 275: Flashloader Packet Types
A Ping packet must be sent before any other communications. In response to a Ping packet, the target sends a Ping Response packet. Table 13-3. Ping Packet Format Byte # Value Name 0x5A start byte 0xA6 ping KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 276 Ping response code Protocol bugfix Protocol minor Protocol major Protocol name = 'P' (0x50) Options low Options high CRC16 low CRC16 high The Serial Protocol Version number returned is 1.1.0. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 277 ^= byte << 8; for (i = 0; i < 8; ++i) uint32_t temp = crc << 1; if (crc & 0x8000) temp ^= 0x1021; crc = temp; KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 278 28 bytes for Parameters (Max 7 parameters) Flags Rsvd Param Param1 Param2 Param3 Param4 Param5 Param6 Param7 Count (32-bit) (32-bit) (32-bit) (32-bit) (32-bit) (32-bit) (32-bit) byte 0 byte 1 byte 2 byte 3 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 279 Kinetis Flashloader (target) returns to the 0xA7 GetPropertyResponse (used for sending host. The valid response tags are listed here. responses to GetProperty command only) 0xA3 ReadMemoryResponse (used for sending responses to ReadMemory command only) KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 280 (with generic response tag = 0xA0) and a list of parameters (defined in the next section). The parameter count field in the header is always set to 2, for status code and command tag parameters. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 281 Descripton 0 - 3 Status code The status of the associated Read Memory command. 4 - 7 Data byte count The number of bytes sent in the data phase. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 282: Flashloader Command Api
Flashloader, see Table 13-43. The 32-bit property tag is the only parameter required for GetProperty command. Table 13-16. Parameters for GetProperty Command Byte # Command 0 - 3 Property tag KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 283 0, followed by the property value(s). The next table shows an example of a GetPropertyResponse packet. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 284 The property tag and the new value to set are the 2 parameters required for the SetProperty command. Table 13-19. Parameters for SetProperty Command Byte # Command 0 - 3 Property tag 4 - 7 Property value KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 285 The SetProperty command has no data phase. Response: The target (Kinetis Flashloader) will return a GenericResponse packet with one of following status codes: Table 13-21. SetProperty Response Status Codes Status Code kStatus_Success kStatus_ReadOnly kStatus_UnknownProperty kStatus_InvalidArgument KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 286 0x5A packetType 0xA4, kFramingPacketType_Command length 0x04 0x00 crc16 0xC4 0x2E Command packet commandTag 0x01 - FlashEraseAll flags 0x00 reserved 0x00 parameterCount 0x00 The FlashEraseAll command has no data phase. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 287 Response: The target (Kinetis Flashloader ) will return a GenericResponse packet with one of following error status codes. Table 13-24. FlashEraseRegion Response Status Codes Status Code kStatus_Success (0) kStatus_MemoryRangeInvalid (10200) kStatus_FlashAlignmentError (101) kStatus_FlashAddressError (102) kStatus_FlashAccessError (103) kStatus_FlashProtectionViolation (104) kStatus_FlashCommandFailure (105) KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 288 Generic Response: 0x5a a4 0c 00 97 04 a0 00 00 02 00 00 00 00 05 00 00 00 ACK: 0x5a a1 Figure 13-10. Protocol Sequence for FillMemory Command KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 289 Table 13-27. Parameters for FlashProgramOnce Command Byte # Command 0 - 3 Index of program once field 4 - 7 Byte count 8 - 11 Data 12 - 16 Data KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 290 13.3.7.7 FlashReadOnce command The FlashReadOnce command returns the contents of the program once field by given index and byte count. The FlashReadOnce command uses 2 parameters: index and byteCount. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 291 Value Framing packet start byte 0x5A packetType 0xA4 length 0x0C 0x00 0xC1 0xA5 Command packet commandTag 0x0F – FlashReadOnce flags 0x00 reserved 0x00 parameterCount 0x02 index 0x0000_0000 byteCount 0x0000_0004 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 292 Start address of specific non-volatile memory to be read 4 - 7 byteCount Byte count to be read 8 - 11 option 0: IFR 1: Flash firmware ID KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 293 Framing packet start byte 0x5A packetType 0xA4 length 0x10 0x00 0xB3 0xCC Command packet commandTag 0x10 – FlashReadResource flags 0x00 reserved 0x00 parameterCount 0x03 startAddress 0x0000_0000 byteCount 0x0000_0008 option 0x0000_0001 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 294 When writing to RAM, the start address need not be aligned, and the data will not be padded. The start address and number of bytes are the 2 parameters required for WriteMemory command. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 295 Generic Response 0x5a a4 0c 00 23 72 a0 00 00 02 00 00 00 00 04 00 00 00 ACK: 0x5a a1 Figure 13-14. Protocol Sequence for WriteMemory Command KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 296 Table 13-37. Parameters for read memory command Byte Parameter Description Start address Start address of memory to read from Byte count Number of bytes to read and return to caller KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 297 Flashloader) works in slave mode, the host need pull data packets until the number of bytes of data specified in the byteCount parameter of ReadMemory command are received by host. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 298 Table 13-40. FlashSecurityDisable Command Packet Format (Example) FlashSecurityDisable Parameter Value Framing packet start byte 0x5A packetType 0xA4, kFramingPacketType_Command length 0x0C 0x00 crc16 0x43 0x7B Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 299 Response: The target (Kinetis Flashloader) will return a GenericResponse packet with status code either set to kStatus_Success for successful execution of the command, or set to an appropriate error status code. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 300 Response: The target (Kinetis Flashloader) will return a GenericResponse packet with a status code either set to kStatus_Success upon successful execution of the command, or set to an appropriate error status code. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 301: Flashloader Exit State
• UART and UART clock source (SIM_SOPT2_PLLFLLSEL = 3) • SPI • I2C You must re-configure the corresponding register to the expected value, instead of relying on the default value. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 302: Peripherals Supported
Read 1 byte of ping response packet from target Read 1 byte 0x5A 0x7A Report Error received? received? from target Figure 13-18. Host reads ping response from target via I2C KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 303: Spi Peripheral
Figure 13-20. Host reads response from target via I2C 13.4.2 SPI Peripheral The Kinetis Flashloader supports loading data into flash via the SPI peripheral, where the SPI peripheral serves as a SPI slave. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 304 Send 0x00 to 0x5A 0xA7 Report Error shift out 1 byte received? received? from target Figure 13-21. Host reads ping packet from target via SPI KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 305: Uart Peripheral
Figure 13-23. Host reads response from target via SPI 13.4.3 UART Peripheral The Kinetis Flashloader integrates an autobaud detection algorithm for the UART peripheral, thereby providing flexible baud rate choices. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 306 • How the host detects an ACK from the target • How the host detects a ping response from the target • How the host detects a command response from the target KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 307 0x5A 0xA7 Wait for 1 byte Report Error received? received? from target Figure 13-25. Host reads a ping response from target via UART KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 308: Get/Setproperty Command Properties
VerifyWrites feature is enabled by default. 0 - No verification is done. 1 - Enable verification. MaxPacketSize Maximum supported packet size for the currently active peripheral interface. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 309: Property Definitions
13.5.1 Property Definitions Get/Set property definitions are provided in this section. 13.5.1.1 CurrentVersion Property The value of this property is a 4-byte structure containing the current version of the flashloader. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 310 1. 1 is subtracted from the command tag because the lowest command tag value is 0x01. To get the bit mask for a given command, use this expression: mask = 1 << (tag - 1) Table 13-46. Command bits: [31:11] [10] KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 311: Kinetis Flashloader Status Error Codes
Memory range conflicts with a protected region. kStatus_UnknownProperty 10300 The requested property value is undefined. kStatus_ReadOnlyProperty 10301 The requested property value cannot be written. kStatus_InvalidPropertyValue 10302 The specified property value is invalid. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 312 Kinetis Flashloader Status Error Codes KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 313: Reset Control Module (Rcm)
System Reset Status Register 1 (RCM_SRS1) 14.2.2/315 4007_F004 Reset Pin Filter Control register (RCM_RPFC) 14.2.3/317 4007_F005 Reset Pin Filter Width register (RCM_RPFW) 14.2.4/318 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 314: System Reset Status Register 0 (Rcm_Srs0)
Indicates a reset has been caused by an active-low level on the external RESET pin. Reset not caused by external reset pin Reset caused by external reset pin Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 315: System Reset Status Register 1 (Rcm_Srs1)
The reset state of these bits depends on what caused the MCU to reset. NOTE The reset value of this register depends on the reset source: • POR (including LVD) — 0x00 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 316 Indicates a reset has been caused by the ARM core indication of a LOCKUP event. Reset not caused by core LOCKUP event Reset caused by core LOCKUP event Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 317: Reset Pin Filter Control Register (Rcm_Rpfc)
Selects how the reset pin filter is enabled in run and wait modes. All filtering disabled Bus clock filter enabled for normal operation LPO clock filter enabled for normal operation Reserved KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 318: Reset Pin Filter Width Register (Rcm_Rpfw)
Bus clock filter count is 22 10110 Bus clock filter count is 23 10111 Bus clock filter count is 24 11000 Bus clock filter count is 25 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 319: Mode Register (Rcm_Mr)
Reflects the state of the EZP_MS pin during the last Chip Reset Pin deasserted (logic 1) Pin asserted (logic 0) This field is reserved. Reserved This read-only field is reserved and always has the value 0. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 320: Sticky System Reset Status Register 0 (Rcm_Ssrs0)
Reset not caused by a loss of lock in the PLL Reset caused by a loss of lock in the PLL Sticky Loss-of-Clock Reset SLOC Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 321: Sticky System Reset Status Register 1 (Rcm_Ssrs1)
This field is reserved. Reserved This read-only field is reserved and always has the value 0. Sticky Stop Mode Acknowledge Error Reset SSACKERR Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 322 Sticky JTAG Generated Reset SJTAG Indicates a reset has been caused by JTAG selection of certain IR codes: EZPORT, EXTEST, HIGHZ, and CLAMP. Reset not caused by JTAG Reset caused by JTAG KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 323: System Mode Controller (Smc)
The WFI or WFE instruction is used to invoke Sleep and Deep Sleep modes. Run, Wait, and Stop are the common terms used for the primary operating modes of Freescale microcontrollers. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 324 The core, system, bus, and flash clock maximum frequencies are restricted in this mode. See the Power Management chapter for details about the maximum allowable frequencies. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 325: Memory Map And Register Descriptions
For more information about the types of reset on this chip, refer to the Reset section details. NOTE The SMC registers can be written only in supervisor mode. Write accesses in user mode are blocked and will result in a bus error. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 326: Power Mode Protection Register (Smc_Pmprot)
Chip Reset not VLLS. See the Reset section details for more information. Address: 4007_E000h base + 0h offset = 4007_E000h Read AHSRUN AVLP ALLS AVLLS Write Reset KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 327: Power Mode Control Register (Smc_Pmctrl)
(PMPROT) register. NOTE This register is reset on Chip POR not VLLS and by reset types that trigger Chip POR not VLLS. It is unaffected by reset types KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 328 NOTE: When set to STOP, the PSTOPO bits in the STOPCTRL register can be used to select a Partial Stop mode if desired. Normal Stop (STOP) Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 329: Stop Control Register (Smc_Stopctrl)
PSTOP2 - Partial Stop with system clock disabled and bus clock enabled Reserved POR Power Option PORPO This bit controls whether the POR detect circuit is enabled in VLLS0 mode. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 330: Power Mode Status Register (Smc_Pmstat)
Address: 4007_E000h base + 3h offset = 4007_E003h Read PMSTAT Write Reset SMC_PMSTAT field descriptions Field Description 7–0 Power Mode Status PMSTAT NOTE: When debug is enabled, the PMSTAT will not update to STOP or VLPS KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 331: Functional Description
15.4.1 Power mode transitions The following figure shows the power mode state transitions available on the chip. Any reset always brings the MCU back to the normal RUN state. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 332 WAIT Sleep-now or sleep-on-exit modes entered with SLEEPDEEP clear, controlled in System Control Register in ARM core. See note. WAIT Interrupt or Reset Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 333 VLLSx PMPROT[AVLLS]=1, PMCTRL[STOPM]=100, STOPCTRL[VLLSM]=x (VLLSx), Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 334: Power Mode Entry/Exit Sequencing
WFI instruction. After the instruction is executed, the following sequence occurs: 1. The CPU clock is gated off immediately. 2. Requests are made to all non-CPU bus masters to enter Stop mode. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 335 For wait modes (WAIT and VLPW), the CPU clock is gated off while all other clocking continues, as in RUN and VLPR mode operation. Some modules that support stop-in- wait functionality have their clocks disabled in these configurations. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 336: Run Modes
• The MCG must be configured in a mode which is supported during VLPR. See the Power Management details for information about these MCG modes. • All clock monitors in the MCG must be disabled. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 337 RUN mode. • Stop mode entry is not supported from HSRUN. • Modifications to clock gating control bits are prohibited. • Flash programming/erasing is not allowed. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 338: Wait Modes
SIM. VLPR mode restrictions also apply to VLPW. When an interrupt from VLPW occurs, the device returns to VLPR mode to execute the interrupt service routine. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 339: Stop Modes
STOP mode is entered via the sleep-now or sleep-on-exit with the SLEEPDEEP bit set in the System Control Register in the ARM core. The MCG module can be configured to leave the reference clocks running. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 340 In LLS, the on-chip voltage regulator is in stop regulation. Most of the peripherals are put in a state-retention mode that does not allow them to operate while in LLS. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 341 Before entering VLLS mode, the user should configure the Low-Leakage Wake-up (LLWU) module to enable the desired wakeup sources. The available wake-up sources in VLLS are detailed in the chip configuration details for this device. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 342: Debug In Low Power Modes
Reset Controller logic to hold the system in reset after the next recovery from a VLLS mode. This bit allows the debugger time to reinitialize the debug module before the debug session continues. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 343 The VLLDBGACK bit is cleared by the debugger (or can be left set as is) or clears automatically due to the reset generated as part of the next VLLS recovery. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 344 Functional description KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 345: Power Management Controller (Pmc)
(V ) or low (V ). The trip voltage is selected by LVDH LVDL LVDSC1[LVDV]. The LVD is disabled upon entering VLPx, LLS, and VLLSx modes. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 346: Lvd Reset Operation
LVD voltage. The LVW also has an interrupt, which is enabled by setting LVDSC2[LVWIE]. If enabled, an LVW interrupt request occurs when LVDSC2[LVWF] is set. LVDSC2[LVWF] is cleared by writing 1 to LVDSC2[LVWACK]. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 347: I/O Retention
Width Section/ address Register name Access Reset value (in bits) page (hex) Low Voltage Detect Status And Control 1 register 4007_D000 16.5.1/348 (PMC_LVDSC1) Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 348: Low Voltage Detect Status And Control 1 Register (Pmc_Lvdsc1)
PMC_LVDSC1 field descriptions Field Description Low-Voltage Detect Flag LVDF This read-only status field indicates a low-voltage detect event. Low-voltage event not detected Low-voltage event detected Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 349: Low Voltage Detect Status And Control 2 Register (Pmc_Lvdsc2)
LVWV is reset solely on a POR Only event. The other fields of the register are reset on Chip Reset Not VLLS. For more information about these reset types, refer to the Reset section details. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 350: Regulator Status And Control Register (Pmc_Regsc)
CMP and ADC. The internal regulator provides a status bit (REGONS) indicating the regulator is in run regulation. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 351 Regulator is in stop regulation or in transition to/from it Regulator is in run regulation This field is reserved. Reserved NOTE: This reserved bit must remain cleared (set to 0). Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 352 Memory map and register descriptions PMC_REGSC field descriptions (continued) Field Description Bandgap Buffer Enable BGBE Enables the bandgap buffer. Bandgap buffer not enabled Bandgap buffer enabled KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 353: Low-Leakage Wakeup Unit (Llwu)
LLS or VLLS. See the chip configuration information for wakeup input sources for this device. • External pin wake-up inputs, each of which is programmable as falling-edge, rising- edge, or any change KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 354: Modes Of Operation
When the wake-up pin filters are enabled, filter operation begins immediately. If a low leakage mode is entered within five LPO clock cycles of an active edge, the edge event will be detected by the LLWU. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 355: Block Diagram
Synchronizer Pin filter 2 detect reset flow WUPE15 FILT2[FILTSEL] LLWU_P15 Edge wakeup occurred detect External pin sources LLWU_P0 wakeup occurred Edge detect WUPE0 Figure 17-1. LLWU block diagram KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 356: Llwu Signal Descriptions
LLWU registers are unaffected by reset types that do not trigger Chip Reset not VLLS. For more information about the types of reset on this chip, refer to the Introduction details. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 357: Llwu Pin Enable 1 Register (Llwu_Pe1)
External input pin enabled with any change detection 5–4 Wakeup Pin Enable For LLWU_P2 WUPE2 Enables and configures the edge detection for the wakeup pin. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 358: Llwu Pin Enable 2 Register (Llwu_Pe2)
Enables and configures the edge detection for the wakeup pin. External input pin disabled as wakeup input External input pin enabled with rising edge detection Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 359: Llwu Pin Enable 3 Register (Llwu_Pe3)
Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 2h offset = 4007_C002h Read WUPE11 WUPE10 WUPE9 WUPE8 Write Reset KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 360: Llwu Pin Enable 4 Register (Llwu_Pe4)
This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 361: Llwu Module Enable Register (Llwu_Me)
LLWU_ME contains the bits to enable the internal module flag as a wakeup input source for inputs MWUF7–MWUF0. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 362 Enables an internal module as a wakeup source input. Internal module flag not used as wakeup source Internal module flag used as wakeup source Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 363: Llwu Flag 1 Register (Llwu_F1)
Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF6. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 364 Indicates that an enabled external wake-up pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF0. LLWU_P0 input was not a wakeup source LLWU_P0 input was a wakeup source KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 365: Llwu Flag 2 Register (Llwu_F2)
Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF13. LLWU_P13 input was not a wakeup source LLWU_P13 input was a wakeup source Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 366: Llwu Flag 3 Register (Llwu_F3)
CMP module, the flag from the associated peripheral is accessible as the MWUFx bit. The flag will need to be cleared in the peripheral instead of writing a 1 to the MWUFx bit. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 367 Module 3 input was not a wakeup source Module 3 input was a wakeup source Wakeup flag For module 2 MWUF2 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 368: Llwu Pin Filter 1 Register (Llwu_Filt1)
Indicates that the filtered external wakeup pin, selected by FILTSEL, was a source of exiting a low-leakage power mode. To clear the flag write a one to FILTF. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 369: Llwu Pin Filter 2 Register (Llwu_Filt2)
Indicates that the filtered external wakeup pin, selected by FILTSEL, was a source of exiting a low-leakage power mode. To clear the flag write a one to FILTF. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 370: Functional Description
5 cycles of delay before the detect circuit alerts the system to the wakeup or reset event when the filter function is enabled. Two wakeup detect filters are available for selected external pins. Glitch filtering is not provided on the internal modules. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 371: Lls Mode
LLWU flag from being falsely set when PMC_REGSC[ACKISO] is cleared. The signal selected as a wake-up source pin must be a digital pin, as selected in the pin mux control. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 372 Functional description KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 373: Miscellaneous Control Module (Mcm)
Crossbar Switch (AXBS) Slave Configuration E008_0008 001Fh 18.2.1/374 (MCM_PLASC) Crossbar Switch (AXBS) Master Configuration E008_000A 0017h 18.2.2/374 (MCM_PLAMC) E008_000C Crossbar Switch (AXBS) Control Register (MCM_PLACR) 0000_0000h 18.2.3/375 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 374: Crossbar Switch (Axbs) Slave Configuration (Mcm_Plasc)
PLAMC is a 16-bit read-only register identifying the presence/absence of bus master connections to the device's crossbar switch. Address: E008_0000h base + Ah offset = E008_000Ah Read Write Reset KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 375: Crossbar Switch (Axbs) Control Register (Mcm_Placr)
This read-only field is reserved and always has the value 0. Arbitration select Fixed-priority arbitration for the crossbar masters Round-robin arbitration for the crossbar masters 8–0 This field is reserved. Reserved KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 376: Interrupt Status And Control Register (Mcm_Iscr)
Address: E008_0000h base + 10h offset = E008_0010h Reserved Reset Reset MCM_ISCR field descriptions Field Description FPU input denormal interrupt enable FIDCE Disable interrupt Enable interrupt Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 377 FPU. Once set, this bit remains set until software clears the FPSCR[UFC] bit. No interrupt Interrupt occurred FPU overflow interrupt status FOFC Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 378 FPU. Once set, this bit remains set until software clears the FPSCR[IOC] bit. No interrupt Interrupt occurred 7–0 This field is reserved. Reserved This read-only field is reserved and always has the value 0. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 379: Compute Operation Control Register (Mcm_Cpo)
Compute operation entry has completed or compute operation exit has not completed. Compute Operation request CPOREQ This bit is auto-cleared by vector fetching if CPOWOI = 1. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 380: Functional Description
To determine the exact source of the interrupt qualify the interrupt status flags with the corresponding interrupt enable bits. 1. Form MCM_ISCR[31:16] && MCM_ISCR[15:0] 2. Search the result for asserted flags, which indicate the exact interrupt sources KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 381: Crossbar Switch Lite (Axbs-Lite)
• Allows concurrent accesses from different masters to different slaves • 32-bit data bus • Operation at a 1-to-1 clock frequency with the bus masters • Programmable configuration for fixed-priority or round-robin slave port arbitration KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 382: Memory Map / Register Definition
The master can also lose control of the slave port if another higher-priority master makes a request to the slave port. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 383: Arbitration
The following table describes possible scenarios based on the requesting master port: KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 384: Initialization/Application Information
(compared to fixed priority) as the fixed master priority does not affect the master selection. 19.4 Initialization/application information No initialization is required for the crossbar switch. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 385 Chapter 19 Crossbar Switch Lite (AXBS-Lite) See the AXBS section of the configuration chapter for the reset state of the arbitration scheme. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 386 Initialization/application information KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 387: Peripheral Bridge (Aips-Lite)
The peripheral bridge performs a bus protocol conversion of the master transactions and generates the following as inputs to the peripherals: • Module enables • Module addresses KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 388: Functional Description
All accesses to the peripheral slots must be sized less than or equal to the designated peripheral slot size. If an access is attempted that is larger than the targeted port, an error response is generated. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 389: Direct Memory Access Multiplexer (Dmamux)
21.1.1 Overview The Direct Memory Access Multiplexer (DMAMUX) routes DMA sources, called slots, to any of the 16 DMA channels. This process is illustrated in the following figure. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 390: Features
• Each channel router can be assigned to one of the possible peripheral DMA slots or to one of the always-on slots. 21.1.3 Modes of operation The following operating modes are available: • Disabled mode KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 391: External Signal Description
Channel Configuration register (DMAMUX_CHCFG5) 21.3.1/392 4002_1006 Channel Configuration register (DMAMUX_CHCFG6) 21.3.1/392 4002_1007 Channel Configuration register (DMAMUX_CHCFG7) 21.3.1/392 4002_1008 Channel Configuration register (DMAMUX_CHCFG8) 21.3.1/392 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 392: Channel Configuration Register (Dmamux_Chcfgn)
DMA channel. DMA channel is enabled DMA Channel Trigger Enable TRIG Enables the periodic trigger capability for the triggered DMA channel. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 393: Functional Description
Because of the dynamic nature of the system (due to DMA channel priorities, bus arbitration, interrupt service routine lengths, etc.), the number of clock cycles between a trigger and the actual DMA transfer cannot be guaranteed. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 394 This means that if a trigger is seen, but the peripheral is not requesting a transfer, then that trigger will be ignored. This situation is illustrated in the following figure. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 395: Dma Channels With No Triggering Capability
21.4.2 DMA channels with no triggering capability The other channels of the DMAMUX provide the normal routing functionality as described in Modes of operation. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 396: Always-Enabled Dma Sources
DMA registers after every minor loop. For this option, the DMA channel must be disabled in the DMA channel MUX. • Use an always-enabled DMA source. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 397: Initialization/Application Information
DMA channels that have triggering capability. To configure source #5 transmit for use with DMA channel 1, with periodic triggering capability: 1. Write 0x00 to CHCFG1 (base address + 0x01). KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 398 *CHCFG10= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000A); volatile unsigned char *CHCFG11= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000B); volatile unsigned char *CHCFG12= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000C); volatile unsigned char *CHCFG13= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000D); KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 399 *CHCFG12= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000C); volatile unsigned char *CHCFG13= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000D); volatile unsigned char *CHCFG14= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000E); volatile unsigned char *CHCFG15= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000F); KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 400 Initialization/application information In File main.c: #include "registers.h" *CHCFG8 = 0x00; *CHCFG8 = 0x87; KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 401: Enhanced Direct Memory Access (Edma)
• Local memory containing transfer control descriptors for each of the 16 channels 22.1.1 eDMA system block diagram Figure 22-1 illustrates the components of the eDMA system, including the eDMA module ("engine"). KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 402: Block Parts
22.1.2 Block parts The eDMA module is partitioned into two major modules: the eDMA engine and the transfer-control descriptor local memory. The eDMA engine is further partitioned into four submodules: KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 403 As noted earlier, in the event of simultaneous accesses, the eDMA engine is given priority and the peripheral transaction is stalled. Memory array TCD storage for each channel's transfer profile. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 404: Features
• Optional error terminations per channel and logically summed together to form one error interrupt to the interrupt controller • Optional support for scatter/gather DMA processing • Support for complex data structures KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 405: Modes Of Operation
The channel descriptors are stored in the local memory in sequential order: channel 0, channel 1, ... channel 15. Each TCDn definition is presented as 11 registers of 16 or 32 bits. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 406: Tcd Initialization
Memory map/register definition 22.3.2 TCD initialization Prior to activating a channel, you must initialize its TCD with the appropriate transfer profile. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 407: Tcd Structure
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 The fields implemented in Word 2 depend on whether DMA_CR[EMLM] is 0 or 1. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 408: Reserved Memory And Bit Fields
Channel n Priority Register (DMA_DCHPRI3) See section 22.3.17/445 4000_8101 Channel n Priority Register (DMA_DCHPRI2) See section 22.3.17/445 4000_8102 Channel n Priority Register (DMA_DCHPRI1) See section 22.3.17/445 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 409 4000_9020 TCD Source Address (DMA_TCD1_SADDR) Undefined 22.3.18/446 4000_9024 TCD Signed Source Address Offset (DMA_TCD1_SOFF) Undefined 22.3.19/446 4000_9026 TCD Transfer Attributes (DMA_TCD1_ATTR) Undefined 22.3.20/447 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 410 4000_9056 DMA_TCD2_CITER_ELINKNO Undefined 22.3.28/454 TCD Last Destination Address Adjustment/Scatter Gather 4000_9058 Undefined 22.3.29/455 Address (DMA_TCD2_DLASTSGA) 4000_905C TCD Control and Status (DMA_TCD2_CSR) Undefined 22.3.30/456 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 411 TCD Signed Minor Loop Offset (Minor Loop and Offset 4000_9088 Undefined 22.3.23/450 Enabled) (DMA_TCD4_NBYTES_MLOFFYES) TCD Last Source Address Adjustment 4000_908C Undefined 22.3.24/451 (DMA_TCD4_SLAST) 4000_9090 TCD Destination Address (DMA_TCD4_DADDR) Undefined 22.3.25/452 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 412 4000_90C4 TCD Signed Source Address Offset (DMA_TCD6_SOFF) Undefined 22.3.19/446 4000_90C6 TCD Transfer Attributes (DMA_TCD6_ATTR) Undefined 22.3.20/447 TCD Minor Byte Count (Minor Loop Disabled) 4000_90C8 Undefined 22.3.21/448 (DMA_TCD6_NBYTES_MLNO) Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 413 4000_90FC TCD Control and Status (DMA_TCD7_CSR) Undefined 22.3.30/456 TCD Beginning Minor Loop Link, Major Loop Count 4000_90FE (Channel Linking Enabled) Undefined 22.3.31/458 (DMA_TCD7_BITER_ELINKYES) Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 414 TCD Signed Destination Address Offset 4000_9134 Undefined 22.3.26/452 (DMA_TCD9_DOFF) TCD Current Minor Loop Link, Major Loop Count (Channel 4000_9136 Undefined 22.3.27/453 Linking Enabled) (DMA_TCD9_CITER_ELINKYES) Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 415 TCD Minor Byte Count (Minor Loop Disabled) 4000_9168 Undefined 22.3.21/448 (DMA_TCD11_NBYTES_MLNO) TCD Signed Minor Loop Offset (Minor Loop Enabled and 4000_9168 Undefined 22.3.22/449 Offset Disabled) (DMA_TCD11_NBYTES_MLOFFNO) Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 416 4000_919C TCD Control and Status (DMA_TCD12_CSR) Undefined 22.3.30/456 TCD Beginning Minor Loop Link, Major Loop Count 4000_919E (Channel Linking Enabled) Undefined 22.3.31/458 (DMA_TCD12_BITER_ELINKYES) Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 417 TCD Last Source Address Adjustment 4000_91CC Undefined 22.3.24/451 (DMA_TCD14_SLAST) 4000_91D0 TCD Destination Address (DMA_TCD14_DADDR) Undefined 22.3.25/452 TCD Signed Destination Address Offset 4000_91D4 Undefined 22.3.26/452 (DMA_TCD14_DOFF) Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 418: Control Register (Dma_Cr)
TCD Beginning Minor Loop Link, Major Loop Count 4000_91FE (Channel Linking Disabled) Undefined 22.3.32/459 (DMA_TCD15_BITER_ELINKNO) 22.3.1 Control Register (DMA_CR) The CR defines the basic operating configuration of the DMA. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 419 When minor loop mapping is disabled (EMLM is 0), all 32 bits of TCDn word2 are assigned to the NBYTES field. Address: 4000_8000h base + 0h offset = 4000_8000h Reset KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 420 Halt On Error Normal operation Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 421: Error Status Register (Dma_Es)
Address: 4000_8000h base + 4h offset = 4000_8004h Reset ERRCHN Reset DMA_ES field descriptions Field Description Logical OR of all ERR status bits Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 422 • TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or • TCDn_CITER[CITER] is equal to zero, or • TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 423: Enable Request Register (Dma_Erq)
Address: 4000_8000h base + Ch offset = 4000_800Ch Reset ERQ9 ERQ8 ERQ7 ERQ6 ERQ5 ERQ4 ERQ3 ERQ2 ERQ1 ERQ0 Reset KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 424 The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled Enable DMA Request 4 ERQ4 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 425: Enable Error Interrupt Register (Dma_Eei)
The DMA error indicator and the error interrupt enable flag must be asserted before an error interrupt request for a given channel is asserted to the interrupt controller. Address: 4000_8000h base + 14h offset = 4000_8014h Reset KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 426 The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error interrupt request Enable Error Interrupt 6 EEI6 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 427: Clear Enable Error Interrupt Register (Dma_Ceei)
If the NOP bit is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. Address: 4000_8000h base + 18h offset = 4000_8018h Read Write CAEE CEEI Reset KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 428: Set Enable Error Interrupt Register (Dma_Seei)
Sets All Enable Error Interrupts SAEE Set only the EEI bit specified in the SEEI field. Sets all bits in EEI 5–4 This field is reserved. Reserved Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 429: Clear Enable Request Register (Dma_Cerq)
Clear only the ERQ bit specified in the CERQ field Clear all bits in ERQ 5–4 This field is reserved. Reserved 3–0 Clear Enable Request CERQ Clears the corresponding bit in ERQ. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 430: Set Enable Request Register (Dma_Serq)
Set only the ERQ bit specified in the SERQ field Set all bits in ERQ 5–4 This field is reserved. Reserved 3–0 Set Enable Request SERQ Sets the corresponding bit in ERQ. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 431: Clear Done Status Bit Register (Dma_Cdne)
Clears only the TCDn_CSR[DONE] bit specified in the CDNE field Clears all bits in TCDn_CSR[DONE] 5–4 This field is reserved. Reserved 3–0 Clear DONE Bit CDNE Clears the corresponding bit in TCDn_CSR[DONE] KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 432: Set Start Bit Register (Dma_Ssrt)
Set only the TCDn_CSR[START] bit specified in the SSRT field Set all bits in TCDn_CSR[START] 5–4 This field is reserved. Reserved 3–0 Set START Bit SSRT Sets the corresponding bit in TCDn_CSR[START] KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 433: Clear Error Register (Dma_Cerr)
Clear only the ERR bit specified in the CERR field Clear all bits in ERR 5–4 This field is reserved. Reserved 3–0 Clear Error Indicator CERR Clears the corresponding bit in ERR KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 434: Clear Interrupt Request Register (Dma_Cint)
Clear only the INT bit specified in the CINT field Clear all bits in INT 5–4 This field is reserved. Reserved 3–0 Clear Interrupt Request CINT Clears the corresponding bit in INT KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 435: Interrupt Request Register (Dma_Int)
Reset DMA_INT field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 436 The interrupt request for corresponding channel is active Interrupt Request 4 INT4 The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 437: Error Register (Dma_Err)
A zero in any bit position has no affect on the corresponding channel’s current error status. The CERR is provided so the error indicator for a single channel can easily be cleared. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 438 An error in this channel has occurred Error In Channel 10 ERR10 An error in this channel has not occurred An error in this channel has occurred Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 439 An error in this channel has not occurred An error in this channel has occurred Error In Channel 0 ERR0 An error in this channel has not occurred An error in this channel has occurred KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 440: Hardware Request Status Register (Dma_Hrs)
31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Hardware Request Status Channel 15 HRS15 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 441 The HRS bit for its respective channel remains asserted for the period when a Hardware Request is Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically cleared by hardware. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 442 A hardware service request for channel 3 is not present A hardware service request for channel 3 is present Hardware Request Status Channel 2 HRS2 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 443: Enable Asynchronous Request In Stop Register (Dma_Ears)
Reset DMA_EARS field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 444 Enable asynchronous DMA request in stop mode for channel 4 EDREQ_4 Disable asynchronous DMA request for channel 4. Enable asynchronous DMA request for channel 4. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 445: Channel N Priority Register (Dma_Dchprin)
Channel n cannot be suspended by a higher priority channel’s service request. Channel n can be temporarily suspended by the service request of a higher priority channel. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 446: Tcd Source Address (Dma_Tcdn_Saddr)
22.3.19 TCD Signed Source Address Offset (DMA_TCDn_SOFF) Address: 4000_8000h base + 1004h offset + (32d × i), where i=0d to 15d Read SOFF Write Reset * Notes: • x = Undefined at reset. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 447: Tcd Transfer Attributes (Dma_Tcdn_Attr)
8-bit 16-bit 32-bit Reserved 16-byte 32-byte burst (4 beats of 64 bits) Reserved Reserved 7–3 Destination Address Modulo DMOD See the SMOD definition Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 448: Tcd Minor Byte Count (Minor Loop Disabled) (Dma_Tcdn_Nbytes_Mlno)
TCD memory. If the major iteration count is completed, additional processing is performed. NOTE: An NBYTES value of 0x0000_0000 is interpreted as a 4 GB transfer. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 449: (Dma_Tcdn_Nbytes_Mloffno)
The minor loop offset is applied to the SADDR Destination Minor Loop Offset enable DMLOE Selects whether the minor loop offset is applied to the destination address upon minor loop completion. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 450: (Dma_Tcdn_Nbytes_Mloffyes)
TCD_NBYTES_MLOFFNO register description. If minor loop mapping is disabled, then refer to the TCD_NBYTES_MLNO register description. Address: 4000_8000h base + 1008h offset + (32d × i), where i=0d to 15d MLOFF Reset MLOFF NBYTES Reset * Notes: KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 451: Tcd Last Source Address Adjustment (Dma_Tcdn_Slast)
This register uses two's complement notation; the overflow bit is discarded. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 452: Tcd Destination Address (Dma_Tcdn_Daddr)
DMA_TCDn_DOFF field descriptions Field Description 15–0 Destination Address Signed Offset DOFF Sign-extended offset applied to the current destination address to form the next-state value as each destination write is completed. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 453: Tcd Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (Dma_Tcdn_Citer_Elinkyes)
CITER field from the Beginning Iteration Count (BITER) field. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 454: Tcd Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (Dma_Tcdn_Citer_Elinkno)
It is decremented each time the minor loop is completed and updated in the transfer control descriptor memory. After the major iteration count is exhausted, the channel performs a number of operations, for Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 455: Tcd Last Destination Address Adjustment/Scatter Gather Address (Dma_Tcdn_Dlastsga)
This channel reload is performed as the major iteration count completes. The scatter/gather address must be 0-modulo-32-byte, otherwise a configuration error is reported. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 456: Tcd Control And Status (Dma_Tcdn_Csr)
The software clears it, or the hardware when the channel is activated. NOTE: This bit must be cleared to write the MAJORELINK or ESG bits. Channel Active ACTIVE Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 457 If this flag is set, the channel generates an interrupt request by setting the appropriate bit in the INT when the current major iteration count reaches zero. The end-of-major loop interrupt is disabled. The end-of-major loop interrupt is enabled. Channel Start START Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 458: Tcd Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (Dma_Tcdn_Biter_Elinkyes)
If channel-to-channel linking is enabled (ELINK = 1), then after the minor loop is exhausted, the eDMA engine initiates a channel service request at the channel defined by this field by setting that channel’s TCDn_CSR[START] bit. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 459: Tcd Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (Dma_Tcdn_Biter_Elinkno)
As the major iteration count is exhausted, the contents of this field are reloaded into the CITER field. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 460: Functional Description
22.4.1 eDMA basic data flow The basic flow of a data transfer can be partitioned into three segments. As shown in the following diagram, the first segment involves the channel activation: KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 461 The following diagram illustrates the second part of the basic data flow: KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 462 (if scatter/ gather is enabled). The updates to the TCD memory and the assertion of an interrupt request are shown in the following diagram. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 463: Fault Reporting And Handling
Each of these possible causes are detailed below: • The addresses and offsets must be aligned on 0-modulo-transfer-size boundaries. • The minor loop byte count must be a multiple of the source and destination transfer sizes. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 464 DMA_ES[ERRCHN] and ECX and VLD are set. In addition, an error interrupt may be generated if enabled. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 465: Channel Preemption
22.4.4 Performance This section addresses the performance of the eDMA module, focusing on two separate metrics: KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 466 32-bit transfer sizes are used. In all cases, the transfer rate includes the time to read the source plus the time to write the destination. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 467 The TCDn word 7 is read and checked for channel linking or scatter/gather requests. The appropriate fields in the first part of the TCDn are written back into the local memory. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 468 Channel startup (4 cycles) read_ws Wait states seen during the system bus read data phase write_ws Wait states seen during the system bus write data phase exit Channel shutdown (3 cycles) KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 469 This allows the link channel or the scatter/gather channel to be eligible and considered in the arbitration pool for next channel selection. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 470: Initialization/Application Information
If the major loop is exhausted, further post processing executes, such as interrupts, major loop channel linking, and scatter/gather operations, if enabled. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 471 (CITER) DMA request DMA request DMA request Figure 22-293. Example of multiple loop iterations The following figure lists the memory array terms and how the TCD settings interrelate. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 472: Programming Errors
The hardware service request handshake signals, error interrupts, and error reporting is associated with the selected channel. 22.5.3 Arbitration mode considerations This section discusses arbitration considerations for the eDMA. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 473: Performing Dma Transfers
TCDn_CSR[INT_MAJ] = 1 TCDn_CSR[START] = 1 (Should be written last after all other fields have been initialized) All other TCDn fields = 0 This generates the following event sequence: KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 474 The eDMA is programmed for two iterations of the major loop transferring 16 bytes per iteration. After the channel's hardware requests are enabled in the ERQ register, the slave device initiates channel service requests. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 475 9. Second hardware, that is, eDMA peripheral, requests channel service. 10. The channel is selected by arbitration for servicing. 11. eDMA engine writes: TCDn_CSR[DONE] = 0, TCDn_CSR[START] = 0, TCDn_CSR[ACTIVE] = 1. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 476 All upper address bits remain the same as in the original value. A setting of 0 for this field disables the modulo feature. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 477: Monitoring Transfer Descriptor Status
START ACTIVE DONE Channel service request via software Channel is executing Channel has completed the minor loop and is idle Channel has completed the major loop and is idle KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 478 Channel priorities are treated as equal, that is, constantly rotating, when Round-Robin Arbitration mode is selected. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 479: Channel Linking
TCDn_CITER[CITER] field uses a 15-bit vector to form the current iteration count. The bits associated with the TCDn_CITER[LINKCH] field are concatenated onto the CITER value to increase the range of the CITER. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 480: Dynamic Programming
Dynamic channel linking is the process of setting the TCD.major.e_link bit during channel execution. This bit is read from the TCD local memory at the end of channel execution, thus allowing the user to enable the feature during channel execution. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 481 The TCD.e_sg would be set in the programmer’s model, but it would be unclear whether the actual scatter/gather request was honored before the channel retired. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 482 If e_sg = 1b, the dynamic link attempt was successful. If e_sg = 0b and the major.linkch (ID) did not change, the attempted dynamic link did not succeed (the channel was already retiring). KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 483 (the channel was already retiring). If e_sg = 0b and the dlast_sga changed, the dynamic link attempt was successful (the new TCD’s e_sg value cleared the e_sg bit). KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 484 Initialization/application information KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 485: External Watchdog Monitor (Ewm)
23.1.1 Features Features of EWM module include: • Independent LPO clock source • Programmable time-out period specified in terms of number of EWM LPO clock cycles. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 486: Modes Of Operation
15 (EWM_service_time) peripheral bus clocks after exiting from stop mode. User must mask all interrupts prior to executing EWM service instructions. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 487: Block Diagram
EWM enable Counter >Compare High EWM Out Counter < Compare Low Logic EWM_out ((EWM_in ^ assert_in) || ~EWM_in_enable) Compare High > Counter > Compare Low Figure 23-1. EWM Block Diagram KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 488: Ewm Signal Descriptions
INEN, ASSIN and EWMEN bits can be written once after a CPU reset. Modifying these bits more than once, generates a bus transfer error. Address: 4006_1000h base + 0h offset = 4006_1000h Read INTEN INEN ASSIN EWMEN Write Reset KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 489: Service Register (Ewm_Serv)
23.3.3 Compare Low Register (EWM_CMPL) The CMPL register is reset to zero after a CPU reset. This provides no minimum time for the CPU to service the EWM counter. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 490: Compare High Register (Ewm_Cmph)
7–0 To prevent runaway code from changing this field, software should write to this field after a CPU reset COMPAREH even if the (default) maximum service time is required. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 491: Clock Prescaler Register (Ewm_Clkprescaler)
The EWM_out signal remains deasserted when the EWM is being regularly serviced by the CPU within the programmable service window, indicating that the application code is executed as expected. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 492: The Ewm_In Signal
(setting the CTRL[INEN] bit), the EWM_in signal must be in the deasserted state prior to the CPU servicing the EWM. This ensures that the EWM_out stays in the deasserted state; otherwise, the EWM_out pin is asserted. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 493: Ewm Counter
EWM Service Register. The CPU must access the EWM service register with correct write of unique data within the windowed time frame as determined by the CMPL and CMPH registers. Therefore, three possible conditions can occur: KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 494: Ewm Interrupt
CLKPRESCALER[CLK_DIV]. This divided clock is used to run the EWM counter. NOTE The divided clock used to run the EWM counter must be no more than half the frequency of the bus clock. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 495: Watchdog Timer (Wdog)
• External system clock • Unlock sequence for allowing updates to write-once WDOG control/configuration bits. • All WDOG control/configuration bits are writable once only within 256 bus clock cycles of being unlocked. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 496 • Count of WDOG resets as they occur. • Configurable interrupt on time-out to provide debug breadcrumbs. This is followed by a reset after 256 bus clock cycles. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 497: Functional Overview
CPU clock stopping or a run-away condition in code execution. In its simplest form, the watchdog timer runs continuously off a clock source and expects KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 498: Unlocking And Updating The Watchdog
After the update window closes, the watchdog timer restarts and the watchdog functions according to the new configuration. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 499: Watchdog Configuration Time (Wct)
2xWCT + 20 bus clock cycles. Therefore, it must be ensured that the time-out value for the watchdog is always greater than 2xWCT time + 20 bus clock cycles. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 500: Refreshing The Watchdog
In this mode, the watchdog timer cannot be refreshed–there is no requirement to do so while the timer is disabled. However, the watchdog still generates a reset, or interrupt-then-reset if enabled, on a non- KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 501: Debug Modes Of Operation
After it is set, this test-disable bit can only be cleared by a reset. These two tests achieve the overall aim of testing the counter functioning and the compare and reset logic. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 502: Quick Test
The following figure explains the splitting concept: KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 503: Backup Reset Generator
Two successive timer time-outs without an intervening system reset result in the backup reset generator routing out the time-out signal as a reset to the system. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 504: Generated Resets And Interrupts
Also, jobs such as counting the number of watchdog resets would not be done. 24.7 Memory map and register definition This section consists of the memory map and register descriptions. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 505: Watchdog Status And Control Register High (Wdog_Stctrlh)
WDOG functional test mode is disabled permanently until reset. 13–12 This 2-bit field selects the byte to be tested when the watchdog is in the byte test mode. BYTESEL[1:0] Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 506 Selects clock source for the WDOG timer and other internal timing operations. CLKSRC WDOG clock sourced from LPO . WDOG clock sourced from alternate clock source. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 507: Watchdog Status And Control Register Low (Wdog_Stctrll)
Field Description 15–0 Defines the upper 16 bits of the 32-bit time-out value for the watchdog timer. It is defined in terms of cycles TOVALHIGH of the watchdog clock. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 508: Watchdog Time-Out Value Register Low (Wdog_Tovall)
A refresh outside this window resets the system or if IRQRSTEN is set, it interrupts and then resets the system. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 509: Watchdog Window Register Low (Wdog_Winl)
20 bus cycles, resets the system, or if IRQRSTEN is set, it interrupts and then resets the system. 24.7.8 Watchdog Unlock register (WDOG_UNLOCK) Address: 4005_2000h base + Eh offset = 4005_200Eh Read WDOGUNLOCK Write Reset KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 510: Watchdog Timer Output Register High (Wdog_Tmrouth)
Address: 4005_2000h base + 12h offset = 4005_2012h Read TIMEROUTLOW Write Reset WDOG_TMROUTL field descriptions Field Description 15–0 Shows the value of the lower 16 bits of the watchdog timer. TIMEROUTLOW KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 511: Watchdog Reset Count Register (Wdog_Rstcnt)
When performing 8-bit accesses to the watchdog's 16-bit registers where the intention is to access both the bytes of a register, place the two 8-bit accesses one after the other in your code. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 512: Refresh And Unlock Operations With 8-Bit Access
16-bit value is correctly written, write4. Hence, the requirement of writing value2 of the sequence within 20 bus clock cycles of value1 is checked by measuring the gap between write2 and write4. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 513: Restrictions On Watchdog Operation
• The time-out value of the watchdog should be set to a minimum of four watchdog clock cycles. This is to take into account the delay in new settings taking effect in the watchdog clock domain. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 514 If the second refresh value is not written within 20 bus cycles of the first value, the system is reset, or interrupt-then- reset if enabled. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 515: Multipurpose Clock Generator (Mcg)
• Option to program and maximize DCO output frequency for a low frequency external reference clock source. • Option to prevent FLL from resetting its current locked frequency when switching clock modes if FLL reference frequency is not changed. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 516 • External clock monitor with reset and interrupt request capability to check for external clock failure when running in FBE, PEE, BLPE, or FEE modes • Lock detector with interrupt request capability for use with the PLL KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 517 • MCG Fixed Frequency Clock (MCGFFCLK) is provided as a clock source for other on-chip peripherals • MCG Internal Reference Clock (MCGIRCLK) is provided as a clock source for other on-chip peripherals This figure presents the block diagram of the MCG module. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 518 Filter /(24,25,26..55) Multipurpose Clock Generator (MCG) Figure 25-1. Multipurpose Clock Generator (MCG) block diagram NOTE Refer to the chip configuration chapter to identify the oscillator used in this MCU. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 519: Modes Of Operation
MCG Auto Trim Compare Value High Register 4006_400A 25.3.9/530 (MCG_ATCVH) MCG Auto Trim Compare Value Low Register 25.3.10/ 4006_400B (MCG_ATCVL) 25.3.11/ 4006_400C MCG Control 7 Register (MCG_C7) 25.3.12/ 4006_400D MCG Control 8 Register (MCG_C8) KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 520: Mcg Control 1 Register (Mcg_C1)
MCGIRCLK active. Internal Reference Stop Enable IREFSTEN Controls whether or not the internal reference clock remains enabled when the MCG enters Stop mode. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 521: Mcg Control 2 Register (Mcg_C2)
EREFS Selects the source for the external reference clock. See the Oscillator (OSC) chapter for more details. External reference clock requested. Oscillator requested. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 522: Mcg Control 3 Register (Mcg_C3)
If an SCTRIM value stored in nonvolatile memory is to be used, it is your responsibility to copy that value from the nonvolatile memory location to this register. 1. A value for SCTRIM is loaded during reset from a factory programmed location. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 523: Mcg Control 4 Register (Mcg_C4)
DRST field does not update immediately after a write to the DRS field due to internal synchronization between clock domains. See the DCO Frequency Range table for more details. Encoding 0 — Low range (reset default). Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 524: Mcg Control 5 Register (Mcg_C5)
OSCINIT 0 bit should be checked to make sure it is set. MCGPLLCLK is inactive. MCGPLLCLK is active. PLL Stop Enable PLLSTEN0 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 525: Mcg Control 6 Register (Mcg_C6)
Address: 4006_4000h base + 5h offset = 4006_4005h Read LOLIE0 PLLS CME0 VDIV0 Write Reset MCG_C6 field descriptions Field Description Loss of Lock Interrrupt Enable LOLIE0 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 526 11000 00001 01001 10001 11001 00010 01010 10010 11010 00011 01011 10011 11011 00100 01100 10100 11100 00101 01101 10101 11101 00110 01110 10110 11110 00111 01111 10111 11111 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 527: Mcg Status Register (Mcg_S)
IREFS bit due to internal synchronization between clock domains. Source of FLL reference clock is the external reference clock. Source of FLL reference clock is the internal reference clock. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 528: Mcg Status And Control Register (Mcg_Sc)
Writing to C1, C3, C4, and SC registers or entering Stop mode aborts the auto trim operation and clears this bit. Auto Trim Machine disabled. Auto Trim Machine enabled. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 529 CME0 is set. This bit is cleared by writing a logic 1 to it when set. Loss of OSC0 has not occurred. Loss of OSC0 has occurred. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 530: Mcg Auto Trim Compare Value High Register (Mcg_Atcvh)
Values are used by Auto Trim Machine to compare and adjust Internal Reference trim values during ATM SAR conversion. 25.3.11 MCG Control 7 Register (MCG_C7) Address: 4006_4000h base + Ch offset = 4006_400Ch Read OSCSEL Write Reset KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 531: Mcg Control 8 Register (Mcg_C8)
Enables the loss of clock monitoring circuit for the output of the RTC external reference clock. The LOCRE1 bit will determine whether an interrupt or a reset request is generated following a loss of RTC Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 532: Functional Description
25.4.1 MCG mode state diagram The nine states of the MCG are shown in the following figure and are described in Table 25-16. The arrows indicate the permitted MCG mode transitions. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 533 2’b10. 25.4.1.1 MCG modes of operation The MCG operates in one of the following modes. Note The MCG restricts transitions between modes. For the permitted transitions, see Figure 25-14. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 534 C4[DRST_DRS] and C4[DMX32] bits, times the internal reference frequency. See the C4[DMX32] bit description for more details. In FBI mode, the PLL is disabled in a low-power state unless C5[PLLCLKEN] is set . Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 535 [PRDIV]. In preparation for transition to PEE, the PLL's programmable reference divider must be configured to produce a valid PLL reference clock. The FLL is disabled in a low- power state. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 536 (C2[IRCS]=1). After it enters VLPR mode, writes to any of the MCG control registers that can cause an MCG clock mode switch to a non low power clock mode must be avoided. NOTE For the chip-specific modes of operation, see the power management chapter of this MCU. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 537: Low-Power Bit Usage
FRDIV factors) or the slow internal reference clock (32 kHz IRC). The IRCS clock frequency can be re-targeted by trimming the period of its IRCS selected internal reference clock. This can be done by writing a new trim value to the KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 538: External Reference Clock
Crystal Oscillator, divided by the FLL reference clock divider. The source of MCGFFCLK is selected by C1[IREFS]. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 539: Mcg Pll Clock
ATM uses a pulse that is generated by the ATM selected IRC clock to enable a counter that counts number of ATM external clocks. At end of each trim bit, KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 540: Initialization / Application Information
The internal reference will stabilize in t microseconds before the FLL can acquire irefsts lock. As soon as the internal reference is stable, the FLL will acquire lock in t fll_acquire milliseconds. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 541 2'b10 indicating the external reference clock has been appropriately selected. Although the FLL is bypassed, it is still on in FBE mode. 4. Write to the C4 register to determine the DCO output (MCGFLLCLK) frequency range. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 542 2. Wait for S[CLKST] bits in the MCG status register to change to 2'b01, indicating that the internal reference clock has been appropriately selected. 3. Write to the C2 register to determine the IRCS output (IRCSCLK) frequency range. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 543: Using A 32.768 Khz Reference
In FBE, FEE, FBI, and FEI modes, at any time, the application can switch the FLL multiplication factor between 640, 1280, 1920, and 2560 with C4[DRST_DRS] bits. Writes to C4[DRST_DRS] bits will be ignored if C2[LP]=1. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 544 1. First, FEI must transition to FBE mode: a. C2 = 0x2C • C2[RANGE] set to 2'b01 because the frequency of 4 MHz is within the high frequency range. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 545 = 48 MHz. In BLPE mode, the configuration of the VDIV bits does not matter because the PLL is disabled. Changing them only sets up the multiply value for PLL usage in PBE mode. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 546 Loop until S[CLKST] are 2'b11, indicating that the PLL output is selected to feed MCGOUTCLK in the current clock mode. • Now, with PRDIV of divide-by-2, and C6[VDIV] of multiply-by-24, MCGOUTCLK = [(4 MHz / 2) * 24] = 48 MHz. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 547 Chapter 25 Multipurpose Clock Generator (MCG) Figure 25-15. Flowchart of FEI to PEE mode transition using an 4 MHz crystal KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 548 PLLS clock is the FLL. 3. Next, FBE mode transitions into FBI mode: a. C1 = 0x54 • C1[CLKS] set to 2'b01 to switch the system clock to the internal reference clock. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 549 • C2[LP] is 1 • C2[RANGE], C2[HGO], C2[EREFS], C1[IRCLKEN], and C1[IREFSTEN] bits are ignored when the C1[IREFS] bit is set. They can remain set, or be cleared at this point. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 550 BLPE MODE ? BLPE MODE ? (C2[LP]=1) CONTINUE IN BLPI MODE C2 = 0x1C (C2[LP] = 0) Figure 25-16. Flowchart of PEE to BLPI mode transition using an 4 MHz crystal KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 551 At this point, by default, the C4[DRST_DRS] bits are set to 2'b00 and C4[DMX32] is cleared to 0. If the MCGOUTCLK frequency of 40 MHz is desired instead, set the C4[DRST_DRS] bits to 0x01 to switch the FLL KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 552 S[CLKST] = %00? C1 = 0x10 CONTINUE IN FEE MODE CHECK S[OSCINIT] = 1 ? Figure 25-17. Flowchart of BLPI to FEE mode transition using an 4 MHz crystal KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 553: Oscillator (Osc)
• Optionally external input bypass clock from EXTAL signal directly • One clock for MCU clock system • Two clocks for on-chip peripherals that can work in Stop modes Functional Description describes the module's operation in more detail. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 554: Block Diagram
OSCCLK OSC clock selection logic STOP Figure 26-1. OSC Module Block Diagram 26.4 OSC Signal Descriptions The table found here shows the user-accessible signals available for the OSC module. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 555: External Crystal / Resonator Connections
2. With the low-power mode, the oscillator has the internal feedback resistor R . Therefore, the feedback resistor must not be externally with the Connection 3. XTAL EXTAL Crystal or Resonator Figure 26-2. Crystal/Ceramic Resonator Connections - Connection 1 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 556: External Clock Connections
In external clock mode, the pins can be connected as shown in the figure found here. NOTE XTAL can be used as a GPIO when the GPIO alternate function is configured for it. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 557: Memory Map/Register Definitions
Address: 4006_5000h base + 0h offset = 4006_5000h Read ERCLKEN EREFSTEN SC2P SC4P SC8P SC16P Write Reset KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 558 Add 8 pF capacitor to the oscillator load. Oscillator 16 pF Capacitor Load Configure SC16P Configures the oscillator load. Disable the selection. Add 16 pF capacitor to the oscillator load. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 559: Functional Description
26.8.1 OSC module states The states of the OSC module are shown in the following figure. The states and their transitions between each other are described in this section. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 560 MCU, refer to the chip configuration details. The EXTAL and XTAL pins are also decoupled from all other oscillator circuitry in this state. The OSC module circuitry is configured to draw minimal current. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 561: Osc Module Modes
(MCG, Timer, and so on) is configured to use the oscillator output clock (OSC_CLK_OUT). Table 26-6. Oscillator modes Mode Frequency Range Low-frequency, high-gain (32.768 kHz) up to f (39.0625 kHz) osc_lo osc_lo Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 562 (not sensitive to the DC level of EXTAL). Also in this mode, all external components except for the resonator itself are integrated, which includes the load capacitors and feeback resistor that biases EXTAL. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 563: Counter
There is no reset state associated with the OSC module. The counter logic is reset when the OSC is not configured to generate clocks. There are no sources of reset requests for the OSC module. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 564: Low Power Modes Operation
OSC is still functional in these modes. After waking up from Very Low Leakage Stop (VLLSx) modes, all OSC register bits are reset and initialization is required through software. 26.11 Interrupts The OSC module does not generate any interrupts. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 565: Flash Memory Controller (Fmc)
64-bit flash memory location, and both a 4-way, 8-set cache and a single-entry 64-bit buffer can store previously accessed flash memory data for quick access times. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 566: Features
The programming model consists of the FMC control registers and the program visible cache (data and tag/valid entries). NOTE Program the registers only while the flash controller is idle (for example, execute from RAM). Changing configuration settings KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 567 [63:32] of data entry way 1, and U and L represent upper and set 0, and DATAW1S0L lower word, respectively. represents bits [31:0] of data entry way 1, set 0. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 568 Cache Data Storage (upper word) (FMC_DATAW0S0U) 0000_0000h 27.4.8/583 4001_F204 Cache Data Storage (lower word) (FMC_DATAW0S0L) 0000_0000h 27.4.9/584 4001_F208 Cache Data Storage (upper word) (FMC_DATAW0S1U) 0000_0000h 27.4.8/583 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 569 4001_F26C Cache Data Storage (lower word) (FMC_DATAW1S5L) 0000_0000h 27.4.10/ 4001_F270 Cache Data Storage (upper word) (FMC_DATAW1S6U) 0000_0000h 27.4.11/ 4001_F274 Cache Data Storage (lower word) (FMC_DATAW1S6L) 0000_0000h Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 570 4001_F2C4 Cache Data Storage (lower word) (FMC_DATAW3S0L) 0000_0000h 27.4.14/ 4001_F2C8 Cache Data Storage (upper word) (FMC_DATAW3S1U) 0000_0000h 27.4.15/ 4001_F2CC Cache Data Storage (lower word) (FMC_DATAW3S1L) 0000_0000h Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 571: Flash Access Protection Register (Fmc_Pfapr)
4001_F2FC Cache Data Storage (lower word) (FMC_DATAW3S7L) 0000_0000h 27.4.1 Flash Access Protection Register (FMC_PFAPR) Address: 4001_F000h base + 0h offset = 4001_F000h Reserved Reset M7AP[1:0] M6AP[1:0] M5AP[1:0] M4AP[1:0] M3AP[1:0] M2AP[1:0] M1AP[1:0] M0AP[1:0] Reset KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 572 This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits. Prefetching for this master is enabled. Prefetching for this master is disabled. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 573 No access may be performed by this master Only read accesses may be performed by this master Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 574 Only read accesses may be performed by this master Only write accesses may be performed by this master Both read and write accesses may be performed by this master KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 575: Flash Bank 0 Control Register (Fmc_Pfb0Cr)
Cache way is unlocked and may be displaced Cache way is locked and its contents are not displaced 23–20 Cache Invalidate Way x CINV_WAY[3:0] Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 576 Do not cache data references. Cache data references. Bank 0 Instruction Cache Enable B0ICE This bit controls whether instruction fetches are loaded into the cache. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 577 1's cache. A high-to-low transition of this enable forces the page buffer to be invalidated. Single entry buffer is disabled. Single entry buffer is enabled. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 578: Flash Bank 1 Control Register (Fmc_Pfb1Cr)
This read-only field is reserved and always has the value 0. 18–17 Bank 1 Memory Width B1MW[1:0] This read-only field defines the width of the bank 1 memory. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 579 0's cache. A high-to-low transition of this enable forces the page buffer to be invalidated. Single entry buffer is disabled. Single entry buffer is enabled. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 580: Cache Tag Storage (Fmc_Tagvdw0Sn)
14-bit tag for cache entry tag[18:5] 4–1 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 1-bit valid for cache entry valid KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 581: Cache Tag Storage (Fmc_Tagvdw1Sn)
14-bit tag for cache entry tag[18:5] 4–1 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 1-bit valid for cache entry valid KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 582: Cache Tag Storage (Fmc_Tagvdw2Sn)
14-bit tag for cache entry tag[18:5] 4–1 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 1-bit valid for cache entry valid KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 583: Cache Tag Storage (Fmc_Tagvdw3Sn)
This section represents data for the upper word (bits [63:32]) of all sets in the indicated way. Address: 4001_F000h base + 200h offset + (8d × i), where i=0d to 7d data[63:32] Reset KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 584: Cache Data Storage (Lower Word) (Fmc_Dataw0Snl)
This section represents data for the upper word (bits [63:32]) of all sets in the indicated way. Address: 4001_F000h base + 240h offset + (8d × i), where i=0d to 7d data[63:32] Reset KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 585: Cache Data Storage (Lower Word) (Fmc_Dataw1Snl)
This section represents data for the upper word (bits [63:32]) of all sets in the indicated way. Address: 4001_F000h base + 280h offset + (8d × i), where i=0d to 7d data[63:32] Reset KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 586: Cache Data Storage (Lower Word) (Fmc_Dataw2Snl)
This section represents data for the upper word (bits [63:32]) of all sets in the indicated way. Address: 4001_F000h base + 2C0h offset + (8d × i), where i=0d to 7d data[63:32] Reset KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 587: Cache Data Storage (Lower Word) (Fmc_Dataw3Snl)
27.5.1 Default configuration Upon system reset, the FMC is configured to provide a significant level of buffering for transfers from the flash memory: KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 588: Configuration Options
0, while the single-entry buffer can be enabled for bank 1 only. This configuration is ideal for applications that use bank 0 for program space and bank 1 for data space. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 589: Speculative Reads
4. Reading the fourth longword, like the second longword, takes only 1 clock due to the 64-bit flash memory data bus. 27.6 Initialization and application information The FMC does not require user initialization. Flash acceleration features are enabled by default. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 590 FMC's cache might need to be disabled and/or flushed to prevent the possibility of returning stale data. Use the PFB0CR[CINV_WAY] field to invalidate the cache in this manner. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 591: Flash Memory Module (Ftfa)
('1') states and/or programmed ('0') states. Therefore, it is recommended that each flash block or sector be re-erased immediately prior to factory programming to ensure that the full data retention capability is achieved. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 592: Features
• Supports MCU security mechanisms which prevent unauthorized access to the flash memory contents 28.1.2 Block Diagram The block diagram of the flash memory module is shown in the following figure. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 593: Glossary
HSRUN — An MCU power mode enabling high-speed access to the memory resources in the flash module. The user has no access to the flash command set when the MCU is in HSRUN mode. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 594: External Signal Description
Word — 16 bits of data with an aligned word having byte-address[0] = 0. 28.2 External Signal Description The flash memory module contains no signals that connect off-chip. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 595: Memory Map And Registers
Read Once Command, Program Once Command Read Resource Command). The contents of the program flash IFR are summarized in the table found here and further described in the subsequent paragraphs. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 596: Register Descriptions
CCIF. During this initialization period the user may write any register. All register writes are also disabled (except for registers FCNFG and KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 597 4002_0011 Program Flash Protection Registers (FTFA_FPROT2) Undefined 28.33.6/ 4002_0012 Program Flash Protection Registers (FTFA_FPROT1) Undefined 28.33.6/ 4002_0013 Program Flash Protection Registers (FTFA_FPROT0) Undefined Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 598 The FSTAT register reports the operational status of the flash memory module. The CCIF, RDCOLERR, ACCERR, and FPVIOL bits are readable and writable. The MGSTAT0 bit is read only. The unassigned bits read 0 and are not writable. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 599 The FPVIOL bit is cleared by writing a 1 to it. Writing a 0 to the FPVIOL bit has no effect. No protection violation detected Protection violation detected Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 600 Read collision error interrupt enabled. An interrupt request is generated whenever a flash memory read collision error is detected (see the description of FSTAT[RDCOLERR]). Erase All Request ERSAREQ Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 601 X in the reset value. Address: 4002_0000h base + 2h offset = 4002_0002h Read KEYEN MEEN FSLACC Write Reset * Notes: • x = Undefined at reset. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 602 The flash option register allows the MCU to customize its operations by examining the state of these read-only bits, which are loaded from NVM at reset. The function of the bits is defined in the device's Chip Configuration details. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 603 1 to the FSTAT[CCIF] bit. This clears the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed by the user until the command completes KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 604 KB of program flash where each assigned bit protects 1 KB . For configurations with 24 KB of program flash memory or less, FPROT0 is not used. For configurations with 16 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 605 1 and protected regions use a 0, only writes changing 1s to 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with 0-to-1 transitions are ignored. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 606 Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 607 SACCL3 SA[7:0] During the reset sequence, the SACC registers are loaded with the logical AND of Program Flash IFR addresses A and B as indicated in the following table. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 608 All bits in the register are read-only. The contents of this register are loaded during the reset sequence. Address: 4002_0000h base + 28h offset = 4002_0028h Read SGSIZE Write Reset KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 609 Number of Segments Indicator NUMSG The NUMSG field indicates the number of equal-sized segments in the program flash. 0x20 Program flash memory is divided into 32 segments (64 Kbytes, 128 Kbytes) KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 610: Functional Description
FPROT0[PROT31] Last program flash address Figure 28-44. Program flash protection NOTE Flash protection features are discussed further in AN4507: Using the Kinetis Security and Flash Protection Features . Not KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 611: Flash Access Protection
Figure 28-45. Program flash access control (256KB or 512KB of program flash) • FSACC — • For 2 program flash sizes greater than 128KB, eight registers control 64 segments of the program flash memory as shown in the following figure KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 612: Interrupts
Some devices also generate a bus error response as a result of a Read Collision Error event. See the chip configuration information to determine if a bus error response is also supported. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 613: Flash Operation In Low-Power Modes
Chip Configuration details of this device for how to activate each mode. 28.4.6 Flash Reads and Ignored Writes The flash memory module requires only the flash address to execute a flash memory read. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 614: Read While Write (Rww)
Flash command operations are typically used to modify flash memory contents. The next sections describe: • The command write sequence used to set flash command parameters and launch execution • A description of all flash commands available KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 615 The command processing has several steps: 1. The flash memory module reads the command code and performs a series of parameter checks and protection checks, if applicable, which are unique to each command. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 616 FCCOB and FSTAT registers. 4. The flash memory module sets FSTAT[CCIF] signifying that the command has completed. The flow for a generic command write sequence is illustrated in the following figure. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 617 0x02 Program Check × × Tests previously- programmed locations at margin read levels. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 618 28.4.9.3 Flash Commands by Mode The following table shows the flash commands that can be executed in each flash operating mode. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 619: Margin Read Commands
Program Flash 1 Read Program Sector Erase Read Program Sector Erase Read — Program Program — flash 0 Sector Erase — Read — Program Program — flash 1 Sector Erase — KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 620 'factory' margin levels, the flash memory contents should be erased and reprogrammed. CAUTION Factory margin levels must only be used during verify of the initial factory programming. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 621: Flash Command Description
Flash address [15:8] in the flash block to be verified Flash address [7:0] in the flash block to be verified Read-1 Margin Choice 1. Must be longword aligned (Flash address [1:0] = 00). KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 622 Number of phrases to be verified [15:8] Number of phrases to be verified [7:0] Read-1 Margin Choice 1. Must be phrase aligned (Flash address [2:0] = 000). KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 623 Flash address [7:0] Margin Choice Byte 0 expected data Byte 1 expected data Byte 2 expected data Byte 3 expected data 1. Must be longword aligned (Flash address [1:0] = 00). KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 624 The special-purpose memory resources available include program flash IFR space and the Version ID field. Each resource is assigned a select code as shown in Table 28-57. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 625 FSTAT[ACCERR] Flash address is not longword aligned FSTAT[ACCERR] 28.4.11.5 Program Longword Command The Program Longword command programs four previously-erased bytes in the program flash memory using an embedded algorithm. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 626 FSTAT[ACCERR] An invalid flash address is supplied FSTAT[ACCERR] Flash address is not longword aligned FSTAT[ACCERR] Flash address points to a protected area FSTAT[FPVIOL] Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 627 Any errors have been encountered during the verify operation FSTAT[MGSTAT0] 1. User margin read may be run using the Read 1s Block command to verify all bits are erased. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 628 ERSSUSP bit is set, the Erase Flash Sector operation is suspended and the flash memory module sets CCIF. While ERSSUSP is set, all writes to flash registers are ignored except for writes to the FSTAT and FCNFG registers. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 629 Data in this sector is not reliable until a new erase command fully completes. The following figure shows how to suspend and resume the Erase Flash Sector operation. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 630 ERSSCR Suspended Resume Erase? ERSSUSP: Bit in FCNFG register No, Abort SUSPACK: Internal Suspend Acknowledge Clear ERSSUSP User Cmd Interrupt/Suspend Figure 28-48. Suspend and Resume of Erase Flash Sector Operation KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 631 Apply the 'Factory' margin to the normal read-1 level Table 28-67. Read 1s All Blocks Command Error Handling Error Condition Error Bit An invalid margin choice is specified FSTAT[ACCERR] Read-1s fails FSTAT[MGSTAT0] KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 632 The Read Once command can be executed any number of times. Table 28-69. Read Once Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid record index is supplied FSTAT[ACCERR] KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 633 Command not available in current mode/security FSTAT[ACCERR] An invalid record index is supplied FSTAT[ACCERR] The requested record has already been programmed to a non-FFFF value FSTAT[ACCERR] Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 634 Error Bit Command not available in current mode/security FSTAT[ACCERR] Any region of the program flash memory is protected FSTAT[FPVIOL] Any errors have been encountered during the verify operation FSTAT[MGSTAT0] KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 635 Key Byte 1 0x0_0002 Key Byte 2 0x0_0001 Key Byte 3 0x0_0000 Key Byte 4 0x0_0007 Key Byte 5 0x0_0006 Key Byte 6 0x0_0005 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 636: Security
Flash Configuration Field (see Flash Configuration Field Description). The following fields are available in the FSEC register. The settings are described in the Flash Security Register (FTFA_FSEC) details. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 637 8-byte backdoor key value stored in the Flash Configuration Field (see Flash Configuration Field Description). If the FSEC[KEYEN] bits are in the enabled state, the Verify Backdoor Access Key command (see Verify KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 638: Reset Sequence
28.4.13 Reset Sequence On each system reset the flash memory module executes a sequence which establishes initial values for the flash block configuration parameters, FPROT, FOPT, and FSEC registers. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 639 If a reset occurs while any flash command is in progress, that command is immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. Commands and operations do not automatically resume after exiting reset. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 640 Functional Description KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 641: Overview
Memory contents can be read/erased/programmed from an external source, in a format that is compatible with many standalone flash memory chips, without requiring the removal of the microcontroller from the system board. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 642: Block Diagram
• Ability to reset the microcontroller, allowing it to boot from the flash memory after the memory has been configured. 29.1.3 Modes of operation The EzPort can operate in one of two modes, enabled or disabled. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 643: External Signal Descriptions
EZP_CK is the serial clock for data transfers. The serial data in (EZP_D) and chip select (EZP_CS) are registered on the rising edge of EZP_CK, while serial data out (EZP_Q) is driven on the falling edge of EZP_CK. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 644: Ezport Chip Select (Ezp_Cs)
Address Accepted when Command Description Code Data Bytes Bytes secure? WREN Write Enable 0x06 WRDI Write Disable 0x04 RDSR Read Status Register 0x05 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 645: Command Descriptions
WRFCCOB) to be accepted. The write enable register field clears on reset, on a Write Disable command, and at the completion of write command. This command must not be used if a write is already in progress. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 646 Table 29-3. EzPort status register BEDIS Reset: 1. Reset value reflects the status of flash security out of reset. 2. Reset value reflects whether bulk erase is enabled or disabled out of reset. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 647 Flash security can be disabled by performing a BE command. 0 = Flash is not secure. 1 = Flash is secure. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 648 The Read Data at High Speed (FAST_READ) command is identical to the READ command, except for the inclusion of a dummy byte following the address bytes and before the first data byte is returned. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 649 Flash memory map for EzPort access. This command is not accepted if the WEF, WIP, or FS field is set or if the WEN field is not set in the EzPort status register. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 650 WEF flag being set in the EzPort status register. Also, this command is not accepted if the WEF or WIP field is set or if the WEN field is not set in the EzPort status register. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 651 NOTE When security is enabled, the flash is configured in NVM Special mode, restricting the commands that can be executed by the flash. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 652: Flash Memory Map For Ezport Access
The flash block address map for access through EzPort may not conform to the system memory map. Changes are made to allow the EzPort address width to remain 24 bits. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 653 Chapter 29 EzPort Table 29-5. Flash Memory Map for EzPort Access Valid start address Size Flash block Valid commands See device's chip 0x0000_0000 Flash READ, FAST_READ, SP, SE, BE configuration details KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 654 Flash memory map for EzPort access KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 655: External Bus Interface (Flexbus)
• Can be directly connected to the following asynchronous or synchronous slave-only devices with little or no additional circuitry: • External ROMs • Flash memories • Programmable logic devices • Other simple target (slave) devices KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 656: Features
For example, in 16-bit mode, the lower address is driven on FB_AD15– FB_AD0, and in 8-bit mode, the lower address is driven on FB_AD23–FB_AD0. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 657 See CSCR[EXTS] and Extended Transfer Start/Address Latch Enable. FB_ALE Address Latch Enable—Indicates when the address is being driven on the FB_A bus (inverse of FB_TS). Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 658 (FB_TSIZ1–FB_TSIZ0 = 11b), and the address is misaligned within the 16-byte boundary, the external memory or peripheral must be able to wrap around the address. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 659: Memory Map/Register Definition
Note You must set CSMR0[V] before the chip select registers take effect. A bus error occurs when writing to reserved register locations. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 660: Chip Select Address Register (Fb_Csarn)
Defines the base address for memory dedicated to the associated chip-select. BA is compared to bits 31– 16 on the internal address bus to determine if the associated chip-select's memory is being accessed. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 661: Chip Select Mask Register (Fb_Csmrn)
Specifies whether the corresponding CSAR, CSMR, and CSCR contents are valid. Programmed chip- selects do not assert until the V bit is 1b (except for FB_CS0, which acts as the global chip-select). Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 662: Chip Select Control Register (Fb_Cscrn)
Address: 4000_C000h base + 8h offset + (12d × i), where i=0d to 5d EXTS ASET RDAH WRAH Reset BEM BSTR Reset FB_CSCRn field descriptions Field Description 31–26 Secondary Wait States Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 663 1 cycle (default for all but FB_CS0 ) 2 cycles 3 cycles 4 cycles (default for FB_CS0 ) Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 664 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports. Burst-Write Enable BSTW Specifies whether burst writes are enabled for memory associated with each chip select. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 665: Chip Select Port Multiplexing Control Register (Fb_Cspmcr)
Any other value Reserved 23–20 FlexBus Signal Group 3 Multiplex control GROUP3 Controls the multiplexing of the FB_CS5 , FB_TSIZ1, and FB_BE_23_16 signals. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 666: Functional Description
• Multiplexed 32-bit address and 16-bit data (non-multiplexed 16-bit address and 16- bit data) • Multiplexed 32-bit address and 8-bit data (non-multiplexed 24-bit address and 8-bit data) • Non-multiplexed 32-bit address and 32-bit data busses KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 667: Address Comparison
No bit ordering is required when connecting address and data lines to the FB_AD bus. For example, a full 16-bit address/16-bit data device connects its addr15–addr0 to FB_AD16–FB_AD1 and data15–data0 to FB_AD31–FB_AD16. See Data-byte alignment and physical connections for a graphical connection. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 668: Data Transfer Signals
FB_AD31–FB_AD24 (FB_BE_31_24). A 32-bit transfer through this 8-bit port takes four transfers, starting with the LSB to the MSB. A 32-bit transfer through a 32-bit port requires one transfer on each four-byte lane. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 669 Byte 2 FB_BE31_24 Byte 0 8-Bit Port Byte 1 Driven with Memory address values Byte 2 Byte 3 Figure 30-24. Connections for external memory port sizes (CSCRn[BLS] = 1) KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 670: Address/Data Bus Multiplexing
FB_AD Port size and phase 31–24 23–16 15–8 7–0 Address phase Address Data phase Data Address phase Address Data phase Address Data Address phase Address Data phase Address Data KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 671: Data Transfer States
S3 or through any additional address hold cycles. FlexBus invalidates the address, data, and FB_R/W on the rising edge of FB_CLK at the beginning of S3, terminating the transfer. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 672 Figure 30-25. Read Cycle Flowchart The read cycle timing diagram is shown in the following figure. Note FB_TA does not have to be driven by the external device for internally-terminated bus cycles. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 673 Figure 30-26. Basic Read-Bus Cycle 30.4.11.2 Basic Write Bus Cycle During a write cycle, the device sends data to memory or to a peripheral device. The following figure shows the write cycle flowchart. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 674 The following figure shows the write cycle timing diagram. Note The address and data busses are muxed between the FlexBus and another module. At the end of the write bus cycles, the address signals are indeterminate. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 675 FB_AD[23:0] throughout the bus cycle. • The external device returns the read data on FB_AD[31:24] and may tristate the data line or continue driving the data one clock after FB_TA is sampled asserted. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 676 TSIZ = 01 Figure 30-29. Single Byte-Read Transfer The following figure shows the similar configuration for a write transfer. The data is driven from the second clock on FB_AD[31:24]. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 677 FB_AD[15:0] throughout the bus cycle. • The external device returns the read data on FB_AD[31:16] and may tristate the data line or continue driving the data one clock after FB_TA is sampled asserted. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 678 TSIZ = 10 Figure 30-31. Single Word-Read Transfer The following figure shows the similar configuration for a write transfer. The data is driven from the second clock on FB_AD[31:16]. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 679 AA=0 FB_TSIZ[1:0] TSIZ=10 Figure 30-32. Single Word-Write Transfer 30.4.11.3.3 Bus Cycle Sizing—Longword Transfer, 32-bit Device, No Wait States The following figure depicts a longword read from a 32-bit device. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 680 AA=1 FB_CSn AA=0 FB_OEn BEM=0 FB_BE/BWEn BEM=1 AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ = 00 Figure 30-33. Longword-Read Transfer The following figure illustrates the longword write to a 32-bit device. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 681 The following figures show the basic read and write bus cycles (also shown in Figure 30-26 Figure 30-31) with the default of no wait states respectively. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 682 FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn BEM=0 FB_BE/BWEn BEM=1 AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 30-35. Basic Read-Bus Cycle (No Wait States) KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 683 If wait states are used, the S1 state repeats continuously until the chip-select auto- acknowledge unit asserts internal transfer acknowledge or the external FB_TA is recognized as asserted. The following figures show a read and write cycle with one wait state respectively. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 684 Functional description FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn BEM=0 FB_BE/BWEn BEM=1 AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 30-37. Read-Bus Cycle (One Wait State) KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 685 Each chip-select can be programmed to assert one to four clocks after transfer start/address-latch enable (FB_TS/FB_ALE) is asserted. The following figures show read- and write-bus cycles with two clocks of address setup respectively. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 686 FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn BEM=0 FB_BE/BWEn BEM=1 AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 30-39. Read-Bus Cycle with Two-Clock Address Setup (No Wait States) KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 687 Address and attributes can be held one to four clocks after chip-select, byte- selects, and output-enable negate. The following figures show read and write bus cycles with two clocks of address hold respectively. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 688 FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn BEM=0 FB_BE/BWEn BEM=1 AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 30-41. Read Cycle with Two-Clock Address Hold (No Wait States) KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 689 AA=0 FB_TSIZ[1:0] TSIZ Figure 30-42. Write Cycle with Two-Clock Address Hold (No Wait States) The following figure shows a bus cycle using address setup, wait states, and address hold. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 690: Burst Cycles
The CSCRn registers enable bursting for reads, writes, or both. Memory spaces can be declared burst-inhibited for reads and writes by writing 0b to the appropriate CSCRn[BSTR] and CSCRn[BSTW] fields. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 691 In multiplexed address/data mode, the address is driven on FB_AD only during the first cycle for all terminated cycles. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 692 The first beat of any write burst cycle has at least one wait state. If the bus cycle is programmed for zero wait states (CSCRn[WS] = 0b), one wait state is added. Otherwise, the programmed number of wait states are used. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 693 The following figure shows a 32-bit write to an 8-bit device with burst inhibited. The transfer results in four individual transfers. The transfer size is driven at 32-bit (00b) during the first transfer and at byte (01b) during the next three transfers. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 694 CSCRn[WS] determines the number of wait states in the first beat. However, for subsequent beats, the CSCRn[WS] (or CSCRn[SWS] if CSCRn[SWSEN] = 1b) determines the number of wait states. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 695 AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ = 00 30.4.12.7 32-bit-write burst to 8-bit port 3-2-2-2 (one wait state) The following figure illustrates a write burst transfer with one wait state. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 696 In multiplexed address/data mode, the address is driven on FB_AD only during the first cycle for internally- and externally-terminated cycles. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 697 FB_TSIZ[1:0] TSIZ=00 30.4.12.9 32-bit-write burst to 8-bit port 3-1-1-1 (address setup and hold) The following figure shows a write cycle with one clock of address setup and address hold. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 698: Extended Transfer Start/Address Latch Enable
FB_CSn asserts. See the following figure. NOTE When EXTS is set, CSCRn[WS] must be programmed to have at least one primary wait state. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 699: Bus Errors
The device can hang if FlexBus is configured for external termination and the CSPMCR is not configured for FB_TA. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 700: Initialization/Application Information
1. Invalidate the chip-select by writing 0b to the associated CSMR's Valid field (CSMRn[V]). 2. Write to the associated CSAR. 3. Write to the associated CSCR. 4. Write to the associated CSMR, including writing 1b to the Valid field (CSMRn[V]). KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 701: Cyclic Redundancy Check (Crc)
• Option for inversion of final CRC result • 32-bit CPU register programming interface 31.1.2 Block diagram The following is a block diagram of the CRC. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 702: Modes Of Operation
Register name Access Reset value (in bits) page (hex) 4003_2000 CRC Data register (CRC_DATA) FFFF_FFFFh 31.2.1/703 4003_2004 CRC Polynomial register (CRC_GPOLY) 0000_1021h 31.2.2/704 4003_2008 CRC Control register (CRC_CTRL) 0000_0000h 31.2.3/704 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 703: Crc Data Register (Crc_Data)
When CTRL[WAS] is 1, values written to this field are part of the seed value. When CTRL[WAS] is 0, data written to this field is used for CRC checksum generation. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 704: Crc Polynomial Register (Crc_Gpoly)
CRC calculation. A new CRC calculation is initialized by asserting CTRL[WAS] and then writing the seed into the CRC data register. Address: 4003_2000h base + 8h offset = 4003_2008h TOTR FXOR WAS Reset Reset KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 705: Functional Description
Width of CRC protocol. TCRC 16-bit CRC protocol. 32-bit CRC protocol. 23–0 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 31.3 Functional description KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 706: Crc Calculations
8. When all values have been written, read the final CRC result from CRC_DATA[LU:LL]. Transpose and complement operations are performed on the fly while reading or writing values. See Transpose feature CRC result complement for details. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 707: Transpose Feature
CTRL[TOT] or CTRL[TOTR] fields, according to the CRC calculation being used. The following types of transpose functions are available for writing to and reading from the CRC data register: 1. CTRL[TOT] or CTRL[TOTR] is 00. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 708 = {reg[0:7], reg[8:15],reg[16:23], reg[24:31]} Figure 31-6. Transpose type 10 4. CTRL[TOT] or CTRL[TOTR] is 11. Bytes are transposed, but bits are not transposed. reg[31:0] becomes {reg[7:0], reg[15:8], reg[23:16], reg[31:24]} KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 709: Crc Result Complement
CRC data register every time the CRC data register is read. When CTRL[FXOR] is cleared, reading the CRC data register accesses the raw checksum value. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 710 Functional description KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 711: Random Number Generator Accelerator (Rnga)
NIST-approved pseudo-random-number generator based on DES or SHA-1 and defined in NIST FIPS PUB 186-2 Appendix 3 and NIST FIPS PUB SP 800-90. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 712: Modes Of Operation
(randomness) from the clocks and stores it in shift registers. Sleep The ring-oscillator clocks are inactive; RNGA does not generate entropy. 32.2.1 Entering Normal mode To enter Normal mode, write 0 to CR[SLP]. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 713: Memory Map And Register Definition
4002_900C RNGA Output Register (RNG_OR) 0000_0000h 32.3.4/717 32.3.1 RNGA Control Register (RNG_CR) Controls the operation of RNGA. Address: 4002_9000h base + 0h offset = 4002_9000h Reset INTM CLRI Reset KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 714 Specifies whether random-data generation and loading (into OR[RANDOUT]) is enabled. NOTE: This field is sticky. You must reset RNGA to stop RNGA from loading OR[RANDOUT] with data. Disabled Enabled KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 715: Rnga Status Register (Rng_Sr)
NOTE: If you read OR[RANDOUT] when SR[OREG_LVL] is not 0, then the contents of a random number contained in OR[RANDOUT] are returned, and RNGA writes 0 to both OR[RANDOUT] and SR[OREG_LVL]. No words (empty) One word (valid) Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 716 Used only when high assurance is enabled (CR[HA]). Indicates that a security violation has occurred. NOTE: This field is sticky. To clear SR[SECV], you must reset RNGA. No security violation Security violation KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 717: Rnga Entropy Register (Rng_Er)
RNG_OR field descriptions Field Description 31–0 Random Output RANDOUT Stores a random-data word generated by RNGA. This is a read-only field. NOTE: Before reading RANDOUT, be sure it is valid (SR[OREG_LVL]=1). KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 718: Functional Description
OR when it is empty, RNGA returns all zeros and, if the interrupt is enabled, RNGA drives a request to the interrupt controller. Polling SR[OREG_LVL] is very important to make sure random values are present before reading from OR. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 719: Initialization/Application Information
3. Poll SR[OREG_LVL] until it is not 0. 4. When SR[OREG_LVL] is not 0, read the available random data from OR[RANDOUT]. 5. Repeat steps 3 and 4 as needed. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 720 Initialization/application information For application information, see Overview. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 721: Analog-To-Digital Converter (Adc)
• Output format in 2's complement 16-bit sign extended for differential modes • Output in right-justified unsigned format for single-ended • Single or continuous conversion, that is, automatic return to idle after single conversion KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 722: Block Diagram
• Temperature sensor • Hardware average function • Selectable voltage reference: external or alternate • Self-Calibration mode 33.1.2 Block diagram The following figure is the ADC module block diagram. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 723: Adc Signal Descriptions
Each differential pair requires two inputs, DADPx and DADMx. The ADC also requires four supply/reference/ground connections. NOTE Refer to ADC configuration section in chip configuration chapter for the number of channels supported on this device. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 724: Analog Power (Vdda)
ALTL depending on MCU configuration. See the chip configuration information on the Voltage References specific to this MCU. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 725: Analog Channel Inputs (Adx)
33.3.4/733 4002_7014 ADC Data Result Register (ADC1_RB) 0000_0000h 33.3.4/733 4002_7018 Compare Value Registers (ADC1_CV1) 0000_0000h 33.3.5/734 4002_701C Compare Value Registers (ADC1_CV2) 0000_0000h 33.3.5/734 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 726 33.3.4/733 4003_B014 ADC Data Result Register (ADC0_RB) 0000_0000h 33.3.4/733 4003_B018 Compare Value Registers (ADC0_CV1) 0000_0000h 33.3.5/734 4003_B01C Compare Value Registers (ADC0_CV2) 0000_0000h 33.3.5/734 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 727: Adc Status And Control Registers 1 (Adcx_Sc1N)
To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC can have more than one status and control register: one for each conversion. The SC1B–SC1n registers indicate potentially multiple SC1 registers for use only in hardware KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 728 Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Conversion Complete Flag COCO Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 729 When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved. 01011 When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 730: Adc Configuration Register 1 (Adcx_Cfg1)
The configuration Register 1 (CFG1) selects the mode of operation, clock source, clock divide, and configuration for low power or long sample time. Address: Base address + 8h offset Reset ADIV MODE ADICLK Reset KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 731 In this case, there is an associated clock startup delay each time the clock source is re-activated. Bus clock Alternate clock 2 (ALTCLK2) Alternate clock (ALTCLK) Asynchronous clock (ADACK) KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 732: Adc Configuration Register 2 (Adcx_Cfg2)
Configures the ADC for very high-speed operation. The conversion sequence is altered with 2 ADCK cycles added to the conversion time to allow higher speed conversion clocks. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 733: Adc Data Result Register (Adcx_Rn)
13-bit differential S Sign-extended 2's complement 12-bit single- Unsigned right- ended justified 11-bit differential S Sign-extended 2's complement 10-bit single- Unsigned right- ended justified Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 734: Compare Value Registers (Adcx_Cvn)
The compare value 2 register (CV2) is used only when the compare range function is enabled, that is, SC2[ACREN]=1. Address: Base address + 18h offset + (4d × i), where i=0d to 1d Reset KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 735: Status And Control Register 2 (Adcx_Sc2)
ADCx_SC2 field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Conversion Active ADACT Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 736 . This pair may be additional external pins or ALTH ALTL internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 737: Status And Control Register 3 (Adcx_Sc3)
Begins the calibration sequence when set. This field stays set while the calibration is in progress and is cleared when the calibration sequence is completed. CALF must be checked to determine the result of the Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 738 Hardware Average Select AVGS Determines how many ADC conversions will be averaged to create the ADC average result. 4 samples averaged. 8 samples averaged. 16 samples averaged. 32 samples averaged. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 739: Adc Offset Correction Register (Adcx_Ofs)
ADPG15 and ADPG14. This register must be written by the user with the value described in the calibration procedure. Otherwise, the gain error specifications may not be met. Address: Base address + 2Ch offset Reset KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 740: Adc Minus-Side Gain Register (Adcx_Mg)
CLP4[9:0], CLPS[5:0], and CLPD[5:0]. CLPx are automatically set when the self- calibration sequence is done, that is, CAL is cleared. If these registers are written by the user after calibration, the linearity error specifications may not be met. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 741: Adc Plus-Side General Calibration Value Register (Adcx_Clps)
5–0 Calibration Value CLPS Calibration Value 33.3.13 ADC Plus-Side General Calibration Value Register (ADCx_CLP4) For more information, see CLPD register description. Address: Base address + 3Ch offset CLP4 Reset KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 742: Adc Plus-Side General Calibration Value Register (Adcx_Clp3)
Reset ADCx_CLP2 field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 743: Adc Plus-Side General Calibration Value Register (Adcx_Clp1)
Reset ADCx_CLP0 field descriptions Field Description 31–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 5–0 Calibration Value CLP0 Calibration Value KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 744: Adc Minus-Side General Calibration Value Register (Adcx_Clmd)
Reset ADCx_CLMS field descriptions Field Description 31–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 5–0 Calibration Value CLMS Calibration Value KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 745: Adc Minus-Side General Calibration Value Register (Adcx_Clm4)
Reset ADCx_CLM3 field descriptions Field Description 31–9 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 8–0 Calibration Value CLM3 Calibration Value KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 746: Adc Minus-Side General Calibration Value Register (Adcx_Clm2)
Reset ADCx_CLM1 field descriptions Field Description 31–7 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 6–0 Calibration Value CLM1 Calibration Value KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 747: Adc Minus-Side General Calibration Value Register (Adcx_Clm0)
The ADC module has the capability of automatically comparing the result of a conversion with the contents of the CV1 and CV2 registers. The compare function is enabled by setting SC2[ACFE] and operates in any of the conversion modes and configurations. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 748: Clock Select And Divide Control
If the available clocks are too fast, the clock must be divided to the appropriate frequency. This divider is specified by CFG1[ADIV] and can be divide-by 1, 2, 4, or 8. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 749: Voltage Reference Selection
ADHWT signal to trigger a new conversion. The channel and status fields selected for the conversion depend on the active trigger select signal: • ADHWTSA active selects SC1A. • ADHWTSn active selects SC1n. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 750: Conversion Control
SC2[ADTRG]=1, and a hardware trigger select event, ADHWTSn, has occurred. The channel and status fields selected depend on the active trigger select signal: • ADHWTSA active selects SC1A. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 751 SC1n[COCO] sets only if the last of the selected number of conversions is completed and the compare condition is true. An interrupt is generated if the respective SC1n[AIEN] is high at the time that the respective SC1n[COCO] is set. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 752 CFG2[ADACKEN]=1, it remains active regardless of the state of the ADC or the MCU power mode. Power consumption when the ADC is active can be reduced by setting CFG1[ADLPC]. This results in a lower maximum value for f ADCK KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 753 3. The result of the conversion is transferred to Rn upon completion of the conversion algorithm. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 754 27 ADCK cycles 10b single-ended 20 ADCK cycles 11b differential 30 ADCK cycles 12b single-ended 20 ADCK cycles 13b differential 30 ADCK cycles Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 755 • 10-bit mode, with the bus clock selected as the input clock source • The input clock divide-by-1 ratio selected • Bus frequency of 8 MHz • Long sample time disabled • High-speed conversion disabled KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 756 Figure 33-92. Table 33-110. Typical conversion time Variable Time SFCAdder 3 ADCK cycles + 5 bus clock cycles AverageNum 34 ADCK cycles LSTAdder 20 ADCK cycles HSCAdder KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 757 When hardware averaging is selected, the completion of a single conversion will not set SC1n[COCO]. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 758: Automatic Compare Function
CV2. Greater than Outside range, inclusive Compare true if the result is greater than or equal to CV1 Or the result is less than or equal to CV2. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 759: Calibration Function
Prior to calibration, the user must configure the ADC's clock source and frequency, low power configuration, voltage reference selection, sample time, and high speed configuration according to the application's clock source availability and needs. If the KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 760 When calibration is complete, the user may reconfigure and use the ADC as desired. A second calibration may also be performed, if desired, by clearing and again setting SC3[CAL]. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 761: User-Defined Offset Function
ADC error specifications may not be met. Storing the value generated by the calibration function in memory before overwriting with a user- specified value is recommended. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 762: Temperature Sensor
• m is referred as temperature sensor slope in the device data sheet. It is the hot or cold voltage versus temperature slope in V/°C. For temperature calculations, use the V and temperature sensor slope values from TEMP25 the ADC Electricals table. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 763: Mcu Wait Mode Operation
33.4.10 MCU Normal Stop mode operation Stop mode is a low-power consumption Standby mode during which most or all clock sources on the MCU are disabled. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 764: Mcu Low-Power Stop Mode Operation
Therefore, the module must be re-enabled and re-configured following exit from Low-Power Stop mode. NOTE For the chip specific modes of operation, see the power management information for the device. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 765: Initialization Information
5. Update SC1:SC1n registers to select whether conversions will be single-ended or differential and to enable or disable conversion complete interrupts. Also, select the input channel which can be used to perform conversions. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 766 Bit 4:0 ADCH 00001 Input channel 1 selected as ADC input channel. RA = 0xxx Holds results of conversion. CV = 0xxx Holds compare value when compare function enabled. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 767: Application Information
33.6.1 External pins and routing 33.6.1.1 Analog supply pins Depending on the device, the analog power and ground supplies, V and V , of the ADC module are available as: KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 768 V and V loop. The REFH REFL best external component to meet this current demand is a 0.1 μF capacitor with good KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 769: Sources Of Error
RAS + RADIN =SC / (FMAX * NUMTAU * CADIN) Figure 33-95. Sampling equation Where: RAS = External analog source resistance SC = Number of ADCK cycles used during sample window KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 770 REFL plane. • Operate the MCU in Wait or Normal Stop mode before initiating (hardware-triggered conversions) or immediately after initiating (hardware- or software-triggered conversions) the ADC conversion. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 771 12-bit modes. As a consequence, however, the code width of the first (0x000) conversion is only 1/2 LSB and the code width of the last (0xFF or 0x3FF) is 1.5 LSB. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 772 However, even small amounts of system noise can cause the converter to be indeterminate, between two codes, for a range of input voltages around the transition voltage. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 773 • Missing codes: Missing codes are those values never converted for any input value. In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and have no missing codes. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 774 Application information KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 775: Comparator (Cmp)
34.1.1 CMP features The CMP has the following features: • Operational over the entire supply range • Inputs may range from rail to rail • Programmable hysteresis control KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 776: 6-Bit Dac Key Features
• 6-bit resolution • Selectable supply reference source • Power Down mode to conserve power when not in use • Option to route the output to internal comparator input KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 777: Cmp, Dac And Anmux Diagram
• Two 8-to-1 channel mux • Operational over the entire supply range 34.1.4 CMP, DAC and ANMUX diagram The following figure shows the block diagram for the High-Speed Comparator, DAC, and ANMUX modules. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 778: Cmp Block Diagram
ANMUX and filter control CMPO MSEL[2:0] Figure 34-1. CMP, DAC and ANMUX block diagram 34.1.5 CMP block diagram The following figure shows the block diagram for the CMP module. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 779 CR0[FILTER_CNT] is set greater than 0x01. • If CR1[SE] = 1, the external SAMPLE input is used as sampling clock • If CR1[SE] = 0, the divided bus clock is used as sampling clock KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 780: Memory Map/Register Definitions
Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. 6–4 Filter Sample Count FILTER_CNT Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 781: Cmp Control Register 1 (Cmpx_Cr1)
WE is cleared. However, avoid writing 1s to both field locations because this "11" case is reserved and may change in future implementations. Sampling mode is not selected. Sampling mode is selected. Windowing Enable Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 782 When the user selects the same input from analog mux to the positive and negative port, the comparator is disabled automatically. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 783: Cmp Filter Period Register (Cmpx_Fpr)
Enables the DMA transfer triggered from the CMP module. When this field is set, a DMA request is asserted when CFR or CFF is set. DMA is disabled. DMA is enabled. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 784: Dac Control Register (Cmpx_Daccr)
CMPx_DACCR field descriptions Field Description DAC Enable DACEN Enables the DAC. When the DAC is disabled, it is powered down to conserve power. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 785: Mux Control Register (Cmpx_Muxcr)
MSEL Determines which input is selected for the minus input of the comparator. For INx inputs, see CMP, DAC, and ANMUX block diagrams. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 786: Functional Description
The external sample input is enabled using CR1[SE]. When set, the output of the comparator is sampled only on rising edges of the sample input. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 787 SAMPLE=1 to generate COUTA, which is then resampled and filtered to generate COUT. See the Windowed/Filtered mode (#7). All other combinations of CR1[EN], CR1[WE], CR1[SE], CR0[FILTER_CNT], and FPR[FILT_PER] are illegal. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 788 CMPO COUT To other system functions WINDOW/SAMPLE bus clock Clock COUTA CMPO to prescaler divided FILT_PER CGMUX clock Figure 34-21. Comparator operation in Continuous mode KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 789 In Sampled, Non-Filtered mode, the analog comparator block is powered and active. The path from analog inputs to COUTA is combinational unclocked. Windowing control is completely bypassed. COUTA is sampled whenever a rising-edge is detected on the filter block clock input. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 790 COUTA is sampled whenever a rising edge is detected on the filter block clock input. The only difference in operation between Sampled, Non-Filtered (# 3A) and Sampled, Filtered (# 4A) is that, now, CR0[FILTER_CNT]>1, which activates filter operation. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 791 CMPO COUT To other SOC functions WINDOW/SAMPLE bus clock Clock COUTA CMPO to prescaler divided FILT_PER CGMUX clock SE=1 Figure 34-24. Sampled, Filtered (# 4A): sampling point externally driven KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 792 WINDOW signal is high. In actual operation, COUTA may lag the analog inputs by up to one bus clock cycle plus the combinational path delay through the comparator and polarity select logic. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 793 COUTA CMPO to divided prescaler FILT_PER CGMUX clock SE=0 Figure 34-27. Windowed mode For control configurations which result in disabling the filter block, see Filter Block Bypass Logic diagram. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 794 Configuration for this mode is virtually identical to that for the Windowed/Filtered Mode shown in the next section. The only difference is that the value of CR0[FILTER_CNT] must be 1. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 795: Power Modes
Figure 34-29. Windowed/Filtered mode 34.3.2 Power modes 34.3.2.1 Wait mode operation During Wait and VLPW modes, the CMP, if enabled, continues to operate normally and a CMP interrupt can wake the MCU. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 796: Startup And Operation
The filter delay is specified in the Low-pass filter. • During operation, the propagation delay of the selected data paths must always be considered. It may take many bus clock cycles for COUT and SCR[CFR]/SCR[CFF] KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 797: Low-Pass Filter
In other words, SCR[COUT] will be 0 for some initial period, even when COUTA is at logic 1. Setting both CR1[SE] and FPR[FILT_PER] to 0 disables the filter and eliminates switching current associated with the filtering process. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 798 Sampled, Filtered mode + (CR0[FILTER_CNT] * ) + T SAMPLE > 0x01 > 0x00 + (CR0[FILTER_CNT] * FPR[FILT_PER] x T ) + T Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 799: Cmp Interrupts
DMA transfer request and clears the flag to allow a subsequent change on comparator output to occur and force another DMA request. The comparator can remain functional in STOP modes. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 800: Cmp Asynchronous Dma Support
STOP modes. After the data transfer has finished, system will go back to STOP modes. Refer to DMA chapters in the device reference manual for the asynchronous DMA function for details. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 801: Digital-To-Analog Converter
34.8.1 Voltage reference source select • V connects to the primary voltage source as supply reference of 64 tap resistor ladder • V connects to an alternate voltage source KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 802: Dac Resets
This module has a single reset input, corresponding to the chip-wide peripheral reset. 34.10 DAC clocks This module has a single clock input, the bus clock. 34.11 DAC interrupts This module has no interrupts. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 803: 12-Bit Digital-To-Analog Converter (Dac)
• Static operation in Normal Stop mode • 16-word data buffer supported with configurable watermark and multiple operation modes • DMA support 35.3 Block diagram The block diagram of the DAC module is as follows: KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 804: Memory Map/Register Definition
DACBBIEN DACBFMD DACTRGSE Figure 35-1. DAC block diagram 35.4 Memory map/register definition The DAC has registers to control analog comparator and programmable voltage divider to perform the digital-to-analog functions. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 805 DAC Control Register 1 (DAC1_C1) 35.4.5/810 4002_8023 DAC Control Register 2 (DAC1_C2) 35.4.6/811 4003_F000 DAC Data Low Register (DAC0_DAT0L) 35.4.1/807 4003_F001 DAC Data High Register (DAC0_DAT0H) 35.4.2/807 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 806 DAC Data High Register (DAC0_DAT15H) 35.4.2/807 4003_F020 DAC Status Register (DAC0_SR) 35.4.3/808 4003_F021 DAC Control Register (DAC0_C0) 35.4.4/809 4003_F022 DAC Control Register 1 (DAC0_C1) 35.4.5/810 4003_F023 DAC Control Register 2 (DAC0_C2) 35.4.6/811 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 807: Dac Data Low Register (Dacx_Datnl)
When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage based on the following formula. V * (1 + DACDAT0[11:0])/4096 When the DAC buffer is enabled, DATA[11:0] is mapped to the 16-word buffer. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 808: Dac Status Register (Dacx_Sr)
DAC trigger making the DAC read pointer increase. Write to this bit is ignored in FIFO mode. The DAC buffer read pointer is not equal to C2[DACBFUP]. The DAC buffer read pointer is equal to C2[DACBFUP]. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 809: Dac Control Register (Dacx_C0)
The DAC buffer read pointer top flag interrupt is disabled. The DAC buffer read pointer top flag interrupt is enabled. DAC Buffer Read Pointer Bottom Flag Interrupt Enable DACBBIEN Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 810: Dac Control Register 1 (Dacx_C1)
Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 811: Dac Control Register 2 (Dacx_C2)
When both the DAC and the buffer are enabled, the DAC converts the data in the data buffer to analog output voltage. The data buffer read pointer advances to the next word whenever any hardware or software trigger event occurs. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 812 NOTE: If the software set the read pointer to the upper limit, the read pointer will not advance in this mode. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 813: Dma Operation
The status register flags are still set and are cleared automatically when the DMA completes. 35.5.3 Resets During reset, the DAC is configured in the default mode and is disabled. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 814 In low-power stop modes, the DAC is fully shut down. NOTE The assignment of module modes to core modes is chip- specific. For module-to-core mode assignments, see the chapter that describes how modules are configured. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 815: Introduction
ADC, DAC, or CMP. The voltage reference has three operating modes that provide different levels of supply rejection and power consumption.. The following figure is a block diagram of the Voltage Reference. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 816: Overview
The Voltage Reference has the following features: • Programmable trim register with 0.5 mV steps, automatically loaded with factory trimmed value upon reset • Programmable buffer mode selection: • Off KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 817: Voltage Reference (Vrefv1)
The following table shows the Voltage Reference signals properties. Table 36-1. VREF Signal Descriptions Signal Description VREF_OUT Internally-generated Voltage Reference output NOTE When the VREF output buffer is disabled, the status of the VREF_OUT signal is high-impedence. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 818: Memory Map And Register Definition
NOTE: Min = minimum and max = maximum voltage reference output. For minimum and maximum voltage reference output values, refer to the Data Sheet for this chip. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 819: Vref Status And Control Register (Vref_Sc)
Internal 1.75 V regulator is enabled. Second order curvature compensation enable ICOMPEN This bit should be written to 1 to achieve the performance stated in the data sheet. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 820: Functional Description
100 nF capacitor is required. Voltage Reference enabled, VREF_OUT available for low power buffer on internal and external use. 100 nF capacitor is required. Reserved Reserved KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 821: Voltage Reference Disabled, Sc[Vrefen] = 0
(Tstup) and the value is specified in the appropriate device data sheet. If this mode is entered when the VREF module is enabled then you must wait the longer of KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 822: Internal Voltage Regulator
1. Enable the chop oscillator (VREF_TRM[CHOPEN] = 1) 2. Configure the VREF_SC register to the desired settings with the internal regulator disabled, VREF_SC[REGEN] = 0 3. Wait > 300ns KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 823: Initialization/Application Information
The TRM[CHOPEN], SC[REGEN] and SC[ICOMPEN] bits must be written to 1 to achieve the performance stated in the device data sheet. NOTE See section "Internal voltage regulator" for details on the required sequence to enable the internal regulator. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 824 Initialization/Application Information KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 825: Introduction
• Trigger outputs can be enabled or disabled independently • One 16-bit delay register per pre-trigger output • Optional bypass of the delay registers of the pre-trigger outputs • Operation in One-Shot or Continuous modes KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 826: Implementation
• y—Pulse-Out number, valid value is from 0 to Y-1. NOTE The number of module output triggers to core is chip-specific. For module to core output triggers implementation, see the chip configuration information. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 827: Programmable Delay Block (Pdb)
37.1.4 DAC External Trigger Input Connections The implementation of DAC external trigger inputs is chip-specific. See the chip configuration information for details. 37.1.5 Block diagram This diagram illustrates the major components of the PDB. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 828 In this diagram, only one PDB channel n, one DAC interval trigger x, and one Pulse-Out y are shown. The PDB-enabled control logic and the sequence error interrupt logic are not shown. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 829: Modes Of Operation
If the PDB is enabled and external trigger input source is selected, a positive edge on the EXTRG signal resets and starts the counter. 37.3 Memory map and register definition KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 830 4003_615C DAC Interval n register (PDB0_DACINT1) 0000_0000h 37.3.11/ 4003_6190 Pulse-Out n Enable register (PDB0_POEN) 0000_0000h 37.3.12/ 4003_6194 Pulse-Out n Delay register (PDB0_PO0DLY) 0000_0000h 37.3.12/ 4003_6198 Pulse-Out n Delay register (PDB0_PO1DLY) 0000_0000h KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 831: Status And Control Register (Pdbx_Sc)
Enables the PDB sequence error interrupt. When this field is set, any of the PDB channel sequence error flags generates a PDB sequence error interrupt. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 832 Trigger-In 11 is selected. 1100 Trigger-In 12 is selected. 1101 Trigger-In 13 is selected. 1110 Trigger-In 14 is selected. 1111 Software trigger is selected. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 833: Modulus Register (Pdbx_Mod)
1. It is automatically cleared when the values in buffers are loaded into the internal registers or the PDBEN is cleared. Writing 0 to it has no effect. 37.3.2 Modulus register (PDBx_MOD) Address: 4003_6000h base + 4h offset = 4003_6004h Reset KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 834: Counter Register (Pdbx_Cnt)
Specifies the delay value to schedule the PDB interrupt. It can be used to schedule an independent interrupt at some point in the PDB cycle. If enabled, a PDB interrupt is generated, when the counter is Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 835: Channel N Control Register 1 (Pdbx_Chnc1)
PDB Channel Pre-Trigger Enable These bits enable the PDB ADC pre-trigger outputs. Only lower M pre-trigger bits are implemented in this MCU. PDB channel's corresponding pre-trigger disabled. PDB channel's corresponding pre-trigger enabled. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 836: Channel N Status Register (Pdbx_Chns)
Specifies the delay value for the channel's corresponding pre-trigger. The pre-trigger asserts when the counter is equal to DLY. Reading this field returns the value of internal register that is effective for the current PDB cycle. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 837: Channel N Delay 1 Register (Pdbx_Chndly1)
DAC external trigger input enabled. DAC interval counter is bypassed and DAC external trigger input triggers the DAC interval trigger. DAC Interval Trigger Enable Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 838: Dac Interval N Register (Pdbx_Dacintn)
This read-only field is reserved and always has the value 0. 7–0 PDB Pulse-Out Enable POEN Enables the pulse output. Only lower Y bits are implemented in this MCU. PDB Pulse-Out disabled PDB Pulse-Out enabled KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 839: Pulse-Out N Delay Register (Pdbx_Pondly)
Each channel is associated with 1 ADC block. PDB channel n pre-trigger outputs 0 to M; each pre-trigger output is connected to ADC hardware trigger select and hardware trigger inputs. The pre-triggers are used to precondition the ADC block before the actual trigger KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 840 The lock becomes inactive when: • the rising edge of corresponding ADCnSC1[COCO] occurs, • or the corresponding PDB pre-trigger is disabled, • or the PDB is disabled KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 841: Pdb Trigger Input Source Selection
ADC pre-trigger/trigger outputs and Pulse-Out generation have the same time base, because they both share the PDB counter. The pulse-out connections implemented in this MCU are described in the device's chip configuration details. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 842: Updating The Delay Registers
The following diagrams show the cases of the internal registers being updated with SC[LDMOD] is 00 and x1. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 843: Interrupts
SC[PDBEIE] = 1 37.4.6 DMA If SC[DMAEN] is set, PDB can generate a DMA transfer request when SC[PDBIF] is set. When DMA is enabled, the PDB interrupt is not issued. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 844: Application Information
If the applications need a really long delay value and use a prescaler set to 128, then the resolution would be limited to 128 peripheral clock cycles. Therefore, use the lowest possible prescaler and multiplication factor for a given application. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 845: Flextimer Module (Ftm)
All of the features common with the TPM have fully backwards compatible register assignments. The FlexTimer can also use code on the same core platform without change to perform the same functions. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 846: Features
• It can be a free-running counter or a counter with initial and final value • The counting can be up or up-down • Each channel can be configured for input capture, output compare, or edge-aligned PWM mode • In Input Capture mode: KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 847: Modes Of Operation
FTM is effectively disabled until clocks resume. During Wait mode, the FTM continues to operate normally. If the FTM does not need to produce a KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 848: Block Diagram
The following figure shows the FTM structure. The central component of the FTM is the 16-bit counter with programmable initial and final values and its counting can be up or up-down. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 849 7 mode logic input DECAPEN CH7F channel 7 COMBINE3 channel 7 interrupt CPWMS CH7TRIG match trigger CH7IE MS7B:MS7A ELS7B:ELS7A Figure 38-1. FTM block diagram KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 850: Ftm Signal Descriptions
This section presents a high-level summary of the FTM registers and how they are mapped. The registers and bits of an unavailable function in the FTM remain in the memory map and in the reset value, but they have no active function. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 851: Register Descriptions
Features Mode Selection (FTM3_MODE) 0000_0004h 38.3.11/ 4002_6058 Synchronization (FTM3_SYNC) 0000_0000h 38.3.12/ 4002_605C Initial State For Channels Output (FTM3_OUTINIT) 0000_0000h 38.3.13/ 4002_6060 Output Mask (FTM3_OUTMASK) 0000_0000h Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 852 4003_802C Channel (n) Status And Control (FTM0_C4SC) 0000_0000h 38.3.6/860 4003_8030 Channel (n) Value (FTM0_C4V) 0000_0000h 38.3.7/863 4003_8034 Channel (n) Status And Control (FTM0_C5SC) 0000_0000h 38.3.6/860 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 853 0000_0000h 38.3.24/ 4003_808C Synchronization Configuration (FTM0_SYNCONF) 0000_0000h 38.3.25/ 4003_8090 FTM Inverting Control (FTM0_INVCTRL) 0000_0000h 38.3.26/ 4003_8094 FTM Software Output Control (FTM0_SWOCTRL) 0000_0000h 38.3.27/ 4003_8098 FTM PWM Load (FTM0_PWMLOAD) 0000_0000h KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 854 4003_906C FTM External Trigger (FTM1_EXTTRIG) 0000_0000h 38.3.17/ 4003_9070 Channels Polarity (FTM1_POL) 0000_0000h 38.3.18/ 4003_9074 Fault Mode Status (FTM1_FMS) 0000_0000h 38.3.19/ 4003_9078 Input Capture Filter Control (FTM1_FILTER) 0000_0000h Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 855 4003_A04C Counter Initial Value (FTM2_CNTIN) 0000_0000h 38.3.8/863 4003_A050 Capture And Compare Status (FTM2_STATUS) 0000_0000h 38.3.9/864 38.3.10/ 4003_A054 Features Mode Selection (FTM2_MODE) 0000_0004h 38.3.11/ 4003_A058 Synchronization (FTM2_SYNC) 0000_0000h Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 856 0000_0000h 38.3.24/ 4003_A08C Synchronization Configuration (FTM2_SYNCONF) 0000_0000h 38.3.25/ 4003_A090 FTM Inverting Control (FTM2_INVCTRL) 0000_0000h 38.3.26/ 4003_A094 FTM Software Output Control (FTM2_SWOCTRL) 0000_0000h 38.3.27/ 4003_A098 FTM PWM Load (FTM2_PWMLOAD) 0000_0000h KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 857: Status And Control (Ftmx_Sc)
TOF remains set indicating an overflow has occurred. In this case, a TOF interrupt request is not lost due to the clearing sequence for a previous TOF. FTM counter has not overflowed. FTM counter has overflowed. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 858: Counter (Ftmx_Cnt)
Reset clears the CNT register. Writing any value to COUNT updates the counter with its initial value, CNTIN. When BDM is active, the FTM counter is frozen. This is the value that you may read. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 859: Modulo (Ftmx_Mod)
Address: Base address + 8h offset Reserved Reset FTMx_MOD field descriptions Field Description 31–16 This field is reserved. Reserved 15–0 Modulo Value KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 860: Channel (N) Status And Control (Ftmx_Cnsc)
(set on channel (n) match, and clear on channel (n+1) match) Low-true pulses (clear on channel (n) match, and set on channel (n +1) match) Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 861 Enabled Falling edge Enabled Rising and falling edges Address: Base address + Ch offset + (8d × i), where i=0d to 7d Reset CHIE MSB MSA ELSB ELSA Reset KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 862 FTM counter is not reset when the selected channel (n) input event is detected. FTM counter is reset when the selected channel (n) input event is detected. DMA Enable Enables DMA transfers for the channel. Disable DMA transfers. Enable DMA transfers. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 863: Channel (N) Value (Ftmx_Cnv)
FTM clock, write the new value to the the CNTIN register and then initialize the FTM counter by writing any value to the CNT register. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 864: Capture And Compare Status (Ftmx_Status)
CHnF remains set indicating an event has occurred. In this case, a CHnF interrupt request is not lost due to the clearing sequence for a previous CHnF. Address: Base address + 50h offset Reset KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 865 CH3F See the register description. No channel event has occurred. A channel event has occurred. Channel 2 Flag CH2F See the register description. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 866: Features Mode Selection (Ftmx_Mode)
• PWM synchronization • Write protection • Channel output initialization These controls relate to all channels within this module. Address: Base address + 54h offset Reset FAULTM INIT Reset KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 867 The INIT bit is always read as 0. FTM Enable FTMEN This field is write protected. It can be written only when MODE[WPDIS] = 1. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 868: Synchronization (Ftmx_Sync)
The synchronization event selection also depends on the PWMSYNC (MODE register) and SYNCMODE (SYNCONF register) bits. See synchronization. Address: Base address + 58h offset Reset KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 869 The REINIT bit configures the synchronization when SYNCMODE is zero. FTM counter continues to count normally. FTM counter is updated with its initial value when the selected trigger is detected. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 870: Initial State For Channels Output (Ftmx_Outinit)
Selects the value that is forced into the channel output when the initialization occurs. The initialization value is 0. The initialization value is 1. Channel 6 Output Initialization Value CH6OI Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 871: Output Mask (Ftmx_Outmask)
This feature is used for BLDC control where the PWM signal is presented to an electric motor at specific times to provide electronic commutation. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 872 Channel output is masked. It is forced to its inactive state. Channel 3 Output Mask CH3OM Defines if the channel output is masked or unmasked. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 873: Function For Linked Channels (Ftmx_Combine)
Dual Edge Capture mode, Complementary, and Combine mode for each pair of channels (n) and (n+1), where n equals 0, 2, 4, and 6. Address: Base address + 64h offset Reset Reset KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 874 The channel (n+1) output is the same as the channel (n) output. The channel (n+1) output is the complement of the channel (n) output. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 875 The Dual Edge Capture mode in this pair of channels is disabled. The Dual Edge Capture mode in this pair of channels is enabled. Complement Of Channel (n) For n = 4 COMP2 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 876 Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in Dual Edge Capture mode according to Table 38-7. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 877 DECAP bit is cleared automatically by hardware if dual edge capture – one-shot mode is selected and when the capture of channel (n+1) event is made. The dual edge captures are inactive. The dual edge captures are active. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 878: Deadtime Insertion Control (Ftmx_Deadtime)
Selects the division factor of the system clock. This prescaled clock is used by the deadtime counter. This field is write protected. It can be written only when MODE[WPDIS] = 1. Divide the system clock by 1. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 879: Ftm External Trigger (Ftmx_Exttrig)
Several channels can be selected to generate multiple triggers in one PWM period. Channels 6 and 7 are not used to generate channel triggers. Address: Base address + 6Ch offset Reserved Reset KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 880 Enables the generation of the channel trigger when the FTM counter is equal to the CnV register. The generation of the channel trigger is disabled. The generation of the channel trigger is enabled. Channel 5 Trigger Enable CH5TRIG Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 881: Channels Polarity (Ftmx_Pol)
That is, the safe value of a channel is the value of its POL bit. Address: Base address + 70h offset Reserved Reset Reserved POL7 POL6 POL5 POL4 POL3 POL2 POL1 POL0 Reset KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 882 Channel 1 Polarity POL1 Defines the polarity of the channel output. This field is write protected. It can be written only when MODE[WPDIS] = 1. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 883: Fault Mode Status (Ftmx_Fms)
38.3.18 Fault Mode Status (FTMx_FMS) This register contains the fault detection flags, write protection enable bit, and the logic OR of the enabled fault inputs. Address: Base address + 74h offset Reset Reset KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 884 Writing a 1 to FAULTF2 has no effect. FAULTF2 bit is also cleared when FAULTF bit is cleared. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 885: Input Capture Filter Control (Ftmx_Filter)
Writing to the FILTER register has immediate effect and must be done only when the channels 0, 1, 2, and 3 are not in input modes. Failure to do this could result in a missing valid signal. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 886: Fault Control (Ftmx_Fltctrl)
38.3.20 Fault Control (FTMx_FLTCTRL) This register selects the filter value for the fault inputs, enables the fault inputs and the fault inputs filter. Address: Base address + 7Ch offset Reset FFVAL Reset KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 887 Enables the fault input. This field is write protected. It can be written only when MODE[WPDIS] = 1. Fault input is disabled. Fault input is enabled. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 888 Fault Input 0 Enable FAULT0EN Enables the fault input. This field is write protected. It can be written only when MODE[WPDIS] = 1. Fault input is disabled. Fault input is enabled. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 889: Quadrature Decoder Control And Status (Ftmx_Qdctrl)
CH0FVAL field of FILTER. The phase A filter is also disabled when CH0FVAL is zero. Phase A input filter is disabled. Phase A input filter is enabled. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 890 The Quadrature Decoder mode has precedence over the other modes. See Table 38-7. This field is write protected. It can be written only when MODE[WPDIS] = 1. Quadrature Decoder mode is disabled. Quadrature Decoder mode is enabled. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 891: Configuration (Ftmx_Conf)
Selects the FTM behavior in BDM mode. See mode. This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 892: Ftm Fault Input Polarity (Ftmx_Fltpol)
Fault Input 2 Polarity FLT2POL Defines the polarity of the fault input. This field is write protected. It can be written only when MODE[WPDIS] = 1. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 893: Synchronization Configuration (Ftmx_Synconf)
Reset FTMx_SYNCONF field descriptions Field Description 31–21 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 894 The software trigger activates the FTM counter synchronization. Synchronization Mode SYNCMODE Selects the PWM Synchronization mode. Legacy PWM synchronization is selected. Enhanced PWM synchronization is selected. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 895: Ftm Inverting Control (Ftmx_Invctrl)
This register has a write buffer. The INVmEN bit is updated by the INVCTRL register synchronization. Address: Base address + 90h offset Reset KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 896: Ftm Software Output Control (Ftmx_Swoctrl)
• The CHnOCV bits select the value that is forced at the corresponding channel (n) output. This register has a write buffer. The fields are updated by the SWOCTRL register synchronization. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 897 The software output control forces 0 to the channel output. The software output control forces 1 to the channel output. Channel 0 Software Output Control Value CH0OCV Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 898 The channel output is affected by software output control. Channel 0 Software Output Control Enable CH0OC The channel output is not affected by software output control. The channel output is affected by software output control. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 899: Ftm Pwm Load (Ftmx_Pwmload)
Include the channel in the matching process. Channel 5 Select CH5SEL Do not include the channel in the matching process. Include the channel in the matching process. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 900: Functional Description
Include the channel in the matching process. 38.4 Functional description The notation used in this document to represent the counters and the generation of the signals is shown in the following figure. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 901: Clock Source
Refer to the chip specific documentation for further information. Due to FTM hardware implementation limitations, the frequency of the fixed frequency clock must not exceed 1/2 of the system clock frequency. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 902: Prescaler
The FTM counter has these modes of operation: • Up counting • Up-down counting • Quadrature Decoder mode 38.4.3.1 Up counting Up counting is selected when: • QUADEN = 0, and • CPWMS = 0 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 903 FTM counting is up and signed. CNTIN[15] = 0 and CNTIN ≠ 0x0000 The initial value of the FTM counter is a positive number, so the FTM counting is up and unsigned. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 904 FTM operation difficult to comprehend. However, there is no restriction on this configuration, and an example is shown in the following figure. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 905 The TOF bit is set when the FTM counter changes from MOD to (MOD – 1). If (CNTIN = 0x0000), the FTM counting is equivalent to TPM up-down counting, that is, up-down and unsigned counting. See the following figure. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 906 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 TOF bit set TOF bit Figure 38-213. Example when the FTM counter is free running The FTM counter is also a free running counter when: KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 907 FTM counter NUMTOF[4:0] 0x02 TOF counter 0x01 0x01 0x00 0x02 0x00 0x02 0x01 0x02 set TOF bit Figure 38-214. Periodic TOF when NUMTOF = 0x02 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 908: Input Capture Mode
While in BDM, the input capture function works as configured. When a selected edge event occurs, the FTM counter value, which is frozen because of BDM, is captured into the CnV register and the CHnF bit is set. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 909 As long as the new state is stable on the input, the counter continues to increment. When the counter is equal to CHnFVAL[3:0], the state change of the input signal is validated. It is then transmitted as a pulse edge to the edge detector. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 910 The figure below shows the FTM counter reset when the selected input capture event is detected in a channel in input capture mode with ICRST = 1. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 911: Output Compare Mode
The CHnF bit is set and the channel (n) interrupt is generated if CHnIE = 1 at the channel (n) match (FTM counter = CnV). KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 912: Edge-Aligned Pwm (Epwm) Mode
CHnF bit is set and the channel (n) interrupt is generated if CHnIE = 1, however the channel (n) output is not modified and controlled by FTM. 38.4.6 Edge-Aligned PWM (EPWM) mode The Edge-Aligned mode is selected when: • QUADEN = 0 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 913 CNTIN register value is loaded into the FTM counter, and it is forced high at the channel (n) match (FTM counter = CnV). See the following figure. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 914: Center-Aligned Pwm (Cpwm) Mode
0x0001 to 0x7FFF because values outside this range can produce ambiguous results. In the CPWM mode, the FTM counter counts up until it reaches MOD and then counts down until it reaches CNTIN. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 915 If (ELSnB:ELSnA = X:1), then the channel (n) output is forced low at the channel (n) match (FTM counter = CnV) when counting down, and it is forced high at the channel (n) match when counting up. See the following figure. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 916: Combine Mode
(n) match (FTM counter = C(n)V). The CH(n+1)F bit is set and the channel (n +1) interrupt is generated, if CH(n+1)IE = 1, at the channel (n+1) match (FTM counter = C(n+1)V). KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 917 ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 Figure 38-230. Channel (n) output if (CNTIN < C(n)V < MOD) and (CNTIN < C(n+1)V < MOD) and (C(n)V < C(n+1)V) KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 918 (n) output with ELSnB:ELSnA = X:1 Figure 38-233. Channel (n) output if (CNTIN < C(n)V < MOD) and (C(n)V is Almost Equal to CNTIN) and (C(n+1)V = MOD) KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 919 ELSnB:ELSnA = 1:0 channel (n) output 100% duty cycle with ELSnB:ELSnA = X:1 Figure 38-235. Channel (n) output if C(n)V and C(n+1)V are not between CNTIN and MOD KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 920 (n) output 0% duty cycle with ELSnB:ELSnA = 1:0 channel (n) output 100% duty cycle with ELSnB:ELSnA = X:1 Figure 38-238. Channel (n) output if (C(n)V = C(n+1)V = MOD) KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 921 ELSnB:ELSnA = 1:0 channel (n) output 100% duty cycle with ELSnB:ELSnA = X:1 Figure 38-240. Channel (n) output if (C(n)V < CNTIN) and (CNTIN < C(n+1)V < MOD) KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 922 ELSnB:ELSnA = 1:0 channel (n) output 100% duty cycle with ELSnB:ELSnA = X:1 Figure 38-242. Channel (n) output if (C(n)V > MOD) and (CNTIN < C(n+1)V < MOD) KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 923: Complementary Mode
(n+1) match occurs, that is, FTM counter = C(n+1)V. So, Combine mode allows the generation of asymmetrical PWM signals. 38.4.9 Complementary mode The Complementary mode is selected when: KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 924: Registers Updated From Write Buffers
Figure 38-246. Channel (n+1) output in Complementary mode with (ELSnB:ELSnA = X:1) NOTE The complementary mode is not available in Output Compare mode. 38.4.10 Registers updated from write buffers KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 925 Table 38-305. CnV register update When Then CnV register is updated CLKS[1:0] = 0:0 When CnV register is written, independent of FTMEN bit. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 926: Pwm Synchronization
The PWM synchronization with hardware trigger is initiated when a rising edge is detected at the enabled hardware trigger inputs. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 927 PWMSYNC and REINIT bits. In this case if (PWMSYNC = 1) or (PWMSYNC = 0 and REINIT = 0) then SWSYNC bit is cleared at the next selected loading point after that the KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 928 For both counting modes, if neither CNTMIN nor CNTMAX are 1, then the boundary cycles are not used as loading points for registers updates. See the register synchronization descriptions in the following sections for details. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 929 = 0). However, it is expected that the MOD register be synchronized only by the enhanced PWM synchronization. In the case of enhanced PWM synchronization, the MOD register synchronization depends on SWWRBUF, SWRSTCNT, HWWRBUF, and HWRSTCNT bits according to this flowchart: KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 930 If the trigger event was a software trigger, then the SWSYNC bit is cleared on the next selected KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 931 SWSYNC bit is cleared according to the following example. If the trigger event was a hardware trigger, then the TRIGn bit is cleared according to Hardware trigger. Examples with software and hardware triggers follow. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 932 1 to SWSYNC bit SWSYNC bit software trigger event selected loading point MOD register is updated Figure 38-255. MOD synchronization with (SYNCMODE = 0) and (PWMSYNC = 1) KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 933 SYNCMODE = 0). However, it is expected that the OUTMASK register be synchronized only by the enhanced PWM synchronization. In the case of enhanced PWM synchronization, the OUTMASK register synchronization depends on SWOM and HWOM bits. See the following flowchart: KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 934 Figure 38-256. OUTMASK register synchronization flowchart In the case of legacy PWM synchronization, the OUTMASK register synchronization depends on PWMSYNC bit according to the following description. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 935 If (SYNCMODE = 0), (SYNCHOM = 1), and (PWMSYNC = 1), then this synchronization is made on the next enabled hardware trigger. The TRIGn bit is cleared according to Hardware trigger. An example with a hardware trigger follows. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 936 PWM synchronization (INVC = 1 and SYNCMODE = 1) according to the following flowchart. In the case of enhanced PWM synchronization, the INVCTRL register synchronization depends on SWINVC and HWINVC bits. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 937 HWTRIGMODE bit ? clear TRIGn bit Figure 38-260. INVCTRL register synchronization flowchart 38.4.11.9 SWOCTRL register synchronization The SWOCTRL register synchronization updates the SWOCTRL register with its buffer value. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 938 ? wait hardware trigger n update SWOCTRL with its buffer value update SWOCTRL with its buffer value HWTRIGMODE bit ? clear TRIGn bit Figure 38-261. SWOCTRL register synchronization flowchart KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 939 = 0). However, the FTM counter must be synchronized only by the enhanced PWM synchronization. In the case of enhanced PWM synchronization, the FTM counter synchronization depends on SWRSTCNT and HWRSTCNT bits according to the following flowchart. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 940 SWSYNC bit is cleared according to the following example. If the trigger event was a hardware trigger then the TRIGn bit is cleared according to Hardware trigger. Examples with software and hardware triggers follow. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 941 Figure 38-266. FTM counter synchronization with (SYNCMODE = 0), (HWTRIGMODE = 0), (REINIT = 1), (PWMSYNC = 1), and a hardware trigger was used KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 942: Inverting
INV(m) bit selects the inverting to the pair channels (n) and (n+1). Figure 38-267. Channels (n) and (n+1) outputs after the inverting in High-True (ELSnB:ELSnA = 1:0) Combine mode KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 943: Software Output Control
PWM generation. The software output control is selected when: • QUADEN = 0 • DECAPEN = 0, and • CHnOC = 1 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 944 Software output control forces the following values on channels (n) and (n+1) when the COMP bit is one. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 945: Deadtime Insertion
(FTM counter = C(n)V) occurs, the channel (n) output remains at the high value until the end of the deadtime delay when the channel (n) output is cleared. Similarly, KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 946 Figure 38-271. Deadtime insertion with ELSnB:ELSnA = X:1, POL(n) = 0, and POL(n+1) = NOTE • The deadtime feature must be used only in Complementary mode. • The deadtime feature is not available in Output Compare mode. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 947 Figure 38-272. Example of the deadtime insertion (ELSnB:ELSnA = 1:0, POL(n) = 0, and POL(n+1) = 0) when the deadtime delay is comparable to channel (n+1) duty cycle KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 948: Output Mask
If CHnOM = 1, then the channel (n) output is forced to its inactive state (POLn bit value). If CHnOM = 0, then the channel (n) output is unaffected by the output mask. See the following figure. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 949: Fault Control
When there is a state change in the fault input n signal, the 5-bit counter is reset and starts counting up. As long as the new state is stable on the fault input n, the KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 950 1 value FAULTIN fault input 2 value fault input 3 value FAULTIE fault interrupt FAULTF0 FAULTF1 FAULTF FAULTF2 FAULTF3 Figure 38-276. FAULTF and FAULTIN bits and fault interrupt KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 951 FAULTF bit is cleared NOTE The channel (n) output is after the fault control with automatic fault clearing and POLn = 0. Figure 38-277. Fault control with automatic fault clearing KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 952: Polarity Control
• If FLTjPOL = 1, the fault j input polarity is low, so the logical zero at the fault input j indicates a fault. 38.4.17 Polarity control The POLn bit selects the channel (n) output polarity: KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 953: Initialization
See the description of the CLKS field in the Status and Control register. 38.4.19 Features priority The following figure shows the priority of the features used at the generation of channels (n) and (n+1) outputs signals. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 954: Channel Trigger Output
If CHjTRIG = 1, where j = 0, 1, 2, 3, 4, or 5, then the FTM generates a trigger when the channel (j) match occurs (FTM counter = C(j)V). The channel trigger output provides a trigger signal that is used for on-chip modules. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 955: Initialization Trigger
• The FTM counter is automatically updated with the CNTIN register value by the selected counting mode. • When there is a write to CNT register. • When there is the FTM counter synchronization. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 956 0x04 0x05 0x06 0x07 0x00 0x01 0x02 0x03 0x04 0x05 FTM counter FTM counter synchronization initialization trigger Figure 38-283. Initialization trigger is generated when there is the FTM counter synchronization KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 957: Capture Test Mode
FTM counter and CnV registers. In this test mode, all channels must be configured for Input Capture mode and FTM counter must be configured to the counting. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 958: Dma
The channel interrupt is generated if (CHnF = 1). generated. The channel DMA transfer request is not The channel interrupt is not generated. generated. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 959: Dual Edge Capture Mode
* Filtering function for dual edge capture mode is only available in the channels 0 and 2 Figure 38-287. Dual Edge Capture mode block diagram The MS(n)A bit defines if the Dual Edge Capture mode is one-shot or continuous. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 960 The edge captures are enabled while DECAP bit is set. For each new measurement in One-Shot Capture mode, first the CH(n)F and CH(n+1) bits must be cleared, and then the DECAP bit must be set. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 961 The DECAPEN bit selects the Dual Edge Capture mode, so it remains set. The DECAP bit is set to enable the measurement of next KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 962 The CH(n)F bit is set when the first edge of the positive polarity pulse is detected, that is, the edge selected by ELS(n)B:ELS(n)A bits. The CH(n+1)F bit KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 963 If both channels (n) and (n+1) are configured to capture falling edges (ELS(n)B:ELS(n)A = 1:0 and ELS(n+1)B:ELS(n+1)A = 1:0), then the period between two consecutive falling edges is measured. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 964 - Problem 3: channel (n) input = 1, set DECAP, not clear CH(n)F, and not clear CH(n+1)F. Figure 38-290. Dual Edge Capture – One-Shot mode to measure of the period between two consecutive rising edges KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 965 The Dual Edge Capture mode implements a read coherency mechanism between the FTM counter value captured in C(n)V and C(n+1)V registers. The read coherency mechanism is illustrated in the following figure. In this example, the channels (n) and (n KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 966: Quadrature Decoder Mode
The Quadrature Decoder mode is selected if (QUADEN = 1). The Quadrature Decoder mode uses the input signals phase A and B to control the FTM counter increment and decrement. The following figure shows the quadrature decoder block diagram. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 967 An edge at phase A must not occur together an edge at phase B and vice-versa. The PHAPOL bit selects the polarity of the phase A input, and the PHBPOL bit selects the polarity of the phase B input. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 968 • there is a rising edge at phase B signal and phase A signal is at logic zero; • there is a rising edge at phase A signal and phase B signal is at logic one. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 969 FTM counter changes from CNTIN to MOD, TOF bit is set and TOFDIR bit is cleared. TOF bit indicates the FTM counter overflow occurred. TOFDIR indicates the counting was down when the FTM counter overflow occurred. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 970 FTM counter CNTIN 0x0000 Time Figure 38-298. Motor position jittering in a mid count value The following figure shows motor jittering produced by the phase B and A pulses respectively: KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 971: Bdm Mode
The channels outputs are frozen Writes to these registers bypass the registers when the chip enters in BDM buffers mode Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 972: Intermediate Load
In this case, it is not required to use the PWM synchronization. There are multiple possible loading points for intermediate load: KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 973 Table 38-315. Conditions for loads occurring at the next enabled loading point When a new value was written Then To the MOD register The MOD register is updated with its write buffer value. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 974: Global Time Base (Gtb)
FTM module B FTM counter GTBEEN bit FTM counter enable enable logic gtb_in gtb_in example glue logic gtb_out GTBEOUT bit gtb_out Figure 38-301. Global time base (GTB) block diagram KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 975 5. Reset the FTM counter: Write any value to the CNT register. To initiate the GTB feature in the configuration described in the preceding figure, write 1 to CONF[GTBEOUT] in the FTM module used as the time base. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 976: Reset Overview
The next step is to select the FTM counter clock by the CLKS[1:0] bits (item 4). It is important to highlight that the pins are only controlled by FTM when CLKS[1:0] bits are different from zero (See the table in the description of CnSC register). KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 977: Ftm Interrupts
– Channel (n) is in output compare and the channel (n) output is toggled when there is a match – C(n)V = 0x0014 Figure 38-303. FTM behavior after reset when the channel (n) is in Output Compare mode 38.6 FTM Interrupts KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 978: Timer Overflow Interrupt
• Do not use the Inverting without SW synchronization (see item 6). • Do not use the Initialization. • Do not change the polarity control. • Do not configure the HW synchronization KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 979 • Generate the Software Trigger Write to SYNC (SWSYNC = 1, TRIG2 = 0, TRIG1 = 0, TRIG0 = 0, SYNCHOM = 1, REINIT = 0, CNTMAX = 0, CNTMIN = 0) KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 980 Initialization Procedure KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 981: Periodic Interrupt Timer (Pit)
The PIT module is an array of timers that can be used to raise interrupts and trigger DMA channels. 39.1.1 Block diagram The following figure shows the block diagram of the PIT module. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 982: Features
• Ability of timers to generate DMA trigger pulses • Ability of timers to generate interrupts • Maskable interrupts • Independent timeout periods for each timer 39.2 Signal description The PIT module has no external pins. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 983: Memory Map/Register Description
39.3.1 PIT Module Control Register (PIT_MCR) This register enables or disables the PIT timer clocks and controls the timers when the PIT enters the Debug mode. Access: User read/write KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 984 Clock for standard PIT timers is disabled. Freeze Allows the timers to be stopped when the device enters the Debug mode. Timers continue to run in Debug mode. Timers are stopped in Debug mode. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 985: Timer Load Value Register (Pit_Ldvaln)
• If the timer is disabled, do not use this field as its value is unreliable. • The timer uses a downcounter. The timer values are frozen in Debug mode if MCR[FRZ] is set. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 986: Timer Control Register (Pit_Tctrln)
Timer Enable Enables or disables the timer. Timer n is disabled. Timer n is enabled. 39.3.5 Timer Flag Register (PIT_TFLGn) These registers hold the PIT interrupt flags. Access: User read/write KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 987: Functional Description
Each time a timer reaches 0, it will generate a trigger pulse and set the interrupt flag. All interrupts can be enabled or masked by setting TCTRLn[TIE]. A new interrupt can be generated only after the previous one is cleared. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 988 LDVAL with the new load value. This value will then be loaded after the next trigger event. See the following figure. Timer enabled New start Value p2 set Start value = p1 Trigger event Figure 39-25. Dynamically setting a new load value KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 989: Interrupts
5.12 ms/20 ns = 256,000 cycles and Timer 3 every 30 ms/20 ns = 1,500,000 cycles. The value for the LDVAL register trigger is calculated as: LDVAL trigger = (period / clock period) -1 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 990: Example Configuration For Chained Timers
The interrupt for Timer 2 is enabled by setting TCTRL2[TIE], the Chain mode is activated by setting TCTRL2[CHN], and the timer is started by writing a 1 to TCTRL2[TEN]. TCTRL1[TEN] needs to be set, and TCTRL1[CHN] and TCTRL1[TIE] are cleared. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 991 PIT_TCTRL2 |= TEN; // start Timer 2 // Timer 1 PIT_LDVAL1 = 0x23C345FF; // setup Timer 1 for 600 000 000 cycles PIT_TCTRL1 = TEN; // start Timer 1 KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 992 Example configuration for chained timers KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 993: Low-Power Timer (Lptmr)
• Configurable clock source for prescaler/glitch filter • Configurable input source for pulse counter • Rising-edge or falling-edge 40.1.2 Modes of operation The following table describes the operation of the LPTMR module in various modes. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 994: Lptmr Signal Descriptions
CNR to increment. Timing Assertion or deassertion may occur at any time; input may assert asynchronously to the bus clock. 40.3 Memory map and register definition KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 995: Low Power Timer Control Status Register (Lptmrx_Csr)
LPTMR is disabled. The input connections vary by device. See the chip configuration details for information on the connections to these inputs. Pulse counter input 0 is selected. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 996: Low Power Timer Prescale Register (Lptmrx_Psr)
LPTMR is disabled and internal logic is reset. LPTMR is enabled. 40.3.2 Low Power Timer Prescale Register (LPTMRx_PSR) Address: 4004_0000h base + 4h offset = 4004_0004h Reset PRESCALE PBYP Reset KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 997 LPTMR is disabled. The clock connections vary by device. NOTE: See the chip configuration details for information on the connections to these inputs. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 998: Low Power Timer Compare Register (Lptmrx_Cmr)
Address: 4004_0000h base + Ch offset = 4004_000Ch COUNTER Reset LPTMRx_CNR field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 15–0 Counter Value COUNTER KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 999: Functional Description
40.4.3 LPTMR prescaler/glitch filter The LPTMR prescaler and glitch filter share the same logic which operates as a prescaler in Time Counter mode and as a glitch filter in Pulse Counter mode. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 Freescale Semiconductor, Inc.
Page 1000 CNR can increment is once every 2 to 2 prescaler clock edges. When first enabled, the glitch filter will wait an additional one or two prescaler clock edges due to synchronization logic. KV31F Sub-Family Reference Manual , Rev. 3, 7/2014 1000 Freescale Semiconductor, Inc.

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