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Freescale Semiconductor MK22FN256VLH12 Reference Manual (1313 pages)

K22F series Sub-Family

Brand: Freescale Semiconductor | Category: Microcontrollers | Size: 13 MB

Table of Contents
3
Chapter 1 About this Document

47
- Overview
  47
  - Purpose
    47
  - Audience
    47
- Conventions
  47
  - Numbering Systems
    47
  - Typographic Notation
    48
  - Special Terms
    48
Chapter 2 Introduction

49
- Overview
  49
- Module Functional Categories
  49
  - ARM® Cortex®-M4 Core Modules
    50
  - System Modules
    51
  - Memories and Memory Interfaces
    52
  - Clocks
    52
  - Security and Integrity Modules
    53
  - Analog Modules
    53
  - Timer Modules
    53
  - Communication Interfaces
    54
  - Human-Machine Interfaces
    55
- Orderable Part Numbers
  55
Chapter 3 Chip Configuration

57
- Introduction
  57
- Core Modules
  57
- System Modules
  67
- Clock Modules
  81
  - MCG Configuration
    81
  - OSC Configuration
    83
  - RTC OSC Configuration
    83
- Memories and Memory Interfaces
  84
- Security
  91
  - CRC Configuration
    92
  - RNG Configuration
    92
- Analog
  93
  - 16-Bit SAR ADC Configuration
    93
  - CMP Configuration
    101
  - 12-Bit DAC Configuration
    103
  - VREF Configuration
    104
- Timers
  105
  - PDB Configuration
    105
  - Flextimer Configuration
    108
  - PIT Configuration
    114
  - Low-Power Timer Configuration
    115
  - RTC Configuration
    117
- Communication Interfaces
  118
  - Universal Serial Bus (USB) FS Subsystem
    118
  - SPI Configuration
    123
  - I2C Configuration
    127
  - UART Configuration
    128
  - LPUART Configuration
    130
  - I2S Configuration
    131
- Human-Machine Interfaces
  134
  - GPIO Configuration
    134
Chapter 4 Memory Map

137
Chapter 5 Clock Distribution

147
- Introduction
  147
- Programming Model
  147
- High-Level Device Clocking Diagram
  147
- Clock Definitions
  148
  - Device Clock Summary
    149
- Internal Clocking Requirements
  152
  - Clock Divider Values after Reset
    153
  - VLPR Mode Clocking
    153
- Clock Gating
  154
- Module Clocks
  154
  - PMC 1-Khz LPO Clock
    156
  - IRC 48Mhz Clock
    156
  - WDOG Clocking
    157
  - Debug Trace Clock
    157
  - PORT Digital Filter Clocking
    158
  - LPTMR Clocking
    158
  - RTC_CLKOUT and CLKOUT32K Clocking
    159
  - USB FS OTG Controller Clocking
    160
  - UART Clocking
    161
  - LPUART0 Clocking
    161
  - I2S/SAI Clocking
    162
Chapter 6 Reset and Boot

165
- Introduction
  165
- Reset
  166
  - Power-On Reset (POR)
    166
  - System Reset Sources
    166
  - MCU Resets
    170
  - Reset Pin
    171
  - Debug Resets
    172
- Boot
  173
  - Boot Sources
    173
  - Boot Options
    173
  - FOPT Boot Options
    174
  - Boot Sequence
    175
Chapter 7 Power Management

177
- Introduction
  177
- Clocking Modes
  177
  - Partial Stop
    177
  - DMA Wakeup
    178
  - Compute Operation
    179
  - Peripheral Doze
    180
  - Clock Gating
    181
- Power Modes Description
  181
- Entering and Exiting Power Modes
  183
- Power Mode Transitions
  184
- Power Modes Shutdown Sequencing
  185
- Flash Program Restrictions
  186
- Module Operation in Low Power Modes
  186
Chapter 8 Security

191
- Introduction
  191
- Flash Security
  191
- Security Interactions with Other Modules
  192
  - Security Interactions with Ezport
    192
  - Security Interactions with Debug
    192
Chapter 9 Debug

193
- Introduction
  193
  - References
    195
- The Debug Port
  195
  - JTAG-To-SWD Change Sequence
    196
  - JTAG-To-Cjtag Change Sequence
    196
- Debug Port Pin Descriptions
  197
- System TAP Connection
  197
  - IR Codes
    198
- JTAG Status and Control Registers
  198
  - MDM-AP Control Register
    199
  - MDM-AP Status Register
    201
- Debug Resets
  202
- Ahb-Ap
  203
- Itm
  203
- Core Trace Connectivity
  204
- Tpiu
  204
- Dwt
  204
- Debug in Low Power Modes
  205
  - Debug Module State in Low Power Modes
    205
- Debug & Security
  206
Chapter 10 Signal Multiplexing and Signal Descriptions

207
- Introduction
  207
- Signal Multiplexing Integration
  207
  - Port Control and Interrupt Module Features
    208
  - Clock Gating
    209
  - Signal Multiplexing Constraints
    209
- Pinout
  209
  - K22F Signal Multiplexing and Pin Assignments
    209
  - K22F Pinouts
    214
- Module Signal Description Tables
  218
  - Core Modules
    219
  - System Modules
    219
  - Clock Modules
    220
  - Memories and Memory Interfaces
    220
  - Analog
    220
  - Timer Modules
    222
  - Communication Interfaces
    223
  - Human-Machine Interfaces (HMI)
    226
Chapter 11 Port Control and Interrupts (PORT)

227
- Introduction
  227
- Overview
  227
  - Features
    227
  - Modes of Operation
    228
- External Signal Description
  229
- Detailed Signal Description
  229
- Memory Map and Register Definition
  229
- Functional Description
  242
  - Pin Control
    242
  - Global Pin Control
    243
  - External Interrupts
    243
  - Digital Filter
    244
Chapter 12 System Integration Module (SIM)

247
Chapter 13 Kinetis Flashloader

279
- Chip-Specific Information
  279
- Introduction
  279
- Functional Description
  281
  - Memory Maps
    281
  - Kinetis Flashloader
    281
  - Start-Up Process
    282
  - Clock Configuration
    283
  - Flashloader Protocol
    284
  - Flashloader Packet Types
    288
  - Flashloader Command API
    295
  - Flashloader Exit State
    314
- Peripherals Supported
  315
  - I2C Peripheral
    315
  - SPI Peripheral
    316
  - UART Peripheral
    318
  - USB Peripheral
    321
- Get/Setproperty Command Properties
  323
  - Property Definitions
    324
- Kinetis Flashloader Status Error Codes
  326
Chapter 14 Reset Control Module (RCM)

329
- Introduction
  329
- Reset Memory Map and Register Descriptions
  329
Chapter 15 System Mode Controller (SMC)

339
- Introduction
  339
- Modes of Operation
  339
- Memory Map and Register Descriptions
  341
- Functional Description
  347
  - Power Mode Transitions
    347
  - Power Mode Entry/Exit Sequencing
    350
  - Run Modes
    352
  - Wait Modes
    354
  - Stop Modes
    355
  - Debug in Low Power Modes
    358
Chapter 16 Power Management Controller (PMC)

361
- Introduction
  361
- Features
  361
- Low-Voltage Detect (LVD) System
  361
  - LVD Reset Operation
    362
  - LVD Interrupt Operation
    362
  - Low-Voltage Warning (LVW) Interrupt Operation
    362
- I/O Retention
  363
- Memory Map and Register Descriptions
  363
Chapter 17 Low-Leakage Wakeup Unit (LLWU)

369
- Introduction
  369
  - Features
    369
  - Modes of Operation
    370
  - Block Diagram
    371
- LLWU Signal Descriptions
  372
- Memory Map/Register Definition
  372
- Functional Description
  386
  - LLS Mode
    387
  - VLLS Modes
    387
  - Initialization
    387
Chapter 18 Miscellaneous Control Module (MCM)

389
Chapter 19 Crossbar Switch Lite (AXBS-Lite)

397
- Introduction
  397
  - Features
    397
- Memory Map / Register Definition
  398
- Functional Description
  398
  - General Operation
    398
  - Arbitration
    399
- Initialization/Application Information
  400
Chapter 20 Peripheral Bridge (AIPS-Lite)

403
- Introduction
  403
  - Features
    403
  - General Operation
    403
- Functional Description
  404
  - Access Support
    404
Chapter 21 Direct Memory Access Multiplexer (DMAMUX)

405
- Introduction
  405
  - Overview
    405
  - Features
    406
  - Modes of Operation
    406
- External Signal Description
  407
- Memory Map/Register Definition
  407
  - Channel Configuration Register (Dmamux_Chcfgn)
    408
- Functional Description
  409
- Initialization/Application Information
  413
  - Reset
    413
  - Enabling and Configuring Sources
    413
Chapter 22 Enhanced Direct Memory Access (Edma)

417
Chapter 23 External Watchdog Monitor (EWM)

501
- Introduction
  501
  - Features
    501
  - Modes of Operation
    502
  - Block Diagram
    503
- EWM Signal Descriptions
  504
- Memory Map/Register Definition
  504
- Functional Description
  507
  - The Ewm_Out Signal
    507
  - The Ewm_In Signal
    508
  - EWM Counter
    509
  - EWM Compare Registers
    509
  - EWM Refresh Mechanism
    509
  - EWM Interrupt
    510
  - Counter Clock Prescaler
    510
Chapter 24 Watchdog Timer (WDOG)

511
- Introduction
  511
- Features
  511
- Functional Overview
  513
  - Unlocking and Updating the Watchdog
    514
  - Watchdog Configuration Time (WCT)
    515
  - Refreshing the Watchdog
    516
  - Windowed Mode of Operation
    516
  - Watchdog Disabled Mode of Operation
    516
  - Debug Modes of Operation
    517
- Testing the Watchdog
  517
  - Quick Test
    518
  - Byte Test
    518
- Backup Reset Generator
  519
- Generated Resets and Interrupts
  520
- Memory Map and Register Definition
  520
- Watchdog Operation with 8-Bit Access
  527
  - General Guideline
    527
  - Refresh and Unlock Operations with 8-Bit Access
    528
- Restrictions on Watchdog Operation
  529
Chapter 25 Multipurpose Clock Generator (MCG)

531
- Introduction
  531
  - Features
    531
  - Modes of Operation
    535
- External Signal Description
  535
- Memory Map/Register Definition
  535
- Functional Description
  548
  - MCG Mode State Diagram
    548
  - Low-Power Bit Usage
    553
  - MCG Internal Reference Clocks
    553
  - External Reference Clock
    554
  - MCG Fixed Frequency Clock
    554
  - MCG PLL Clock
    555
  - MCG Auto TRIM (ATM)
    555
- Initialization / Application Information
  556
  - MCG Module Initialization Sequence
    556
  - Using a 32.768 Khz Reference
    559
  - MCG Mode Switching
    559
Chapter 26 Oscillator (OSC)

569
- Introduction
  569
- Features and Modes
  569
- Block Diagram
  570
- OSC Signal Descriptions
  570
- External Crystal / Resonator Connections
  571
- External Clock Connections
  572
- Memory Map/Register Definitions
  573
  - OSC Memory Map/Register Definition
    573
- Functional Description
  575
  - OSC Module States
    575
  - OSC Module Modes
    577
  - Counter
    579
  - Reference Clock Pin Requirements
    579
- Reset
  579
- Low Power Modes Operation
  580
- Interrupts
  580
Chapter 27 RTC Oscillator (OSC32K)

581
- Introduction
  581
  - Features and Modes
    581
  - Block Diagram
    581
- RTC Signal Descriptions
  582
  - EXTAL32 - Oscillator Input
    582
  - XTAL32 - Oscillator Output
    582
- External Crystal Connections
  583
- Memory Map/Register Descriptions
  583
- Functional Description
  583
- Reset Overview
  584
- Interrupts
  584
Chapter 28 Flash Memory Controller (FMC)

585
- Introduction
  585
  - Overview
    585
  - Features
    586
- Modes of Operation
  586
- External Signal Description
  586
- Memory Map and Register Descriptions
  586
- Functional Description
  607
  - Default Configuration
    607
  - Configuration Options
    608
  - Speculative Reads
    609
- Initialization and Application Information
  609
Chapter 29 Flash Memory Module (FTFA)

611
- Introduction
  611
  - Features
    612
  - Block Diagram
    612
  - Glossary
    613
- External Signal Description
  614
- Memory Map and Registers
  614
  - Flash Configuration Field Description
    615
  - Program Flash IFR Map
    615
  - Register Descriptions
    616
- Functional Description
  630
  - Flash Protection
    630
  - Flash Access Protection
    631
  - Interrupts
    632
  - Flash Operation in Low-Power Modes
    633
  - Functional Modes of Operation
    633
  - Flash Reads and Ignored Writes
    633
  - Read While Write (RWW)
    634
  - Flash Program and Erase
    634
  - Flash Command Operations
    634
  - Margin Read Commands
    638
  - Flash Command Description
    639
  - Security
    653
  - Reset Sequence
    655
- Overview
  657
Chapter 30

658
- Block Diagram
  658
- Features
  658
- Modes of Operation
  658
- External Signal Descriptions
  659
  - Ezport Clock (EZP_CK)
    659
  - Ezport Chip Select (EZP_CS)
    660
  - Ezport Serial Data in (EZP_D)
    660
  - Ezport Serial Data out (EZP_Q)
    660
- Command Definition
  660
  - Command Descriptions
    661
- Flash Memory Map for Ezport Access
  668
Chapter 31 Cyclic Redundancy Check (CRC)

671
- Introduction
  671
  - Features
    671
  - Block Diagram
    671
  - Modes of Operation
    672
- Memory Map and Register Descriptions
  672
- Functional Description
  675
  - CRC Initialization/Reinitialization
    675
  - CRC Calculations
    676
  - Transpose Feature
    677
  - CRC Result Complement
    679
Chapter 32 Random Number Generator Accelerator (RNGA)

681
- Introduction
  681
  - Overview
    681
- Modes of Operation
  682
  - Entering Normal Mode
    682
  - Entering Sleep Mode
    682
- Memory Map and Register Definition
  683
  - RNGA Control Register (RNG_CR)
    683
  - RNGA Status Register (RNG_SR)
    685
  - RNGA Entropy Register (RNG_ER)
    687
  - RNGA Output Register (RNG_OR)
    687
- Functional Description
  688
  - Output (OR) Register
    688
  - Core Engine / Control Logic
    688
- Initialization/Application Information
  689
Chapter 33 Analog-To-Digital Converter (ADC)

691
Chapter 34 Comparator (CMP)

745
- Introduction
  745
  - CMP Features
    745
  - 6-Bit DAC Key Features
    746
  - ANMUX Key Features
    746
  - CMP, DAC and ANMUX Diagram
    747
  - CMP Block Diagram
    748
- Memory Map/Register Definitions
  750
- Functional Description
  756
  - CMP Functional Modes
    756
  - Power Modes
    765
  - Startup and Operation
    766
  - Low-Pass Filter
    767
- CMP Interrupts
  769
- DMA Support
  769
- CMP Asynchronous DMA Support
  770
- Digital-To-Analog Converter
  771
- DAC Functional Description
  771
  - Voltage Reference Source Select
    771
- DAC Resets
  772
- DAC Clocks
  772
- DAC Interrupts
  772
Chapter 35 12-Bit Digital-To-Analog Converter (DAC)

773
- Introduction
  773
- Features
  773
- Block Diagram
  773
- Memory Map/Register Definition
  774
  - DAC Data Low Register (Dacx_Datnl)
    776
  - DAC Data High Register (Dacx_Datnh)
    776
  - DAC Status Register (Dacx_Sr)
    777
  - DAC Control Register (Dacx_C0)
    778
  - DAC Control Register 1 (Dacx_C1)
    779
  - DAC Control Register 2 (Dacx_C2)
    780
- Functional Description
  780
  - DAC Data Buffer Operation
    780
  - DMA Operation
    782
  - Resets
    782
  - Low-Power Mode Operation
    782
Chapter 36 Voltage Reference (VREFV1)

785
- Introduction
  785
  - Overview
    786
  - Features
    786
  - Modes of Operation
    787
  - VREF Signal Descriptions
    787
- Memory Map and Register Definition
  788
  - VREF Trim Register (VREF_TRM)
    788
  - VREF Status and Control Register (VREF_SC)
    789
- Functional Description
  790
- Initialization/Application Information
  793
- Introduction
  795
  - Features
    795
  - Implementation
    796
Chapter 37 Programmable Delay Block (PDB)

797
- Back-To-Back Acknowledgment Connections
  797
- DAC External Trigger Input Connections
  797
- Block Diagram
  797
- Modes of Operation
  799
- PDB Signal Descriptions
  799
- Memory Map and Register Definition
  799
- Functional Description
  809
  - PDB Pre-Trigger and Trigger Outputs
    809
  - PDB Trigger Input Source Selection
    811
  - Pulse-Out's
    811
  - Updating the Delay Registers
    812
  - Interrupts
    813
  - Dma
    813
- Application Information
  814
  - Impact of Using the Prescaler and Multiplication Factor on Timing Resolution
    814
- Introduction
  815
  - Flextimer Philosophy
    815
  - Features
    816
Chapter 38 Flextimer Module (FTM)

817
- Modes of Operation
  817
- Block Diagram
  818
- FTM Signal Descriptions
  820
- Memory Map and Register Definition
  820
  - Memory Map
    820
  - Register Descriptions
    821
  - Status and Control (Ftmx_Sc)
    826
  - Counter (Ftmx_Cnt)
    827
  - Modulo (Ftmx_Mod)
    828
  - Channel (N) Status and Control (Ftmx_Cnsc)
    829
  - Channel (N) Value (Ftmx_Cnv)
    832
  - Counter Initial Value (Ftmx_Cntin)
    832
  - Capture and Compare Status (Ftmx_Status)
    833
  - Features Mode Selection (Ftmx_Mode)
    835
  - Synchronization (Ftmx_Sync)
    837
  - Initial State for Channels Output (Ftmx_Outinit)
    839
  - Output Mask (Ftmx_Outmask)
    840
  - Function for Linked Channels (Ftmx_Combine)
    842
  - Deadtime Insertion Control (Ftmx_Deadtime)
    847
  - FTM External Trigger (Ftmx_Exttrig)
    848
  - Channels Polarity (Ftmx_Pol)
    850
  - Fault Mode Status (Ftmx_Fms)
    852
  - Input Capture Filter Control (Ftmx_Filter)
    854
  - Fault Control (Ftmx_Fltctrl)
    855
  - Quadrature Decoder Control and Status (Ftmx_Qdctrl)
    858
  - Configuration (Ftmx_Conf)
    860
  - FTM Fault Input Polarity (Ftmx_Fltpol)
    861
  - Synchronization Configuration (Ftmx_Synconf)
    862
  - FTM Inverting Control (Ftmx_Invctrl)
    864
  - FTM Software Output Control (Ftmx_Swoctrl)
    865
  - FTM PWM Load (Ftmx_Pwmload)
    868
- Functional Description
  869
  - Clock Source
    870
  - Prescaler
    871
  - Counter
    871
  - Input Capture Mode
    877
  - Output Compare Mode
    880
  - Edge-Aligned PWM (EPWM) Mode
    881
  - Center-Aligned PWM (CPWM) Mode
    883
  - Combine Mode
    885
  - Complementary Mode
    892
  - Registers Updated from Write Buffers
    893
  - PWM Synchronization
    895
  - Inverting
    911
  - Software Output Control
    912
  - Deadtime Insertion
    914
  - Output Mask
    917
  - Fault Control
    918
  - Polarity Control
    921
  - Initialization
    922
  - Features Priority
    922
  - Channel Trigger Output
    923
  - Initialization Trigger
    924
  - Capture Test Mode
    926
  - Dma
    927
  - Dual Edge Capture Mode
    928
  - Quadrature Decoder Mode
    935
  - BDM Mode
    940
  - Intermediate Load
    941
  - Global Time Base (GTB)
    943
- Reset Overview
  945
- FTM Interrupts
  946
  - Timer Overflow Interrupt
    947
  - Channel (N) Interrupt
    947
  - Fault Interrupt
    947
- Initialization Procedure
  947
Chapter 39 Periodic Interrupt Timer (PIT)

949
- Introduction
  949
  - Block Diagram
    949
  - Features
    950
- Signal Description
  950
- Memory Map/Register Description
  951
- Functional Description
  955
  - General Operation
    955
  - Interrupts
    957
  - Chained Timers
    957
- Initialization and Application Information
  957
- Example Configuration for Chained Timers
  958
Chapter 40 Low-Power Timer (LPTMR)

961
- Introduction
  961
  - Features
    961
  - Modes of Operation
    961
- LPTMR Signal Descriptions
  962
  - Detailed Signal Descriptions
    962
- Memory Map and Register Definition
  962
- Functional Description
  967
  - LPTMR Power and Reset
    967
  - LPTMR Clocking
    967
  - LPTMR Prescaler/Glitch Filter
    967
  - LPTMR Compare
    969
  - LPTMR Counter
    969
  - LPTMR Hardware Trigger
    970
  - LPTMR Interrupt
    970
Chapter 41 Real Time Clock (RTC)

971
- Introduction
  971
  - Features
    971
  - Modes of Operation
    971
  - RTC Signal Descriptions
    972
- Register Definition
  973
- Functional Description
  984
  - Power, Clocking, and Reset
    984
  - Time Counter
    985
  - Compensation
    986
  - Time Alarm
    986
  - Update Mode
    987
  - Register Lock
    987
  - Access Control
    987
  - Interrupt
    987
Chapter 42 Universal Serial Bus Full Speed OTG Controller (USBFSOTG)

989
- Introduction
  989
  - Usb
    989
  - USB On-The-Go
    990
  - USBFS Features
    991
- Functional Description
  991
  - Data Structures
    991
- Programmers Interface
  992
  - Buffer Descriptor Table
    992
  - RX Vs. TX as a USB Target Device or USB Host
    993
  - Addressing BDT Entries
    994
  - Buffer Descriptors (Bds)
    994
  - USB Transaction
    997
- Memory Map/Register Definitions
  999
- OTG and Host Mode Operation
  1027
- Host Mode Operation Examples
  1028
- On-The-Go Operation
  1031
  - OTG Dual Role a Device Operation
    1031
  - OTG Dual Role B Device Operation
    1033
- Device Mode IRC48 Operation
  1034
Chapter 43 Serial Peripheral Interface (SPI)

1041
- Introduction
  1041
  - Block Diagram
    1041
  - Features
    1042
  - Interface Configurations
    1044
  - Modes of Operation
    1044
- Module Signal Descriptions
  1046
  - PCS0/SS-Peripheral Chip Select/Slave Select
    1046
  - PCS1-PCS3-Peripheral Chip Selects 1-3
    1047
  - PCS4-Peripheral Chip Select 4
    1047
  - PCS5/PCSS-Peripheral Chip Select 5/Peripheral Chip Select Strobe
    1047
  - SCK-Serial Clock
    1047
  - SIN-Serial Input
    1047
  - SOUT-Serial Output
    1048
- Memory Map/Register Definition
  1048
- Functional Description
  1069
  - Start and Stop of Module Transfers
    1070
  - Serial Peripheral Interface (SPI) Configuration
    1070
  - Module Baud Rate and Clock Delay Generation
    1074
  - Transfer Formats
    1078
  - Continuous Serial Communications Clock
    1083
  - Slave Mode Operation Constraints
    1084
  - Interrupts/Dma Requests
    1085
  - Power Saving Features
    1087
- Initialization/Application Information
  1088
  - How to Manage Queues
    1088
  - Switching Master and Slave Mode
    1089
  - Initializing Module in Master/Slave Modes
    1090
  - Baud Rate Settings
    1090
  - Delay Settings
    1091
  - Calculation of FIFO Pointer Addresses
    1091
Chapter 45 Inter-Integrated Circuit (I2C)

1095
- Introduction
  1095
  - Features
    1095
  - Modes of Operation
    1096
  - Block Diagram
    1096
- I2C Signal Descriptions
  1097
- Memory Map/Register Definition
  1098
  - I2C Address Register 1 (I2Cx_A1)
    1099
  - I2C Frequency Divider Register (I2Cx_F)
    1099
  - I2C Control Register 1 (I2Cx_C1)
    1100
  - I2C Status Register (I2Cx_S)
    1102
  - I2C Data I/O Register (I2Cx_D)
    1104
  - I2C Control Register 2 (I2Cx_C2)
    1104
  - I2C Programmable Input Glitch Filter Register (I2Cx_Flt)
    1105
  - I2C Range Address Register (I2Cx_Ra)
    1107
  - I2C Smbus Control and Status Register (I2Cx_Smb)
    1107
  - I2C Address Register 2 (I2Cx_A2)
    1109
  - I2C SCL Low Timeout Register High (I2Cx_Slth)
    1109
  - I2C SCL Low Timeout Register Low (I2Cx_Sltl)
    1110
- Functional Description
  1110
  - I2C Protocol
    1110
  - 10-Bit Address
    1115
  - Address Matching
    1117
  - System Management Bus Specification
    1118
  - Resets
    1120
  - Interrupts
    1120
  - Programmable Input Glitch Filter
    1123
  - Address Matching Wake-Up
    1123
  - DMA Support
    1124
- Initialization/Application Information
  1125
  - Modes of Operation
    1131
- UART Signal Descriptions
  1132
  - Detailed Signal Descriptions
    1132
- Memory Map and Registers
  1133
- Functional Description
  1173
  - Transmitter
    1173
  - Receiver
    1179
  - Baud Rate Generation
    1193
  - Data Format (Non ISO-7816)
    1195
  - Single-Wire Operation
    1198
  - Loop Operation
    1199
  - ISO-7816/Smartcard Support
    1199
  - Infrared Interface
    1205
- Reset
  1206
- System Level Interrupt Sources
  1206
  - RXEDGIF Description
    1206
- DMA Operation
  1207
- Application Information
  1208
  - Initialization Sequence
    1208
  - Initialization Sequence (Non ISO-7816)
    1210
  - Overrun (OR) Flag Implications
    1211
  - Overrun NACK Considerations
    1212
  - Match Address Registers
    1213
  - Modem Feature
    1213
  - Irda Minimum Pulse Width
    1214
  - Clearing 7816 Wait Timer (WT, BWT, CWT) Interrupts
    1214
  - Legacy and Reverse Compatibility Considerations
    1215
Chapter 47 Low Power Universal Asynchronous Receiver/Transmitter (LPUART)

1217
- Introduction
  1217
  - Features
    1217
  - Modes of Operation
    1218
  - Signal Descriptions
    1218
  - Block Diagram
    1219
- Register Definition
  1220
- Functional Description
  1236
  - Baud Rate Generation
    1236
  - Transmitter Functional Description
    1237
  - Receiver Functional Description
    1240
  - Additional LPUART Functions
    1246
  - Infrared Interface
    1248
  - Interrupts and Status Flags
    1249
Chapter 48 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI)

1251
- Introduction
  1251
  - Features
    1251
  - Block Diagram
    1252
  - Modes of Operation
    1252
- External Signals
  1253
- Memory Map and Register Definition
  1254
- Functional Description
  1279
  - SAI Clocking
    1279
  - SAI Resets
    1281
  - Synchronous Modes
    1282
  - Frame Sync Configuration
    1282
  - Data FIFO
    1283
  - Word Mask Register
    1286
  - Interrupts and DMA Requests
    1286
- Introduction
  1289
  - Features
    1289
  - Modes of Operation
    1289
Chapter 49 General-Purpose Input/Output (GPIO)

1290
- GPIO Signal Descriptions
  1290
- Memory Map and Register Definition
  1291
- Functional Description
  1296
  - General-Purpose Input
    1296
  - General-Purpose Output
    1296
Chapter 50 JTAG Controller (JTAGC)

1299
- Introduction
  1299
  - Block Diagram
    1299
  - Features
    1300
  - Modes of Operation
    1300
- External Signal Description
  1302
  - TCK-Test Clock Input
    1302
  - TDI-Test Data Input
    1302
  - TDO-Test Data Output
    1302
  - TMS-Test Mode Select
    1302
- Register Description
  1303
  - Instruction Register
    1303
  - Bypass Register
    1303
  - Device Identification Register
    1303
  - Boundary Scan Register
    1304
- Functional Description
  1305
  - JTAGC Reset Configuration
    1305
  - IEEE 1149.1-2001 (JTAG) Test Access Port
    1305
  - TAP Controller State Machine
    1305
  - JTAGC Block Instructions
    1307
  - Boundary Scan
    1310
- Initialization/Application Information
  1310

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Motherboard Computer Hardware Microcontrollers Control Unit Controller

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Freescale Semiconductor MK22FN256VLH12 Manuals

Freescale Semiconductor MK22FN256VLH12 Reference Manual (1313 pages)

Table of Contents

Chapter 1 About this Document

Chapter 2 Introduction

Chapter 3 Chip Configuration

Chapter 4 Memory Map

Chapter 5 Clock Distribution

Chapter 6 Reset and Boot

Chapter 7 Power Management

Chapter 8 Security

Chapter 9 Debug

Chapter 10 Signal Multiplexing and Signal Descriptions

Chapter 11 Port Control and Interrupts (PORT)

Chapter 12 System Integration Module (SIM)

Chapter 13 Kinetis Flashloader

Chapter 14 Reset Control Module (RCM)

Chapter 15 System Mode Controller (SMC)

Chapter 16 Power Management Controller (PMC)

Chapter 17 Low-Leakage Wakeup Unit (LLWU)

Chapter 18 Miscellaneous Control Module (MCM)

Chapter 19 Crossbar Switch Lite (AXBS-Lite)

Chapter 20 Peripheral Bridge (AIPS-Lite)

Chapter 21 Direct Memory Access Multiplexer (DMAMUX)

Chapter 22 Enhanced Direct Memory Access (Edma)

Chapter 23 External Watchdog Monitor (EWM)

Chapter 24 Watchdog Timer (WDOG)

Chapter 25 Multipurpose Clock Generator (MCG)

Chapter 26 Oscillator (OSC)

Chapter 27 RTC Oscillator (OSC32K)

Chapter 28 Flash Memory Controller (FMC)

Chapter 29 Flash Memory Module (FTFA)

Chapter 30

Chapter 31 Cyclic Redundancy Check (CRC)

Chapter 32 Random Number Generator Accelerator (RNGA)

Chapter 33 Analog-To-Digital Converter (ADC)

Chapter 34 Comparator (CMP)

Chapter 35 12-Bit Digital-To-Analog Converter (DAC)

Chapter 36 Voltage Reference (VREFV1)

Chapter 37 Programmable Delay Block (PDB)

Chapter 38 Flextimer Module (FTM)

Chapter 39 Periodic Interrupt Timer (PIT)

Chapter 40 Low-Power Timer (LPTMR)

Chapter 41 Real Time Clock (RTC)

Chapter 42 Universal Serial Bus Full Speed OTG Controller (USBFSOTG)

Chapter 43 Serial Peripheral Interface (SPI)

Chapter 45 Inter-Integrated Circuit (I2C)

Chapter 47 Low Power Universal Asynchronous Receiver/Transmitter (LPUART)

Chapter 48 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI)

Chapter 49 General-Purpose Input/Output (GPIO)

Chapter 50 JTAG Controller (JTAGC)

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