Ca-31 Board - Sony DSC-D700 Service Manual

4-3. CA-31 BOARD

The CA-31 board consists of the following.
. CCD and CCD's peripheral circuits
IC204 CX205AK
IC201 CXD2460R
. Analog sample-and-hold circuit and gain amplifier circuit
IC205 CXA2096N
IC206 MB88347LPFV : D/A converter
. Digital 10-bit A/D converter and camera display
IC202 ADS933
IC203 CXD3135R
The light passed through the camera lens and prism reaches the chip surface of
IC204 (CCD) on the CA board and is converted into electric charges corresponding
to the brightness of light using a photosensor of approximately 1,500,000 pixels.
The converted charges are stored in the photosensor for the specified storage time
and then read out to the transfer block. The electric charges that were sequentially
sent to the transfer block are finally output to the output block of IC204 to produce
an output signal as CCD.
. Timing generator
IC201 (CXD2460R) generates various timing pulses required to drive CCD by
inputting the CKI signal (29.670 MHz for NTSC and 24.750 MHz for PAL) from
a system clock generator (on the FM-63 board) and the FRO and HRO signals
output from a sync signal generator (IC203 CXD3135R).
The timing pulses generated by IC201 are as follows:
CL: 910 fH clock (1/2 of CK (1820 fH))
H1 and H2: Clocks for driving the horizontal transfer block of a CCD imager
V1 to V3: Clocks for driving the vertical transfer block of a CCD imager
SUB: Charge sweep pulse for electronic shutter control
RG: Reset gate pulse
XSHP and XSHD: Sample-and-hold pulses for correlative double sampling
WEN: Write enable pulse for low-speed shutter
ADCLK: Sample-and-hold pulse for A/D converter
XCPOB: Pulse for clamping the optical black block
PBLK: Pre-blanking pulse
XRS: Camera signal sample-and-hold pulse
XCPDM: Pulse for clamping the CCD dummy bit block
4-6
: PSCCD with 1,500,000 pixels
: Timing generator for ICX205AK driving
: Camera head amplifier
: 10-bit A/D converter
: Camera signal processing display
DSC-D700 (UC,CE)