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SDDC Plus One
Single device data correction +1 (SDDC Plus One) organizes data in a single bundle
(x4/x8 DRAM). If any or all the bits become corrupted, corrections occur. The x4 con-
dition is corrected on all cases. The x8 condition is corrected only if the system is in
Lockstep Mode. The options are Disable and Enable.
ADDDC Sparing
Adaptive Double Device Data Correction (ADDDC) Sparing detects when the prede-
termined threshold for correctable errors is reached, copying the contents of the failing
DIMM to spare memory. The failing DIMM or memory rank will then be disabled. The
options are Disable and Enable.
Patrol Scrub
Patrol Scrub is a process that allows the CPU to correct correctable memory errors
detected on a memory module and send the correction to the requestor (the original
source). When this item is set to Enable, the IO hub will read and write back one cache
line every 16K cycles if there is no delay caused by internal processing. By using this
method, roughly 64 GB of memory behind the IO hub will be scrubbed every day. The
options are Disable and Enable.
Patrol Scrub Interval
This feature allows you to decide how many hours the system should wait before the
next complete patrol scrub is performed. Use the keyboard to enter a value from 0-24.
The default setting is 24.
IIO Configuration
EV DFX Features
When this feature is set to Enable, the EV_DFX Lock Bits that are located on a proces-
sor will always remain clear during electric tuning. The options are Disable and Enable.
CPU Configuration
IOU0 (II0 PCIe Br1)
This item configures the PCI-E port Bifuraction setting for a PCI-E port specified by the
user. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and Auto.
IOU1 (II0 PCIe Br2)
This item configures the PCI-E port Bifuraction setting for a PCI-E port specified by the
user. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and Auto.
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Chapter 6: BIOS
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