Systick Examples; Timers Examples - ST STEVAL-IDB007V1M SPBTLE-1S User Manual

UM2264
The SPI is configured in master mode and the SPI clock set to 100 kHz. The data is
transferred in the Motorola format with an 8-bit data frame, with clock low when inactive
(CPOL=0) and data valid on clock trailing edge (CPHA = 1).
Master DMA: SPI communication is controlled by DMA of the SPI status register content. It
involves a master board with the Master_Dma firmware code and a slave board with the
Slave_Dma firmware. The Master board has a small command line interface through UART
(USB-to-SERIAL must be connected to the PC), which you can use to read and change the
LED status of the slave board via SPI.
The SPI is configured in master mode and the SPI clock set to 100 kHz. The data is
transferred in the Motorola format with an 8-bit data frame, with clock low when inactive
(CPOL=0) and data valid on clock trailing edge (CPHA = 1).
Slave DMA: SPI communication is controlled by DMA of the SPI status register content. It
involves a master board with the Master_Dma firmware code and a slave board with the
Slave_Dma firmware. The slave board receives read and change requests for the LEDs via
SPI.
The SPI is configured in slave mode and the SPI clock set to 100 kHz. The data is
transferred in the Motorola format with an 8-bit data frame, with clock low when inactive
(CPOL=0) and data valid on clock trailing edge (CPHA = 1).
15.7

SysTick examples

Time base: The interrupt service routine toggles the user LEDs at approximately 1 s
intervals.
15.8

Timers examples

Mode 1: Timer/Counter 1 (TnCNT1) functions as the time base for the PWM timer and
counts down at the clock rate selected by the Timer/Counter 1 clock selector. When an
underflow occurs, the timer register is reloaded alternately from the TnCRA (first reload)
and TnCRB registers and count down begins from the loaded value.
Timer/Counter 2 can be used as a simple system timer, an external-event counter, or a
pulse-accumulate counter. Counter TnCNT2 counts down with the clock selected by the
Timer/Counter 2 clock selector, and can be configured to generate an interrupt upon
underflow.
MFTX1 and MFTX2 use prescaled clock as Timer/Counter 1. The IO2 pin is configured as
output, generating a signal with 250 ms positive level and 500 ms negative level via
MFTX1. The IO3 pin is configured as output, generating a signal with 50 ms positive level
and 100 ms negative level via MFTX2.
Timer/Counter 1 interrupts upon reload are enabled for MFTX1 and MFTX2; interrupt
routines toggle LED DL1 for MFTX1 and LED DL2 for MFTX2.
Mode 1a (pulse-train mode): the Timer/Counter 1 functions as PWM timer and
Timer/Counter 2 is used as a pulse counter that defines the number of pulses to be
generated.
In this example, MFTX2 is configured to generate 30 pulses with positive level of 500 ms
and negative level of 250 ms. MFTX2 uses prescaled clock as Timer/Counter 1. The IO3
pin is configured as output generating the number of pulses configured.
Interrupts TnA and TnB are enabled and toggle GPIO 8 and 10, while Interrupt TnD is
enabled and sets GPIO 7.
A software start trigger or external rising or falling edge start trigger can be selected. This
example uses a software trigger which is generated after system configuration.
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BlueNRG-1 peripheral driver examples
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