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Control and Status Registers Defined
The control and status registers occupy 8 consecutive locations. The following tables provide a functional description of the bit positions.
X = do not care
{ }= always this value
Address
Mode
Base+0
RD
WR
Base+0
Base+1
RD
Base+1
WR
Base+2
RD
Base+2
WR
RD
Base+3
Base+3
WR
Base+4
RD
Base+4
WR
Base+5
RD
Base+5
WR
Base+6
RD
Base+7
RD
Control and Status Name Definition
Field
ACCEN
MEM/IUC
P17-P14
IRQEN
INTPEND
RESTAT
RL
LL
M0-M3
SD0-SD15
LIN/PAGE
Sealevel Systems ROUTE 56.PCI
D7
D6
ACCEN
MEM/IUC
ACCEN
MEM/IUC
{0}
{0}
X
X
LIN/PAGED
{0}
LIN/PAGED
X
{0}
{0}
Software board reset
X
{0}
IRQEN
X
IRQEN
LL
RL
LL
RL
SD7
SD6
SD15
SD14
Description
1 = Host access to RAM or IUSC enabled; 0 = Host access to RAM or IUSC disabled. (0 on power-up)
1 = Enable Host access to RAM; 0 = Enable Host access to IUSC. (0 on power-up)
These bits select which of sixteen 16K RAM pages is visible at the address selected by MA18-MA14.
1 = Interrupts enabled, 0 = Interrupts disabled. (0 on power-up))
IUSC interrupt status: 1 = No interrupt pending on IUSC; 0 = Interrupt pending on IUSC.
Reset status: 1 = On-board reset inactive+e; 0 = On-board reset active.
Remote loopback
Local loopback
I/O mode select to SP505 (all 0 on power-up)
See Interface Selection table for valid interface options
Optional security feature. Unique value per customer or application. ( default value = FFFF)
1=256K linear block in high memory only, 0=16X16K pages in low or high memory, (0 on power-up)
Technical Description
D5
D4
D3
{0}
{1}
P17
X
X
P17
{0}
{0}
{0}
X
X
X
{1}
{0}
{0}
X
X
X
INTPEND
RESTAT
{1}
X
X
X
{0}
{0}
{0}
X
X
X
{0}
{0}
M3
X
X
M3
SD5
SD4
SD3
SD13
SD12
SD11
D2
D1
D0
P16
P15
P14
P16
P15
P14
{0}
{0}
{0}
X
X
X
{0}
{0}
{0}
X
X
X
{0}
{0}
{0}
X
X
X
{0}
{0}
{0}
X
X
X
M2
M1
M0
M2
M1
M0
SD2
SD1
SD0
SD10
SD9
SD8
Page 4
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