Technical Description; Features; Internal Baud Rate Generator; Control And Status Registers Definition - SeaLevel ACB-MP.PCI User Manual

Table of Contents

Advertisement

The ACB-MP.PCI utilizes the Zilog 85230 Enhanced Serial Communications Controller (ESCC). This chip
features programmable baud rate, data format and interrupt control. Refer to the ESCC Users Manual for details on
programming the 85230 ESCC chip.

Features

One channel of synchronous or asynchronous communications using the Zilog Z85230 chip
Programmable electrical interface selection EIA/TIA-232/530/530A/485 and ITU V.35
Programmable options for Transmit clock as input or output
Software programmable baud rate

Internal Baud Rate Generator

The baud rate of the ESCC is programmed under software control. The standard oscillator supplied with the board
is 7.3728 MHz. However, other oscillator values can be substituted to achieve different baud rates.

Control and Status Registers Definition

The control and status registers occupy 16 consecutive I/O locations. The following tables provide a functional
description of the bit positions. X = do not care
Base
Mode
D7
RD
0
+4
WR
X
+4
RD
485CLK
+5
WR
485CLK
+5
RD
0
+6
WR
X
+6
RD
SD7
+14
RD
SD15
+15
Field
IRQST
SCC interrupt status:
DSRA
DSRA:
LLA
Local Loopback:
RLA
Remote Loopback:
TSETSLA
TSET clock source:
RXCOPTA
RXCOPTA:
SYNCA_RTS
SYNCA _RTS:
SYNCA_CTS
SYNCA_CTS:
485CLK
TSET switches with TXD
ECHOA
ECHO enable:
AM0-AM3
I/O mode select.
SD0-SD15
Optional security feature. Unique value per customer or application.
Note: Default values are listed in bold
Sealevel Systems ACB-MP.PCI

Technical Description

D6
D5
IRQST
0
X
X
ECHOA
SYNCA_RTS
ECHOA
SYNCA_RTS
0
0
X
X
SD6
SD5
SD14
SD13
1 = No interrupt pending on ESCC 0 = Interrupt pending on ESCC.
1 = DSRA not active
1 = LL set
1 = RL set
1= Received TXC as source
1= Selects SCC PCLK for RTXCA
1 = SYNCA connected to RTS
1 = SYNCA connected to CTS
1 = clk switches
1 = echo disabled
See table for valid interface options
D4
D3
0
0
0
X
SYNCA_CTS
AM3
AM2
SYNCA_CTS
AM3
AM2
0
RLA
LLA
X
RLA
LLA
SD4
SD3
SD2
SD12
SD11
SD10
Description
0 = DSRA active
0 = LL not set
0 = RL not set
0 = TRXCA as source
0 = Selects received RXC for
0 = SYNCA is high
0 = SYNCA is high
0 = no CLK switching
0 = echo enabled
0 = High Impedance
Technical Description
D2
D1
D0
0
0
DSRA
X
X
X
AM1
AM0
AM1
AM0
TSETSLA
RXCOPTA
TSETSLA
RXCOPTA
SD1
SD0
SD9
SD8
RTXCA
Default value = FFFF
Page 3

Advertisement

Table of Contents
loading

Table of Contents