Fluke PM3082 Service Manual page 64

UNIT DESCRIPTIONS
5.1.1.5 Main and delayed time base triggering
Diagram 12
The main time base triggering (MTR) is mainly formed by IC D6541. The other IC D6621 is the peak-
peak detector for the trigger level. The balanced input signal for triggering on vertical channels 1,2,
3 or 4 is applied to pin 7 and 8. This signal can originate from one of the 4 vertical preamplifier
sections where the source selection is also done. The dc biasing currents come from the circuit with
V6506, V6507 and V6532. This circuit is also supplied with the line trigger sinewave signal MTRLINE
that comes from the power supply. This signal can be used for mains/line triggering and is selected
on the next diagram.
The output signal of D6541 is available at pin 19 and 20. This signal is routed to the main time base
(MTB) via the level shifters V6573 and V6574. The signal MTRVIDEO from output pin 2 of D6541 is
routed to the TV trigger circuit.
The IC D6541 incorporates the filters for HF reject (external capacitor C6549), LF reject (external
capacitor C6551) and AC (external capacitors C6559, C6561, C6562). These filter modes are
switched with the control signals MTRLF-HD (pin 3) and MTRHF-HD (pin 14). Positive/negative slope
and video are switched with the control signals MTRSLOPE (pin 21) and MTRTVSEL-HD (pin 4). The
logic levels of these control signals are indicated in two tables on the diagram. The signal MTRSEN
is a DAC output voltage that determines the gain of the trigger amplifier.
A balanced current signal leaves D6541 at pins 26 and 27. This signal is converted into a voltage
signal via V6604 and V6606. The voltage signal is applied to pins 3 and 7 of the peak-peak detector
D6621. This IC detects the positive and negative peak values of the trigger signal. It reduces in the
peak-peak trigger mode (switched with MTRPPLEV-HD) the range of the level (LEVMTB) to just
within the peak-peak signal value.
The output of the peak-peak detector is present at pin 14 and 15 and routed to level input pin 22 and
23 of D6541, via the level shifter with V6667, V6668, V6686 and V6687. At this point a level offset
correction is also introduced via DAC signal MTRBAL. The level is fixed in TV trigger mode by giving
signal LEVMTB a predefined fixed level. The output pulse MTRTVSYNC from the TV synchronization
separator circuit (see next diagram) is applied to the base of V6687. This signal is interrupted if the
TV trigger mode is off.
The series parallel converter D9011 has outputs that control a number of on/off functions in the MTB
triggering. D9011 is controlled by the microprocessor on unit A3. This happens via the data signal
SDA (Serial DAta) and the synchronization signal SCL (Serial CLock). The enable signal is
STROBE1-HT.
Diagram 13
This diagram shows the TV trigger circuit. The signal MTRVIDEO from pin 2 of MTR circuit D6541 is
applied to the input of the TV CLAMP circuit V6754/V6757/V6759/V6763A/6768. The peak level of
the synchronization pulses is detected via V6757 and C6758. The TV signal at the base of V6768 is
kept at a constant level via V6759 and V6754. Diode V6761 cuts off the video information so that only
synchronization pulses are applied to input pin 2 of N6771.
The TV synchronization separator N6771 is able to decode three different types of sync pulses. The
analog control signal MTRTVMODE at pin 6 can have 3 different values that determine the TV
standard in which the circuit will work. The standards and respective control voltages are indicated in
a table.
N6771 separates the TV synchronization pulses. The following signals are available at its outputs:
- Pin 1 carries negative going line (MTRTVL) pulses. These pulses can be applied to the MTB
trigger (MTR) section via multiplexer D6781. Via multiplexer D7711/3,4,5,9 they are applied to the
delayed trigger (DTR) section.
- Pin 3 carries the negative going field pulses (MTRTVFR) that appear at the beginning of field 1
and field 2.
5.1 -9