Fluke PM3082 Service Manual page 60

UNIT DESCRIPTIONS
The amplifier D1201 can be switched to a number of attenuation/gain positions that are dependent
on the channel 1 AMPL position. The gain x1 position is determined by R1205/R1206/C1205 that are
present across pin 6 and 7. The x1 is switched by control signal PA1X1.
The attenuation /2 is determined by R1207 and switched by PA1/2.
The gain x5 is determined by R1208/R1210/R1215/C1210 and switched by PA1X5. Continuous gain
control is determined by DAC output signal VAR1 that is applied to pin 20. This signal comes from
microprocessor unit A3. It is used for front panel gain control in fine steps and also for gain calibration.
The complete range of the channel 1 input sensitivities is controlled via front panel control AMPL. It
is accomplished by the combination of input attenuator positions and the x1, 12, x5 and the VAR1
functions.
Offset control is achieved via the DAC output signal PA1 OFFSET that is applied to the D1201 input
pin 13. The DAC signal PAIOFFSTRG gives an offset signal in the current sources V1208 (PA1LSA)
and V1209 (PA1LSB). PA1LSA and PA1LSB are applied to level shifters V1201A/1202. This is used
to compensate for offset in the trigger path and also influences the offset in the vertical channel. This
in turn is compensated via the POS1 signal in the Y-functions section.
The circuit in the bottom half of the diagram includes a number of current sources for the channel 1
and 2 preamplifiers. The reference for all these current sources is PAVREF that is present at
N1251/pin 3. This is converted in a reference voltage at the collector of V1252 that is applied to the
current sources. The currents for channel 1 are PA1ICL, PA1ISY, PA1LSA and PA1LSB. The currents
for channel 2 are PA2ICL, PA2ISY, PA2LSA and PA2LSB. PA2LSA and PA2LSB are adjustable via
DAC output signal PA20FFSTRG.
5.1.1.4 Y functions and delay line driver
Diagram 8
This diagram shows the channel 1,2, 3 and 4 function circuits D1301, D2301, D3301 and D4301.
The balanced output signals of each cicuit are available at pin 7 and 8. They are all applied to the
resistance network R1313 through R4314 that is shown on the next diagram. The output of this
network feeds the delay line driver.
The four function circuits are almost identical. Compared with channel 1 and 3, channels 2 and 4 have
additional invert functions. For this reason, only the channel 2 circuit is explained. Here the balanced
input signal is applied to pin 25 and 26 of D2301. The balanced output signal at pin 7 and 8 is switched
by control signal CNT2CH-HX. The balanced output signals FNC2MTR0 and FNC2MTR1 that are
available at pin 13 and 14 are used for triggering the main time base. This is switched via control
signal CNT2MT-HT. The balanced output signals FNC2DTR0 and FNC2DTR1 that are available at
pin 1 and 2 are used for triggering the delayed time base. This is switched via control signal
CNT2DT-HT.
Channel 2 position control is achieved via an adjustable analog DAC voltage POS2 from the
microprocessor unit A3. This voltage is applied to input 9 of operational amplifier N2202. This IC
converts the DAC voltage POS2 (1 ... 4 V) into a voltage between -8 and +8 V. This voltage is
converted into a current via resistor R2311, because pin 12 of D2301 is a virtual ground.
The balanced output signals FNCYOPO and FNCYOP1 at pin 5 and 6 of D2301 of the channel 1 can
be used to provide signals for the Y-out option. The (optional) Y-out circuit (present in channel 1 only)
is located on an additional unit that is connected via the connectors X1303 through X1310. This is
switched via control signal YOP-HX at pin 4. If no option installed, the signal is switched off by a low
level supplied via R1312. If the option is present the switching is achieved by a signal coming from
the additional unit.
5.1 -5