Rabbit RabbitCore User Manual page 87

C-programmable core module with ethernet, serial flash
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Figure A-4 shows a typical timing diagram for the Rabbit 3000 microprocessor external I/O
read and write cycles.
CLK
A[15:0]
/CSx
/IOCSx
/IORD
/BUFEN
D[7:0]
CLK
A[15:0]
/CSx
/IOCSx
/IOWR
/BUFEN
D[7:0]
Figure A-4. I/O Read and Write Cycles—No Extra Wait States
NOTE: /IOCSx can be programmed to be active low (default) or active high.
User's Manual
Tw
T1
valid
T adr
T CSx
T IOCSx
T IORD
T BUFEN
Tw
T1
valid
T adr
T CSx
T IOCSx
T IOWR
T BUFEN
T DHZV
T2
T CSx
T IOCSx
T IORD
T BUFEN
T setup
valid
T hold
T2
T CSx
T IOCSx
T IOWR
T BUFEN
valid
T DVHZ
81

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