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Instruction
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The Processor and the Operating System
45
Description
Mantissa right-shift on Ar2. The number of digits to be shifted
is specified in the lower four bits (0-3) of the B register. The
shift is accomplished in three stages -
1. The digit in bits (0-3) of the A register is right-shifted into
the first digit of the mantissa, with the twelfth digit being
lost. This is the first shift.
2. The mantissa digits are then right-shifted for the remaining
number of digits specified. The twelfth digit, except for the
last shift, is lost on each shift, and the vacated digits are
zero-filled.
3. Finally, the last right-shift takes place, with the twelfth digit
shifting into the A register. The Decimal Carry flag in the
processor is cleared along with the upper 12 bits of the A
register (4-15).
Mantissa left-shift on Ar2 for one digit. This is a circular
~hift,
with the digit in bits (0-3) of the A register forming a thir-
teenth digit. The non-digit part o( the A register is cleared
(Le., bits 4-15), and the Decimal Carry flag in the processor is
cleared.
Mantissa right-shift ()n Ar1 for one digit. The twelfth digit is
shifted into the A register (bits 0-3). The non-digit part of the
A register is cleared (Le., bits 4-15), and the Decimal Carry
flag in the processor is cleared. The first digit in the mantissa
is set to O.
Normalizes the Ar2 mantissa. The mantissa digits are left-
shifted until the first digit of the mantissa is non-zero, or until
twelve shifts have taken place, whichever comes first.
If
the
original first digit is already non-zero, no shifts occur. The
number of shifts required is stored as the first four bits (0-3) of
the B register.
If
twelve shifts were required, the Decimal
Carry flag in the processor is set, otherwise it is cleared.
Ten's complement of Ar1. The mantissa of Ar1 is replaced
with its ten's complement and Decimal Carry is cleared.
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