HP 9835A Programming Manual page 234

35 series desktop computer assembly development rom
Table of Contents

Advertisement

212
Appendix B: Machine Instructions
Instruction
Form
Group
Description
Page
MPY
r·"1F'···
Integer Math
Binary multiply. Uses Booth's Algorithm. The
35
values of the A and B registers are multiplied to-
gether with the product placed into A and B. The
A register contains the least significant bits and
the B register contains the most significant bits
and the sign. B may contain any integer value
except - 32 768.
MRX
BCD Math
Mantissa right shift on Arlo The number of digits
44
to be shifted is specified in the lower 4 bits (0-3)
of the B register. The shift is accomplished in
three stages:
1)
Bits 0-3 of the A register are right-shifted into
D1 of the mantissa, with the twelfth digit
being lost. This is the first shift. This shift al-
ways takes place, even if B
=
o.
2)
The digits are then right-shifted for the re-
maining number of digits specified. The
twelfth digit is lost on each shift (except for
the last shift) and the vacated digits are zero-
filled.
3)
Finally, the last right-shifting takes place,
with the twelfth digit shifting into the lower 4
bits (0-3) of the A register. The Decimal
Carry bit in the processor is cleared and the
non-digit part of the A register is cleared (bits
4-15).
MRY
BCD Math
Mantissa right shift on Ar2. The number of digits
45
to be shifted is specified in the lower 4 bits (0-3)
of the B register. The shift is accomplished in
three stages:
1)
Bits 0-3 of the A register are right-shifted into
D1 of the mantissa, with the twelfth digit
being lost. This is the first shift. This shift al-
ways takes place, even if B
=
o.
2)
The digits are right-shifted for the remaining
number of digits specified. The twelfth digit
is lost on each shift (except for the last shift)
and the vacated digits are zero-filled.

Advertisement

Table of Contents
loading

Table of Contents