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Instruction
Bit Pattern
RAl n
RARn
,RBl n
RBRn
RET
RIA
RIB
RlA
RLB
RZA
RZB
SAln
SAM
SARn
SBln
SBM
SBP
SBRn
SDC
SDI
SDO
'5DS
SEC
SES
SFC
SFS
SIA
SIB
I
SLA
.SLB
I
SOC
SOS
SSC
SSS
STA
STB
SZA
i SZB
TCA
TCB
WBCr
I
WBDr
WWCr
15 14 13 12 11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
o
o
o
o
o
o
1
1
1
1
1
1
1
o
o
o
o
1
1
o
o
o
o
o
o
1
1
o
o
D/I
D/I
o
o
I
i
o
o
o
o
o
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
o
o
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
o
o
1
1
o
o
1
o
1
o
1
o
o
o
1
1
1
1
o
o
o
o
1
1
o
o
o
1
o
1
o
o
1
1
o
1
o
1
o
1
1
1
o
o
o
0 0 1
0 0 1
0 0 1
0 0 1
0 0 0
1 0 0
1 0 0
1 1 1
1 1 1
1 0 0
1 0 0
0 0 1
1 0 1
0 0 1
0 0 1
1 0 1
1 0 0
0 0 1
1 0 1
0 0 1
0 0 1
1 0 0
1 1 0
1 1 1
1 0 1
1 0 0
1 0 1
1 0 1
1
1
1
1
1
o
o
1
0
0
l-oE-_.-"1=-=5'----=n-=--_~___j
1
0
0
~oE-~
__
=n_-~I
___
~~
1
0
0
l-oE-...:..._--=1=5~-......!.n~_~~-l
1
0
0
oE_
n-l
~
o
oE_
-+
1
oE_
-+
1
oE-
-+
H/H
cis
oE_
skip
-+
HIt{
Cis
oE_
o
0
oE_
o
0 L. , . . . . ; . . o E- _ _ -..--______ -+___j
1
0 ...--=O_-'O"--'_oE- __
......:n:...:...-~I
__ -+ _
__l
HIt{
Cis
oE_
skip
_+
o
1
L-...;.O·--OO--.I-:---=---n-_-l----+~
1
0
O~---=,--L.-.
- ' - . . . . - - - - - _ _ . ___ -+----j
H/p,
cIs
~oE_
_+
skip
H/R
CIs
oE_
_+
o
1
L-..-C-O===O==I=oE_====n=-==I===~=:
1
1 ~~ ______ . ___ Sk~iP
_______
~~
o
0 0 0
1
0 0 0
o
0
0
.-.:O~--.::O~....:::O~_..::::.O_.:::::.-0-l
1
1
I
oE_
H/R
cIs
oE_
HIt{
CIs
oE_
1
0
oE_
1
0
oE_
o
1
oE_
o
1
oE_
skip
1
1
0
HIt{
CIs
oE_
1
1
0
HIt{
cis
oE_
1
1
0
HIt{
cIs
oE_
1
1
1
HIp.
CIs
I
oE_
1
0
1
1
0 l,oE_
1
0
0
1
0
oE_
B/C
' !
oE_..::..-.-.-..:;-~-..:...-.'---.-----
B/C
~
address
1
0---1--0--0-'-1
~
~
,I
I _
skip
.
1
0
1
0
0
~
_ _ _ _ _ _ _ _
._~
:
o
0
0
0
0
1
0
0
0
0
OIl
g g
~
1%
~ ~ ~
g
I
~
0
~
i
' I
I
o
0
1
I/o
1
1
1
1 I oE_
r
~
I
o
0
1
I/o
1
1
11
0
1
f:
-+
i
o
0
1
I/o
1
1
1 ..--
_+
I
o
1
1
0
0
0
0
loE-~-n---l-~
Timing
25-n
n+9
25-n
n+9
16
14
14
14
14
14
14
n+9
14
n+9
n+9
14
14
n+9
14
12
12
14
14
14
14
14
14
14
14
14
14
14
14
14
19
19
14
14
9
9
23
23
23
23
12n+21
l
'
WWD r
XFRn
---------------------------~----------~
Notes on bit patterns:
B/C (Base Page/Current Page)
C/S (Clear/Set)
D / I (Direct / Indirect)
H/H (Hold/Don't Hold)
1/ D (Increment/Decrement)
All are coded 0/1 respectively
skip
} if the high bit in the field is 1, the
address
field is negative (2's complement)
Notes on timings:
Appendix B: Machine Instructions
221
All timings are maximum clock times. The clock rate is 6 megahertz. Clock times may vary
up to
±
5% from the clock rate.
Any operation using register R4, R5, R6, or R7, should add 7 clock times.
Any operation using register R8, R9, RIO, Rl1, R12, R13, R14, or R15 should add 5 clock
times.
Maximum interrupt lockout time is 239.
Minimum interrupt lockout time is 2.
Maximum DMA lockout time is 10.
Minimum DMA lockout time is 2.
Interrupt execution is 36.
DMA read
=
3 + IOn + lockout time} n is the number of words
DMA write
=
3 + 9n + lockout time
transferred during a request
Note 1. B is the current value in bits 0 through 3 of the B register.
Note 2. If bits 0 through 3(B) of the B register are 0 then the total timing is 34.
Note 3. T is the total number of 0
~
1 and 1 -+ 0 transitions in the A register (using an
imaginary 0 to .the right of bit 0).
Note 4. B is the current value in bits 0 through 3 of the B register. If B
=
0, then the total timing
is 26.
Note 5. Z is the number of leading zeroes in the mantissa of Ar2. If Z
=
12, then the total timing
is 69.
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