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Appendix B: Machine Instructions
Instruction
Form
Group
Description
Page
AND
{loc} [, 1]
Logical
Logical "and" operation. The contents of the A
41
register are compared, bit by bit, with the contents
of the specified location. For each bit comparison
a 1 results if both bits are 1 's, a
a
results otherwise.
The 16-bit result is left in A. Specifying register
R4, R5, R6, or R7 causes an input bus cycle to the
interface addressed by the Pa register. Indirect
addreSSing may be specified. {loc} must be on
base or current page.
CBL
Stack
Clears the Cb register. Specifies the lower block of
43
memory for byte-referencing stack instructions.
CBU
Stack
Sets the Cb register. Specifies the upper block of
43
memory for byte-referencing stack instructons.
CDC
BCD Math
Clears Decimal Carry explicitly.
CLA
Shift
Clears register A. This is exactly equivalent to SAR
41
16.
CLB
Shift
Clears register B. This is exactly equivalent to SBR
41
16.
CLR
{n}
Load/Store
Clears the specified number of words, beginning
34
at the location pOinted at by the A register. A
maximum of 16 words may be cleared.
CMA
Memory
Perform a one's complement of the A register (bit
41
by bit inversion of all 16 bits).
CMB
Memory
Perform a one's complement of the B register (bit
41
by bit inversion of all 16 bits).
CMX
BCD Math
Ten's complement of Arl. The mantissa of Arl is
45
replaced with its ten's complement and Decimal
Carry is cleared.
CMY
BCD Math
Ten's complement of Ar2. The mantissa of Ar2 is
46
replaced with its ten's complement and Decimal
Carry is cleared.
CPA
{loc} [
]
Test/Branch
Compares the contents of register A with the con-
37
tents of the specified location and skips if they are
unequal. Indirect addreSSing may be specified.
Specifying register R4, R5, R6, or R7 causes an
input bus cycle to the interface addressed by the
Pa register. {loc} must be on base or current page.
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