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I/O Handling
135
The 9835A/B sees the registers as single-words and always sends or receives a full word of
data when it references one of them. If a particular interface utilizes less than the ftill sixteen bits
(when exchanging 8-bit extended ASCII data bytes, for example), then the most significant bits
(8 through 15) are received as zeroes. On output, if fewer than 16 bits are utilized by the
interface, it ignores the most significant bits. The value of these bits, in this case, is a "don't
care" (Le., may be any pattern of ones or zeroes).
All of the HP 98030 series of interface cards use the registers as follows -
Register
On Input
On Output
R4
Primary Data In
Primary Data Out
R5
Primary Status In
Primary Status Out
R6
Secondary Data In
Secondary Data Out
R7
Secondary Status In
Secondary Status Out
The R4 register, then, is almost always used for data transfers. R5 is always used for status and
control information. The "secondary" registers - R6 and R7 - perform the indicated
functions only nominally. The exact interpretation as to how the register is used depends upon
the interface card being used (see the Interfacing Concepts manual for details).
In order to give some specific examples for using the registers, the '98032 16-Bit Parallel
Interface (sometimes called General Purpose Input/Output - GPIO) is used. This card
defines the secondary registers as
Register
On Input
R6
High-Byte Data In
R7
(unused)
Select Codes
On Output
High-Byte Data Out
Trigger
As mentioned earlier, more than one interface card may be connected to the 9835A/B. It
becomes necessary, then, that there be a mechanism whereby a particular interface can be
chosen to respond when an I/O register is referenced for either input or output. This
mechanism is the Peripheral Address Register (Pa).
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