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Instruction
Form
CPB
DBL
DBU
DDR
DIR
DMA
DRS
DSZ
{loc} [ T]
EIR
Appendix B: Machine Instructions
209
Group
Test/Branch
Stack
Stack
I/O
I/O
I/O
BCD Math
Description
Compares the contents of register B with the con-
tents of the specified location and skips if they are
unequal. Indirect addressing may be specified.
Specifying register R4, R5, R6, or R7 causes an
input bus cycle to the interface addressed by the
Pa register. {loc} must be on base or current page.
{loc} must be on base or current page.
Clears the Db register. Specifies the lower block of
memory for byte-referencing stack instructions.
Sets the Db register. Specifies the upper block of
memory for byte-referencing stack instructions.
Disables Data Request. Cancels the DMA
instruction.
Disables the interrupt system. Cancels the EIR
instruction.
Enables the DMA mode. Cancels the DDR
instruction.
Mantissa right shift of Arl for one digit. The
twelfth digit is shifted into bits 0-3 of the A regis-
ter. The non-digit part of the A register is cleared
(bits 4-15), and the Decimal Carry bit in the pro-
cessor is cleared. The first digit in the mantissa is
set to O.
Test/ Alter/Branch Decrements the contents of the specified location
and skips if the new contents are O. Specifying
register R4, R5, R6, or R7 causes an input (or an
input and an output) bus cycle to the interface
addressed by the Pa register. I ndirect addressing
may be specified. {loc} must be on base or current
page.
I/O
Enables the interrupt system. Cancels the DIR in-
struction.
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