Bcd Math Group - HP 9835A Programming Manual

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The Processor and the Operating System
BCD Math Group
This group of instructions provides you with BCD arithmetic operations using the Ar1 and Ar2
registers.
In general, the instructions associate the Ar1 register with "X" and the Ar2 register with "Y" in
the mnemonic for the instruction. Both registers contain values which are considered BCD
full-precision values when operated upon by instructions in this group.
The mantissas referred to below consist of 12 BCD digits. All the shifting operations manipulate
the digits as units (i. e., 1 digit - or 4 bits - at a time). In addition, shifting operations involve
an additional digit in the A register (located in the lower 4 bits, numbered 0 through 3).
All arithmetic is performed in BCD. The values being operated upon are assumed to be nor-
malized BCD floating-point (full-precision) values. Signs and exponents are left strictly alone.
There is a flag in the processor, called Decimal Carry, which is set when an overflow occurs
during a BCD operation.
A full discussion of BCD arithmetic techniques can be found in Chapter 5.
Instruction Description
Mantissa right shift on Arl. The number of digits to be shifted
is specified in the lower 4 bits (0-3) of the B register. The shift
is accomplished in three stages -
1.
The digit in bits (0-3) of the A register is right-shifted into
the first digit of the mantissa, with the twelfth digit being
lost. This is the first shift.
2. The mantissa digits are then right-shifted for theremaining
number of digits specified. The twelfth digit, except for the
last shift, is lost on each shift and the vacated digits are
zero-filled.
3. Finally, the last right-shift takes place with the twelfth digit
shifting into the A register. The Decimal Carry flag in the
processor is cleared along with the upper 12 bits of the A
register (4-15).