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,-'--"'--~'
- ' ..
--~-
..
---~.----~' ---.---"~. ~'
_.-.-' - '
-'·'----~--~'-"--------'----~'-··'-'·'--~----r-"--~-"
: Instruction
Form
Group
Description
I
Page
i
1-
- ; - - - - ' - - - - - , - - - . - - . - - - " - - - - - - - - , - - - - ' - - -
t
1
I
3)
Finally, the last
right~shifting
takes place,
I'
MWA
NOP
NRM
PBC
C'E:C {reg} [
T]
I
I
I
PBD
I
;:::'HL {reg}
I
cr::
I
"D {reg} [ I]
I
I
i
I
,
'
1
i
BCD Math
with the twelfth digit shifting into the lower 4
bits
(0-3)
of the A register. The non-digit part
of the A register is cleared (bits 4-15), and
i
the Decimal Carry bit in the processor is
cleared.
Mantissa word addition. The contents of the B
register are added to the ninth through twelfth
digits of the Ar2 register. Decimal Carry is added
to the twelfth digit; if an overflow occurs, Deci-
mal Carry is set, otherwise Decimal Carry is
cleared.
Miscellaneous
Null operation. This is exactly eqUivalent to LOA
BCD Math
Stack
Stack
, A.
, Normalizes the Ar2 mantissa. Up to twelve left-
shifts of the mantissa are performed until the first
digit of the mantissa is non-zero. If the original
, first digit is already non-zero, no shifts occur. The
: number of shifts required is stored in the first 4
bits
(0-3)
of the B register. If 12 shifts are re-
quired, the Decimal Carry bit in the processor is
set; otherwise, the Decimal Carry bit is cleared.
The exponent is not altered.
Pushes the lower byte (right half) of the specified
register onto the stack pointed at by the Cb and C
registers. Specifying register R4, R5, R6, or R7
causes an input I/O bus cycle to the interface ad-
dressed by the Pa register. Incrementing or de-
crementing of the C register can be specified. In-
crementing is the default. {reg} must be in the
range of
a
through 7. The incrementing or decre-
menting action takes place before pushing.
, ____ ... __ --L _____
._.~
_ _ _ _ , ..
_.L....... ___ . ___ _
Pushes the lower byte (right half) of the speCified
register onto the stack pointed at by the Db and 0
registers. Specifying register R4, R5, R6, or R7
causes an input I/O bus cycle to the interface ad-
dressed by the Pa register. Incrementing or dec-
rementing the 0 register can be speCified. Incre-
menting is the default. {reg} must be in the range
of 0 through 7. The incrementing or decrementing
action takes
p!~~_,~~i<?re
pushing:.
46
47
45
43
43
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