Msub32 Mra, Mrb, Mrc - 32-Bit Integer Subtraction - Texas Instruments TMS320F28004x Technical Reference Manual

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MSUB32 MRa, MRb, MRc
Operands
MRa
MRb
MRc
Opcode
LSW: 0000 0000 00cc bbaa
MSW: 0111 1100 1110 0000
32-bit integer addition of MRb and MRc.
Description
MARa(31:0) = MARb(31:0) - MRc(31:0);
This instruction modifies the following flags in the MSTF register:
Flags
Flag
Modified
The MSTF register flags are modified as follows:
NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; }
This is a single-cycle instruction.
Pipeline
Example
; Given A = (int32)1
;
;
;
;
Calculate Y2 = A - B - C
;
_Cla1Task3:
MADD32 MRa, MRb, MRc
See also
MAND32 MRa, MRb, MRc
MASR32 MRa, #SHIFT
MLSL32 MRa, #SHIFT
MLSR32 MRa, #SHIFT
MOR32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc
SPRUI33 – November 4 2015 – Revised January 2017
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32-Bit Integer Subtraction
CLA floating-point destination register (MR0 to MR3)
CLA floating-point destination register (MR0 to MR3)
CLA floating-point destination register (MR0 to MR3)
TF ZF
No Yes
B = (int32)2
C = (int32)-7
MMOV32 MR0, @_A
MMOV32 MR1, @_B
MMOV32 MR2, @_C
MSUB32 MR3, MR0, MR1
MSUB32 MR3, MR3, MR2
MMOV32 @_y2, MR3
MSTOP
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NF
Yes
; MR0 = 1 (0x00000001)
; MR1 = 2 (0x00000002)
; MR2 = -7 (0xFFFFFFF9)
; A + B
; A + B + C = 6 (0x0000006)
; Store y2
; End of task
Instruction Set
LUF LVF
No No
Control Law Accelerator (CLA)
691