Gpbcsel2 Register - Texas Instruments TMS320F28004x Technical Reference Manual

Registers
6.7.1.1.31 GPBCSEL2 Register (Offset = 6Ah) [reset = 0h]
GPBCSEL2 is shown in
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GPIO B Master Core Select (GPIO40 to GPIO47)
Each field in this register selects the master for one IO pin. The master controls the pin in GPIO mode via
its GPBDAT, GPBSET, GPBCLEAR, and GPBTOGGLE registers.
0x0: CPU is the master
0x1: CLA is the master
0x2 - 0xF: Reserved
31 30 29 28
GPIO47
R/W-0h
15 14 13 12
GPIO43
R/W-0h
Bit Field
31-28 GPIO47
27-24 GPIO46
23-20 GPIO45
19-16 GPIO44
15-12 GPIO43
11-8 GPIO42
7-4 GPIO41
3-0 GPIO40
830
General-Purpose Input/Output (GPIO)
Figure 6-34 and described in
Table.
Figure 6-34. GPBCSEL2 Register
27 26 25
GPIO46
R/W-0h
11 10 9
GPIO42
R/W-0h
Table 6-40. GPBCSEL2 Register Field Descriptions
Type Reset
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
Copyright © 2015–2017, Texas Instruments Incorporated
Table 6-40.
24 23 22 21
GPIO45
R/W-0h
8 7 6 5
GPIO41
R/W-0h
Description
Master core select for GPIO47
Master core select for GPIO46
Master core select for GPIO45
Master core select for GPIO44
Master core select for GPIO43
Master core select for GPIO42
Master core select for GPIO41
Master core select for GPIO40
SPRUI33 – November 4 2015 – Revised January 2017
www.ti.com
20 19 18 17
GPIO44
R/W-0h
4 3 2 1
GPIO40
R/W-0h
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