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–
MSA block: it performs 16 POINTER GENERATOR functions in parallel, according to ITU and ETSI,
on an AU–4 mapping basis.
–
MST block: it is located in FPGA and performs Multiplex Section Termination Source:
•
K2 byte is also processed for RDI insertion. RDI is inserted according to sink function
consequent actions;
•
S1: Byte S1 is inserted;
•
B2: The error monitoring byte B2 is allocated in the STM–16 for a multiplex section bit
error–monitoring function. This function is a bit interleaved parity (BIP–24) code using even
parity as defined in Recommendation G.707. The BIP–24 is computed over all bits (except
those in the RSOH bytes) of the previous STM–16 frame and placed in the 3x16 respective B2
byte positions of the current STM–16 frame.
•
M1: The number of errors detected by monitoring B2 in the sink side is passed to the source
side via the aREI and is encoded in the MS–REI (byte M1) according to 9.2.2.12/G.707.
–
RST block: FPGA block implements the RST source functions listed here below.
•
B1: The error monitoring byte B1 is allocated in the STM–16 for a regenerator section bit error
monitoring function. This function is a bit interleaved parity 8 (BIP–8) code using even parity as
defined in Recommendation G.707. The BIP–8 is computed over all bits of the previous
STM–16 frame the RSn_CP after scrambling. The result is placed in byte B1 position of the
RSOH before scrambling.
•
A1, A2: Frame alignment bytes A1 and A2 (3 x 16 of each) are generated and inserted in the
first row of the RSOH.
•
Scrambling is performed according to Recommendation G.707, which excludes the first row of
the STM–16 RSOH (9x16 bytes, including the A1, A2, J0 and bytes reserved for national use
or future international standardization) from scrambling.
TX SIDE
–
RST block: FPGA block implements the RST sink functions listed here below.
•
The STM–16 frame alignment process is performed according to G.783 Recommendation.
•
After the recovery of the frame phase start the received signal is descramblered using the
generator polynomial specified in G.707 Recommendation.
•
B1 check is performed. Even bit parity is computed for each bit "n" of every byte of the preceding
scrambled STM–16 frame and compared with bit "n" of B1 recovered from the current frame
in order to detect errored blocks
–
MST block: it is located in FPGA block and the function performed are listed below;
•
B2: The 3 x 16 error monitoring B2 bytes are recovered from the MSOH. A BIP–24–16 code is
computed for the STM–16 frame. The computed BIP–24–16 value for the current frame is
compared with the recovered B2 bytes from the following frame and errors are reported .
B2 Errored Block events happened during the last second are reported in an "Alarms and
controls" block register.
B2 Errored Block is also used to calculate total number of errored blocks.
•
M1: MS–REI information is decoded according to G.707 from byte M1 and reported as a 1
second count
MS–REI Errored Block events happened during the last second are reported in an "Alarms and
controls" block register.
MS–REI indication is also used to calculate total number of remote errored block.
•
K2: MS AIS detection
ED
02
3AL 91669 AA AA
674
549
/
674
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