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140 MBIT/S PORT MANAGEMENT
(See Figure 105. on page 222)
Side B to Side A description:
a )
High Order Path layer:
•
High Order Path layer Trail Termination Function (HPT): S4_TT_Sk
•
J1:
•
G1[1–4]: The REI information is recovered.
•
G1[5]:
•
C2:
•
B3:
•
SSF detection ––> SSF alarm
•
Low Order Path layer Adaptation to PDH Section layer (LPA): S4/P4x_A_Sk or S4/P4s_A_Sk
•
C2:
•
AIS or SSF is applied if TSF or Signal label Mismatch is detected
b )
Electrical PDH Physical Section layer (PPI)
•
Adaptation to PDH section layer:E4/P4x_A_So or E4/P4s_A_So
•
It convert the internal signal code to the line code (CMI)
•
Trail Termination: E4_TT_So
•
signal conditioning for transmission medium ( e.g. electrical level, etc.).
Side A to Side B description:
a )
Electrical PDH Physical Section layer (PPI)
•
Trail Termination: E4_TT_Sk
•
Input LOS detection.
•
PDH physical Adaptation layer: E4/P4x_A_Sk or E4/P4s_A_Sk
•
timing is extracted.
•
data are decoded.
•
AIS detection and insertion.
•
LOF detection (only in case of E4/P4x_A_Sk)
b )
Low Order Path layer:
•
PDH Section layer to Low Order Path layer Adaptation (LPA): S4/P4x_A_So or S4/P4s_A_So
•
The signal label is inserted in C2
•
High Order Path layer Trail Termination Function (HPT): S4_TT_So
•
J1:
•
G1:
•
B3:
ED
02
Path Trace information is recovered ––> TIM detection.
Path Status monitoring ––>HP–RDI detection.
UNEQ detection.
VC–4 BIP–8 Errored Block Count––> Ex–BER, Signal Degrade alarm
Signal label detection in the byte C2 –> Signal label Mismatch detection.
path trace identifier is inserted.
insertion of RDI[5] and/or REI[1–4] information.
VC–4 Bip–8 calculation and insertion.
3AL 91669 AA AA
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