Alcatel 1660SM Technical Handbook page 533

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SIL: it provides to acknowledge the ethernet inter–frames silences and to discard them. In this
way the useful data only are transferred to the subsequent data buffer.
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BUFF: it is a buffer in which the ethernet data are written by means of a smooth ethernet clock,
as they are ready, and then are read by the GFP mapper. In case that the buffer is near to full
the mechanism of flow–control is started, in order to slow down the remote ethernet data source.
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GFP: it is the GFP mapper. The data are drawn from the buffer at 155Mb/s rate; possible gaps
between ethernet encapsulated frames are filled with Inter–Packet Gaps (IPG).
TABLES MEM:
this is a memory storing some tables of data relevant to: routing, delays of the queues and delays
of the links, destinations of the ethernet signals, etc.
GFP–SDH:
this is an integrated circuit that accomplishes the data passage from GFP frames to SDH frames and
viceversa. Every function contained in it is repeated 8 times, in order to process the 8 afferent signals.
Its main functions are:
NOTE: the functions are here described only in the direction from GFP to SDH, in the opposite
direction they are opposite and specular.
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LPA: it provides to map, directly, the GFP data into an SDH higher order unstructured C4
container.
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HPT: this block adds the higher order POH bytes to the C–4 payload (bulk); it accomplishes only
a reduced HPT, since the complete function is implemented on the SDH–BP macro–block.
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XC&VC: it implements the Cross–Connection (routing) and the Virtual Concatenation of the
encapsulated ethernet signals. The Virtual Concatenation consists in the distribution of the
bytes flow of a single ethernet signal, by bytes de–interleaving, over several, concatenated VC4
signals; the virtual concatenation can be done over 2 or 4 or 7 VC4's.
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MSA, MST, RST: they accomplish only reduced SDH functions for the STM1 signal, since they
are used here only for intra–board framing purposes;
ALIGNMENT BUFFER:
this is a buffer storing the data, needed in the case of virtual concatenation: since different VC4's can
have different delays, they must be memorized to be aligned; the maximum tolerable delay difference
is 250msec.
SDH–BP:
this is an integrated circuit that accomplishes the data passage from STM1 frames to VC4 frames
for the BackPanel format and viceversa. Two of these macro–blocks are located on the board, in
order to process the 8 afferent signals, since each of them can process 4 stm1 signals. Every function
contained in it is repeated 4 times.
Its main functions are:
NOTE: the functions are here described only in the direction toward the back panel, in the opposite
direction they are opposite and specular.
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RST, MST, MSA: these are standard SDH functions for the STM1 signal, their function is
reduced since they are used here only for intra–board framing purposes;
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HPT: this block adds the higher order POH bytes to the C–4 payload (bulk);
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4:1&1:4 : this is a parallel–to–serial converter, in direction towards the backpanel, and a
serial–to–parallel converter, in direction from the backpanel; the backpanel signal format is
STM4–like, at 622 Mb/s rate. The backpanel signal is split in two: the first (D1a and D2a) going
to the main MATRIX Unit and the second (D1b and D2b) to the spare MATRIX Unit
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