This document is a quick guideline to help the user perform a schematics review to achieve the best
performance. This document does not apply to the UCD9080 and UCD9081 devices.
1
Introduction
The UCD90xxx family of digital power supply sequencers, also known as system health monitors are
flexible and powerful enough to meet users sequencing, monitoring, margining and other needs. The
entire family of devices are designed to have similar behaviors, with a different number of rails or some
other minor features. Users only need to learn how to use the device once, and can then seamlessly
switch to other devices within the family that best fit their future designs. This document is a quick
guideline to help user to perform a schematics review to achieve the best performance. This document
does not apply to the UCD9080 and UCD9081 device.
2
If a brownout circuit is used, ensure that forward voltage of the selected Schottky diode does not trigger
the brownout voltage threshold under operational temperature range. The pullup source for the RESET
signal must be connected to the cathode side of the diode, if brownout circuitry is used.
2.1
UCD90240, UCD90320 and UCD90320U
The UCD90240, UCD90320 and UCD90320U devices have the following power supply parameters:
•
Pin A2, G13, M12, and N10 leave floating or isolated
•
Pin G12, K11, M10 and N13 ties to DVSS
•
K12 ties to V33D
•
Three 1-μF X7R ceramic capacitors in parallel with two 0.1-μF X7R ceramic capacitors for BPCAP
decoupling
•
Two 1-μF X7R ceramic capacitors in parallel with four 0.1-μF X7R ceramic capacitors and two 0.01-μF
X7R ceramic capacitors for V33D decoupling
•
One 1-μF X7R ceramic capacitor in parallel with one 0.1-μF X7R ceramic capacitor and one 0.01-μF
X7R ceramic capacitor for V33A decoupling. A 1-Ω resistor can be placed between V33D and V33A to
decouple the noise on V33D from V33A.
•
One 1-μF X7R ceramic capacitor in parallel with one 0.01-μF X7R ceramic capacitor for VREFA+
decoupling (if used)
•
Place decoupling capacitors as close to the device as possible
•
If an application does not use the RESET signal, the RESET pin must be tied to V33D, either by direct
connection to the nearest V33D pin, or by an R-C circuit as shown in
V33D
10 kW
1 nF
Figure 1. RESET With R-C Network
SLVUB50C – June 2017 – Revised March 2019
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UCD90xxx Sequencer Schematics Guidelines
UCD90320
RESET
Copyright © 2017–2019, Texas Instruments Incorporated
SLVUB50C – June 2017 – Revised March 2019
Figure
1.
Analog Input
UCD90320
200 W
AMONx
Figure 2. Example of Analog Inputs
UCD90xxx Sequencer Schematics Guidelines
User's Guide
1
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