NXP Semiconductors LPC1767 Manuals

Manuals and User Guides for NXP Semiconductors LPC1767. We have 1 NXP Semiconductors LPC1767 manual available for free PDF download: User Manual

NXP Semiconductors LPC1767 User Manual (841 pages)

ARM, ARM Cortex-M3, 32-bit, USB, Ethernet, CAN, I2S, Microcontroller

Brand: NXP Semiconductors | Category: Microcontrollers | Size: 3 MB

Chapter 1: Lpc176X/5X Introductory Information

4
Introduction

4
Features

5
Applications

7
Ordering Information

8
- Part Options Summary
  8
Simplified Block Diagram

9
Chapter 35 : Supplementary Information

10
Architectural Overview

10
ARM Cortex-M3 Processor

10
- Cortex-M3 Configuration Options
  10
  - System Options
    10
  - Debug Related Options
    11
On-Chip Flash Memory System

11
On-Chip Static RAM

11
Block Diagram

12
Chapter 2: Lpc176X/5X Memory Map

13
Memory Map and Peripheral Addressing

13
Memory Maps

13
APB Peripheral Addresses

15
Memory Re-Mapping

16
- Boot ROM Re-Mapping
  16
AHB Arbitration

16
Bus Fault Exceptions

16
Chapter 3: Lpc176X/5X System Control

18
Introduction

18
Pin Description

18
Register Description

19
Reset

19
- Reset Source Identification Register (RSID - 0X400F C180)
  22
Brown-Out Detection

23
External Interrupt Inputs

24
- Register Description
  25
  - 0X400F C140
    25
  - 0X400F C148)
    26
  - 0X400F C14C)
    27
Other System Controls and Status Flags

29
- System Controls and Status Register (SCS - 0X400F C1A0)
  29
Chapter 4: Lpc176X/5X Clocking and Power Control

30
Summary of Clocking and Power Control Functions

30
Register Description

31
Oscillators

32
- Internal RC Oscillator
  32
- Main Oscillator
  32
- RTC Oscillator
  34
Clock Source Selection Multiplexer

35
- Clock Source Select Register (CLKSRCSEL - 0X400F C10C)
  35
PLL0 (Phase Locked Loop 0)

36
- PLL0 Operation
  36
- PLL0 and Startup/Boot Code Interaction
  36
- PLL0 Register Description
  37
- PLL0 Control Register (PLL0CON - 0X400F C080)
  37
- PLL0 Configuration Register (PLL0CFG - 0X400F C084)
  38
- PLL0 Status Register (PLL0STAT - 0X400F C088)
  39
- PLL0 Interrupt: PLOCK0
  40
- PLL0 Modes
  40
- PLL0 Feed Register (PLL0FEED - 0X400F C08C)
  41
- PLL0 and Power-Down Mode
  41
- PLL0 Frequency Calculation
  41
- Procedure for Determining PLL0 Settings
  43
- Examples of PLL0 Settings
  44
  - Example 1
    44
  - Example 2
    44
  - Example 3
    45
- PLL0 Setup Sequence
  47
PLL1 (Phase Locked Loop 1)

48
- PLL1 Register Description
  48
- PLL1 Control Register
  48
  - C0A0)
    49
- PLL1 Configuration Register (PLL1CFG - 0X400F C0A4)
  50
- PLL1 Status Register (PLL1STAT - 0X400F C0A8)
  50
- PLL1 Modes
  51
- PLL1 Interrupt: PLOCK1
  51
- PLL1 Feed Register
  52
  - C0Ac)
    52
- PLL1 and Power-Down Mode
  52
- PLL1 Frequency Calculation
  53
- Procedure for Determining PLL1 Settings
  53
Clock Dividers

55
Power Control

59
- Sleep Mode
  59
  - Deep Sleep Mode
    59
- Power-Down Mode
  60
- Deep Power-Down Mode
  61
- Peripheral Power Control
  61
- Register Description
  61
- Power Mode Control Register (PCON - 0X400F C0C0)
  62
- Encoding of Reduced Power Modes
  63
  - Wake-Up from Reduced Power Modes
    63
- Power Control for Peripherals Register (PCONP - 0X400F C0C4)
  63
- Power Control Usage Notes
  65
- Power Domains
  65
Wake-Up Timer

66
External Clock Output Pin

67
- Clock Output Configuration Register
  67
Chapter 5: Lpc176X/5X Flash Accelerator

69
Introduction

69
Flash Accelerator Blocks

69
- Flash Memory Bank
  69
- Flash Programming Issues
  70
Register Description

70
Flash Accelerator Configuration Register

71
Operation

71
Chapter 6: Lpc176X/5X Nested Vectored Interrupt Controller (NVIC)

73
Features

73
Description

73
Interrupt Sources

73
Vector Table Remapping

76
- Examples
  76
Register Description

77
Chapter 7: Lpc176X/5X Pin Configuration

92
Lpc176X/5X Pin Configuration

92
Lpc176X/5X Pin Description

95
Chapter 8: Lpc176X/5X Pin Connect Block

105
How to Read this Chapter

105
Description

105
Pin Function Select Register Values

105
- Multiple Connections
  106
Pin Mode Select Register Values

106
- Function of PINMODE in Open Drain Mode
  107
Register Description

108
Chapter 9 : Lpc176X/5X General Purpose Input/Output (GPIO)

121
Basic Configuration

121
Features

121
- Digital I/O Ports
  121
- Interrupt Generating Digital Ports
  121
Applications

122
Pin Description

122
Register Description

123
GPIO Usage Notes

141
- Example: an Instantaneous Output of 0S and 1S on a GPIO Port
  141
- Writing to FIOSET/FIOCLR Vs. FIOPIN
  141
Chapter 10: Lpc176X/5X Ethernet

142
Basic Configuration

142
Introduction

142
Features

143
Architecture and Operation

144
DMA Engine Functions

145
Overview of DMA Operation

145
Ethernet Packet

146
Overview

147
- Partitioning
  147
- Example PHY Devices
  148
Pin Description

148
Registers and Software Interface

149
- Register Map
  149
Ethernet MAC Register Definitions

151
- MAC Configuration Register 1 (MAC1 - 0X5000 0000)
  151
- MAC Configuration Register 2 (MAC2 - 0X5000 0004)
  151
- Back-To-Back Inter-Packet-Gap Register (IPGT - 0X5000 0008)
  153
- Non Back-To-Back Inter-Packet-Gap Register (IPGR - 0X5000 000C)
  153
- Collision Window / Retry Register (CLRT - 0X5000 0010)
  154
- Maximum Frame Register (MAXF - 0X5000 0014)
  154
- PHY Support Register (SUPP - 0X5000 0018)
  154
- Test Register (TEST - 0X5000 001C)
  154
- MII Mgmt Configuration Register (MCFG - 0X5000 0020)
  155
- MII Mgmt Command Register
  156
  - 0X5000 0024)
    156
- MII Mgmt Address Register
  156
  - 0X5000 0028)
    156
- MII Mgmt Write Data Register
  156
  - 0X5000 002C)
    156
- MII Mgmt Read Data Register
  157
  - 0X5000 0030)
    157
- MII Mgmt Indicators Register
  157
- 0X5000 0034)
  157
  - Station Address 0 Register
    158
- Station Address 1 Register
  158
- Station Address 2 Register
  158
Control Register Definitions

159
Receive Filter Register Definitions

167
Module Control Register Definitions

169
- Interrupt Status Register
  169
  - 0X5000 0FE0)
    169
- Interrupt Enable Register
  170
  - 0X5000 0FE4)
    170
  - 0Fe8)
    170
- Interrupt Set Register (Intset - 0X5000 0FEC)
  171
- Power-Down Register
  172
  - 0X5000 0FF4)
    172
Descriptor and Status Formats

173
- Receive Descriptors and Statuses
  173
- Transmit Descriptors and Statuses
  176
Ethernet Block Functional Description

178
- Overview
  178
- AHB Interface
  179
Interrupts

179
- Direct Memory Access (DMA)
  179
- Initialization
  182
- Transmit Process
  183
- Receive Process
  189
- Transmission Retry
  195
- Status Hash CRC Calculations
  195
- Duplex Modes
  196
- IEE 802.3/Clause 31 Flow Control
  196
- Half-Duplex Mode Backpressure
  198
- Receive Filtering
  199
- Power Management
  201
- Wake-Up on LAN
  201
- Enabling and Disabling Receive and Transmit
  203
- Transmission Padding and CRC
  205
- Huge Frames and Frame Length Checking
  206
- Statistics Counters
  206
- MAC Status Vectors
  206
- Reset
  207
- Ethernet Errors
  208
AHB Bandwidth

209
- DMA Access
  209
- Types of CPU Access
  210
- Overall Bandwidth
  210
CRC Calculation

212
Chapter 11 : Lpc176X/5X USB Device Controller

214
How to Read this Chapter

214
Basic Configuration

214
Introduction

214
Features

215
Fixed Endpoint Configuration

215
Functional Description

216
- Analog Transceiver
  217
- Serial Interface Engine (SIE)
  217
- Endpoint RAM (EP_RAM)
  217
- EP_RAM Access Control
  217
- DMA Engine and Bus Master Interface
  218
- Register Interface
  218
- Softconnect
  218
- Goodlink
  218
Operational Overview

218
Pin Description

219
Clocking and Power Management

219
- Power Requirements
  219
- Clocks
  219
- Power Management Support
  220
- Remote Wake-Up
  221
Register Description

221
Interrupt Handling

242
- Slave Mode
  243
- DMA Mode
  243
Serial Interface Engine Command Description

245
USB Device Controller Initialization

253
Slave Mode Operation

254
- Interrupt Generation
  254
- Data Transfer for out Endpoints
  255
- Data Transfer for in Endpoints
  255
DMA Operation

255
- Transfer Terminology
  256
- USB Device Communication Area
  256
- Triggering the DMA Engine
  257
- The DMA Descriptor
  257
- Next_Dd_Pointer
  258
- Dma_Mode
  258
- Next_Dd_Valid
  258
- Isochronous_Endpoint
  259
- Max_Packet_Size
  259
- Dma_Buffer_Length
  259
- Dma_Buffer_Start_Addr
  259
- Dd_Retired
  259
- Dd_Status
  259
- Packet_Valid
  260
- Ls_Byte_Extracted
  260
- Ms_Byte_Extracted
  260
- Present_Dma_Count
  260
- Message_Length_Position
  260
- Isochronous_Packetsize_Memory_Address
  260
- Non-Isochronous Endpoint Operation
  260
- Setting up DMA Transfers
  260
- Finding DMA Descriptor
  261
- Transferring the Data
  261
- Optimizing Descriptor Fetch
  261
- Ending the Packet Transfer
  261
- No_Packet DD
  262
- Isochronous Endpoint Operation
  262
- Setting up DMA Transfers
  262
- Finding the DMA Descriptor
  262
- Transferring the Data
  263
  - OUT Endpoints
    263
  - IN Endpoints
    263
- DMA Descriptor Completion
  263
- Isochronous out Endpoint Operation
  263
  - Example
    263
- Auto Length Transfer Extraction (ATLE) Mode Operation
  264
  - OUT Transfers in ATLE Mode
    265
  - IN Transfers in ATLE Mode
    266
- Setting up the DMA Transfer
  266
- Finding the DMA Descriptor
  266
- Transferring the Data
  266
  - OUT Endpoints
    266
  - IN Endpoints
    266
- Ending the Packet Transfer
  267
  - OUT Endpoints
    267
  - IN Endpoints
    267
Double Buffered Endpoint Operation

267
- Bulk Endpoints
  267
- Isochronous Endpoints
  269
Chapter 12 : Lpc176X/5X USB Host Controller

270
How to Read this Chapter

270
Basic Configuration

270
Introduction

270
- Features
  271
- Architecture
  271
Interfaces

271
- Pin Description
  272
- USB Host Usage Note
  272
- Software Interface
  272
- Register Map
  272
- USB Host Register Definitions
  273
Chapter 13: Lpc176X/5X USB OTG

274
How to Read this Chapter

274
Basic Configuration

274
Introduction

274
Features

274
Architecture

275
Modes of Operation

275
Pin Configuration

276
Register Description

278
USB Interrupt Status Register

278
HNP Support

287
- B-Device: Peripheral to Host Switching
  288
  - Remove D+ Pull-Up
    290
  - Add D+ Pull-Up
    291
- A-Device: Host to Peripheral HNP Switching
  291
  - Ceiver
    294
  - Discharge VBUS
    294
  - Load and Enable OTG Timer
    295
  - Stop OTG Timer
    295
  - Suspend Host on Port 1
    295
Clocking and Power Management

295
- Device Clock Request Signals
  296
- Host Clock Request Signals
  297
- Power-Down Mode Support
  297
USB OTG Controller Initialization

297
Chapter 14 : Lpc176X/5X UART0/2/3

299
Basic Configuration

299
Features

299
Pin Description

300
Register Description

300
Architecture

317
Chapter 15: Lpc176X/5X UART1

319
Basic Configuration

319
Features

319
Pin Description

320
Register Description

321
Architecture

342
Chapter 16: Lpc176X/5X CAN1/2

344
Basic Configuration

344
CAN Controllers

344
Features

344
- General CAN Features
  344
- CAN Controller Features
  345
- Acceptance Filter Features
  345
Pin Description

345
CAN Controller Architecture

345
- APB Interface Block (AIB)
  346
- Interface Management Logic (IML)
  346
- Transmit Buffers (TXB)
  346
- Receive Buffer (RXB)
  347
- Error Management Logic (EML)
  348
- Bit Timing Logic (BTL)
  348
- Bit Stream Processor (BSP)
  348
- CAN Controller Self-Tests
  348
  - Global Self Test
    349
  - Local Self Test
    349
Memory Map of the CAN Block

350
CAN Controller Registers

350
CAN Controller Operation

371
- Error Handling
  371
- Sleep Mode
  371
- Interrupts
  372
- Transmit Priority
  372
Centralized CAN Registers

372
Global Acceptance Filter

374
Acceptance Filter Modes

374
- Acceptance Filter off Mode
  375
- Acceptance Filter Bypass Mode
  375
- Acceptance Filter Operating Mode
  375
- Fullcan Mode
  375
Sections of the ID Look-Up Table RAM

375
ID Look-Up Table RAM

376
Acceptance Filter Registers

378
Configuration and Search Algorithm

382
- Acceptance Filter Search Algorithm
  382
Fullcan Mode

383
Examples of Acceptance Filter Tables and ID Index Values

394
Chapter 17: Lpc176X/5X SPI

402
Basic Configuration

402
Features

402
SPI Overview

402
Pin Description

403
SPI Data Transfers

403
SPI Peripheral Details

405
- General Information
  405
- Master Operation
  405
- Slave Operation
  406
- Exception Conditions
  406
Register Description

407
SPI Interrupt Register

411
- 411
  411
Architecture

412
Chapter 18: Lpc176X/5X SSP0/1

413
Basic Configuration

413
Features

413
Description

413
Pin Descriptions

414
Bus Description

414
- Texas Instruments Synchronous Serial Frame
  414
  - Format
    414
- SPI Frame Format
  415
  - Control
    415
- SPI Format with CPOL=0,CPHA=0
  416
- SPI Format with CPOL=0,CPHA=1
  417
- SPI Format with CPOL = 1,CPHA = 0
  417
- SPI Format with CPOL = 1,CPHA = 1
  419
  - Format
    419
- Setup and Hold Time Requirements on CS with Respect to SK in Microwire Mode
  421
Register Description

422
Chapter 19 : Lpc176X/5X I2C0/1/2

429
Basic Configuration

429
Features

429
Applications

430
Description

430
- I 2 C FAST Mode Plus
  431
Pin Description

431
I 2 C Operating Modes

432
- Master Transmitter Mode
  432
- Master Receiver Mode
  433
- Slave Receiver Mode
  434
- Slave Transmitter Mode
  435
I 2 C Implementation and Operation

435
- Input Filters and Output Stages
  435
- Address Registers, I2ADR0 to I2ADR3
  436
- Address Mask Registers, I2MASK0 to I2MASK3
  437
- Comparator
  437
- Shift Register, I2DAT
  437
- Arbitration and Synchronization Logic
  437
- Serial Clock Generator
  438
- Timing and Control
  439
- Control Register, I2CONSET and I2CONCLR 439 Status Decoder and Status Register
  439
Register Description

440
Details of I C Operating Modes

450
- Master Transmitter Mode
  451
- Master Receiver Mode
  453
- Slave Receiver Mode
  455
- Slave Transmitter Mode
  457
- Detailed State Tables
  458
- Miscellaneous States
  463
- I2STAT = 0Xf8
  463
- I2STAT = 0X00
  463
- Some Special Cases
  463
- Simultaneous Repeated START Conditions from Two Masters
  463
- Data Transfer after Loss of Arbitration
  464
- Forced Access to the I C-Bus
  464
- C-Bus Obstructed by a LOW Level on SCL or SDA
  464
- Bus Error
  464
- I 2 C State Service Routines
  466
- Initialization
  466
- I 2 C Interrupt Service
  466
- The State Service Routines
  466
- Adapting State Services to an Application
  466
Software Example

467
- Initialization Routine
  467
- Start Master Transmit Function
  467
- Start Master Receive Function
  467
- C Interrupt Routine
  467
- Non Mode Specific States
  467
- State: 0X00
  467
- Master States
  468
- State: 0X08
  468
- State: 0X10
  468
- Master Transmitter States
  468
- State: 0X18
  468
- State: 0X20
  469
- State: 0X28
  469
- State: 0X30
  469
- State: 0X38
  469
- Master Receive States
  469
- State: 0X40
  469
- State: 0X48
  470
- State: 0X50
  470
- State: 0X58
  470
- Slave Receiver States
  470
- State: 0X60
  470
- State: 0X68
  471
- State: 0X70
  471
- State: 0X78
  471
- State: 0X80
  471
- State: 0X88
  472
- State: 0X90
  472
- State: 0X98
  472
- State: 0Xa0
  472
- Slave Transmitter States
  472
- State: 0Xa8
  472
- State: 0Xb0
  473
- State: 0Xb8
  473
- State: 0Xc0
  473
- State: 0Xc8
  473
Chapter 20 : Lpc176X/5X I2S

474
Basic Configuration

474
Features

474
Description

475
Pin Descriptions

476
Register Description

477
S Transmit and Receive Interfaces

484
S Operating Modes

485
FIFO Controller

489
Chapter 21: Lpc176X/5X Timer 0/1/2/3

491
Basic Configuration

491
Features

491
Applications

492
Description

492
Pin Description

492
- Multiple CAP and MAT Pins
  492
Register Description

493
Example Timer Operation

500
Architecture

501
Chapter 22 : Lpc176X/5X Repetitive Interrupt Timer (RIT)

502
Features

502
Description

502
Register Description

502
RI Timer Operation

503
Description

505
Chapter 23 : Lpc176X/5X System Tick Timer

505
Operation

505
Basic Configuration

505
Features

505
Register Description

506
Example Timer Calculations

509
- Example 1)
  509
- Example 2)
  509
- Example 3)
  509
- Example 4)
  509
Chapter 24: Lpc176X/5X Pulse Width Modulator (PWM)

510
Basic Configuration

510
Features

510
Description

511
Sample Waveform with Rules for Single and Double Edge Control

513
- Rules for Single Edge Controlled PWM Outputs
  514
- Rules for Double Edge Controlled PWM Outputs
  514
Pin Description

514
Register Description

515
Chapter 25: Lpc176X/5X Motor Control PWM

523
Introduction

523
Description

523
Pin Description

523
Block Diagram

524
Configuring Other Modules for MCPWM Use

525
General Operation

525
Register Description

526
PWM Operation

538
- Pulse-Width Modulation
  538
  - Edge-Aligned PWM Without Dead-Time
    538
  - Center-Aligned PWM Without Dead-Time
    538
  - Dead-Time Counter
    539
- Shadow Registers and Simultaneous Updates 540 Fast Abort (ABORT)
  540
- Capture Events
  540
- External Event Counting (Counter Mode)
  541
- Three-Phase DC Mode
  541
- Three Phase AC Mode
  542
- Interrupts
  543
Chapter 26: Lpc176X/5X Quadrature Encoder Interface (QEI)

544
Basic Configuration

544
Features

544
Introduction

544
Functional Description

546
- Input Signals
  546
- Quadrature Input Signals
  546
- Digital Input Filtering
  547
- Position Capture
  547
- Velocity Capture
  547
- Velocity Compare
  548
Pin Description

549
Register Description

550
- Register Summary
  550
- Control Registers
  551
- C000)
  551
- C008)
  551
- QEI Status Register (QEISTAT - 0X400B C004)
  551
- Position, Index and Timer Registers
  552
  - C00C)
    552
- QEI Maximum Position Register (QEIMAXPOS - 0X400B C010)
  552
- QEI Position Compare Register 0 (CMPOS0 - 0X400B C014)
  552
- QEI Position Compare Register 1 (CMPOS1 - 0X400B C018)
  552
- QEI Position Compare Register 2 (CMPOS2 - 0X400B C01C)
  553
- QEI Index Count Register (INXCNT - 0X400B C020)
  553
  - C024)
    553
- QEI Timer Reload Register (QEILOAD - 0X400B C028)
  553
- QEI Timer Register (QEITIME - 0X400B C02C)
  553
  - C030)
    554
  - C034)
    554
  - 0X400B C038)
    554
  - C03C)
    554
- Interrupt Registers
  555
- QEI Interrupt Status Register (QEIINTSTAT)
  555
- QEI Interrupt Set Register (QEISET - 0X400B CFEC)
  555
- QEI Interrupt Clear Register (QEICLR - 0X400B CFE8)
  556
- QEI Interrupt Enable Register (QEIIE - 0X400B CFE4)
  556
- QEI Interrupt Enable Set Register (QEIIES - 0X400B CFDC)
  557
- QEI Interrupt Enable Clear Register (QEIIEC - 0X400B CFD8)
  558
Basic Configuration

559
Chapter 27 : Lpc176X/5X Real-Time Clock (RTC) and Backup Registers

559
Features

559
Description

559
Architecture

560
Pin Description

561
Register Description

561
RTC Usage Notes

569
Chapter 28: Lpc176X/5X Watchdog Timer (WDT)

570
Features

570
Applications

570
Description

571
Register Description

571
Block Diagram

574
Chapter 29 : Lpc176X/5X Analog-To-Digital Converter (ADC)

575
Basic Configuration

575
Features

575
Description

575
Pin Description

576
Register Description

577
Operation

582
- Hardware-Triggered Conversion
  582
- Interrupts
  582
- Accuracy Vs. Digital Receiver
  582
- DMA Control
  582
Chapter 30 : Lpc176X/5X Digital-To-Analog Converter (DAC)

583
Pin Description

583
Basic Configuration

583
Features

583
Register Description

584
Operation

585
- DMA Counter
  585
- Double Buffering
  585
Chapter 31 : Lpc176X/5X General Purpose DMA (GPDMA)

587
Basic Configuration

587
Introduction

587
Features

587
Functional Description

588
- DMA Controller Functional Description
  588
- AHB Slave Interface
  588
- Control Logic and Register Bank
  589
- DMA Request and Response Interface
  589
- Channel Logic and Channel Register Bank
  589
- Interrupt Request
  589
- AHB Master Interface
  589
- Bus and Transfer Widths
  589
- Endian Behavior
  589
- Error Conditions
  591
- Channel Hardware
  592
- DMA Request Priority
  592
- Interrupt Generation
  592
- DMA System Connections
  592
- DMA Request Signals
  592
- DMA Response Signals
  592
- DMA Request Connections
  593
Register Description

594
Using the DMA Controller

608
- Programming the DMA Controller
  608
- Enabling the DMA Controller
  608
- Disabling the DMA Controller
  608
- Enabling a DMA Channel
  608
- Disabling a DMA Channel
  608
  - Disabling a DMA Channel and Losing Data in the FIFO
    608
  - Disabling the DMA Channel Without Losing Data in the FIFO
    608
- Setting up a New DMA Transfer
  608
- Halting a DMA Channel
  609
- Programming a DMA Channel
  609
- Flow Control
  609
- Peripheral-To-Memory or Memory-To-Peripheral DMA Flow
  610
- Peripheral-To-Peripheral DMA Flow
  610
- Memory-To-Memory DMA Flow
  611
- Interrupt Requests
  611
- Hardware Interrupt Sequence Flow
  612
- Address Generation
  612
- Word-Aligned Transfers Across a Boundary . 612 Scatter/Gather
  612
- Linked List Items
  613
- Programming the DMA Controller for Scatter/Gather DMA
  613
- Example of Scatter/Gather DMA
  613
Chapter 32: Lpc176X/5X Flash Memory Interface and Programming

616
Introduction

616
Features

616
Description

616
- Memory Map after any Reset
  617
- Criterion for Valid User Code
  617
- Communication Protocol
  618
- ISP Command Format
  618
- ISP Response Format
  618
- ISP Data Format
  618
- ISP Flow Control
  619
- ISP Command Abort
  619
- Interrupts During IAP
  619
- RAM Used by ISP Command Handler
  619
- RAM Used by IAP Command Handler
  619
Boot Process Flowchart

620
Sector Numbers

621
Code Read Protection (CRP)

622
ISP Commands

624
IAP Commands

632
- Prepare Sector(S) for Write Operation
  634
- Copy RAM to Flash
  635
- Erase Sector(S)
  635
- Blank Check Sector(S)
  636
- Read Part Identification Number
  636
- Read Boot Code Version Number
  636
- Read Device Serial Number
  637
- Compare <Address1> <Address2> <No of Bytes
  637
- Re-Invoke ISP
  637
- IAP Status Codes
  638
JTAG Flash Programming Interface

638
Flash Signature Generation

639
- Register Description for Signature Generation
  639
  - Registers
    640
- Signature Generation Result Registers
  640
  - 0X0X4008 4FE0)
    641
  - 0X0X4008 4FE8)
    641
- Algorithm and Procedure for Signature Generation
  642
  - Signature Generation
    642
  - Content Verification
    642
Chapter 33 : Lpc176X/5X JTAG, Serial Wire Debug (SWD), and Trace

643
Features

643
Introduction

643
Description

643
Pin Description

643
Debug Notes

644
JTAG TAP Identification

645
Debug Memory Re-Mapping

645
- Memory Mapping Control Register (MEMMAP - 0X400F C040)
  645
Chapter 34 : Appendix: Cortex-M3 User Guide

646
ARM Cortex-M3 User Guide: Introduction

646
ARM Cortex-M3 User Guide: Instruction Set

649
- Instruction Set Summary
  649
  - Note
    649
- Intrinsic Functions
  652
- About the Instruction Descriptions
  652
- Operands
  653
- Restrictions When Using PC or SP
  653
- Flexible Second Operand
  653
- Constant
  653
- Register with Optional Shift
  654
- Shift Operations
  654
- Asr
  655
  - Note
    655
- Lsr
  655
- Lsl
  656
  - Note
    656
- Ror
  656
- Rrx
  657
- Address Alignment
  657
- PC-Relative Expressions
  658
  - Note
    658
- Conditional Execution
  658
- The Condition Flags
  659
- Condition Code Suffixes
  659
- Instruction Width Selection
  660
- Example: Instruction Width Selection
  660
- Memory Access Instructions
  661
- Adr
  662
- Syntax
  662
- Operation
  662
- Restrictions
  662
- Condition Flags
  662
- Examples
  662
- LDR and STR, Immediate Offset
  663
- Syntax
  663
- Operation
  663
- Restrictions
  664
- Condition Flags
  664
- Examples
  665
- LDR and STR, Register Offset
  666
- Syntax
  666
- Operation
  666
- Restrictions
  666
- Condition Flags
  667
- Examples
  667
- LDR and STR, Unprivileged
  668
- Syntax
  668
- Operation
  668
- Restrictions
  668
- Condition Flags
  668
- Examples
  669
- LDR, PC-Relative
  670
- Syntax
  670
- Operation
  670
- Restrictions
  670
- Condition Flags
  671
- Examples
  671
- LDM and STM
  672
- Syntax
  672
- Operation
  672
- Restrictions
  673
- Condition Flags
  673
- Examples
  673
- Incorrect Examples
  673
- PUSH and POP
  674
- Syntax
  674
- Operation
  674
- Restrictions
  674
- Condition Flags
  674
- Examples
  674
- LDREX and STREX
  675
- Syntax
  675
- Operation
  675
- Restrictions
  675
- Condition Flags
  676
- Examples
  676
- Clrex
  677
- Syntax
  677
- Operation
  677
- Condition Flags
  677
- Examples
  677
- General Data Processing Instructions
  678
- ADD, ADC, SUB, SBC, and RSB
  679
- Syntax
  679
- Operation
  679
- Restrictions
  679
  - Note
    680
- Condition Flags
  680
- Examples
  680
- Multiword Arithmetic Examples
  680
- AND, ORR, EOR, BIC, and ORN
  682
- Syntax
  682
- Operation
  682
- Restrictions
  682
- Condition Flags
  682
- Examples
  682
- ASR, LSL, LSR, ROR, and RRX
  684
- Syntax
  684
- Operation
  684
- Restrictions
  684
- Condition Flags
  685
- Examples
  685
- Clz
  686
- Syntax
  686
- Operation
  686
- Restrictions
  686
- Condition Flags
  686
- Examples
  686
- CMP and CMN
  687
- Syntax
  687
- Operation
  687
- Restrictions
  687
- Condition Flags
  687
- Examples
  687
- MOV and MVN
  688
- Syntax
  688
- Operation
  688
- Restrictions
  689
- Condition Flags
  689
- Example
  689
- Movt
  690
- Syntax
  690
- Operation
  690
- Restrictions
  690
- Condition Flags
  690
- Examples
  690
- REV, REV16, REVSH, and RBIT
  691
- Syntax
  691
- Operation
  691
- Restrictions
  691
- Condition Flags
  691
- Examples
  691
- TST and TEQ
  692
- Syntax
  692
- Operation
  692
- Restrictions
  692
- Condition Flags
  692
- Examples
  692
- Multiply and Divide Instructions
  693
- MUL, MLA, and MLS
  694
- Syntax
  694
- Operation
  694
- Restrictions
  694
- Condition Flags
  694
- Examples
  695
- UMULL, UMLAL, SMULL, and SMLAL
  696
- Syntax
  696
- Operation
  696
- Restrictions
  696
- Condition Flags
  696
- Examples
  697
- SDIV and UDIV
  698
- Syntax
  698
- Operation
  698
- Restrictions
  698
- Condition Flags
  698
- Examples
  698
- Saturating Instructions
  699
- SSAT and USAT
  699
- Syntax
  699
- Operation
  699
- Restrictions
  700
- Condition Flags
  700
- Examples
  700
- Bitfield Instructions
  701
- BFC and BFI
  702
- Syntax
  702
- Operation
  702
- Restrictions
  702
- Condition Flags
  702
- Examples
  702
- SBFX and UBFX
  703
- Syntax
  703
- Operation
  703
- Restrictions
  703
- Condition Flags
  703
- Examples
  703
- SXT and UXT
  704
- Syntax
  704
- Operation
  704
- Restrictions
  704
- Condition Flags
  704
- Examples
  705
- Branch and Control Instructions
  706
- B, BL, BX, and BLX
  707
- Syntax
  707
- Operation
  707
- Restrictions
  708
- Condition Flags
  708
- Examples
  708
- CBZ and CBNZ
  709
- Syntax
  709
- Operation
  709
- Restrictions
  709
- Condition Flags
  709
- Examples
  709
- Syntax
  710
- Operation
  710
- Restrictions
  710
- Condition Flags
  711
- Example
  711
- TBB and TBH
  713
- Syntax
  713
- Operation
  713
- Restrictions
  713
- Condition Flags
  713
- Examples
  713
- Miscellaneous Instructions
  715
- Bkpt
  716
- Syntax
  716
- Operation
  716
- Condition Flags
  716
- Examples
  716
- Cps
  717
- Syntax
  717
- Operation
  717
- Restrictions
  717
- Condition Flags
  717
- Examples
  717
- Dmb
  718
- Syntax
  718
- Operation
  718
- Condition Flags
  718
- Examples
  718
- Dsb
  719
- Syntax
  719
- Operation
  719
- Condition Flags
  719
- Examples
  719
- Isb
  720
- Syntax
  720
- Operation
  720
- Condition Flags
  720
- Examples
  720
- Mrs
  721
- Syntax
  721
- Operation
  721
- Restrictions
  721
- Condition Flags
  721
- Examples
  721
- Msr
  722
- Syntax
  722
- Operation
  722
  - Note
    722
- Restrictions
  722
- Condition Flags
  722
- Examples
  722
- Nop
  723
- Syntax
  723
- Operation
  723
- Condition Flags
  723
- Examples
  723
- Sev
  724
- Syntax
  724
- Operation
  724
- Condition Flags
  724
- Examples
  724
- Svc
  725
- Syntax
  725
- Operation
  725
- Condition Flags
  725
- Examples
  725
- Wfe
  726
- Syntax
  726
- Operation
  726
- Condition Flags
  726
- Examples
  726
- Wfi
  727
- Syntax
  727
- Operation
  727
- Condition Flags
  727
- Examples
  727
ARM Cortex-M3 User Guide: Processor

728
- Programmers Model
  728
- Processor Mode and Privilege Levels for Software Execution
  728
- Stacks
  728
- Core Registers
  729
- General-Purpose Registers
  730
- Stack Pointer
  730
- Link Register
  730
- Program Counter
  730
- Program Status Register
  730
- Exception Mask Registers
  734
- CONTROL Register
  735
- Exceptions and Interrupts
  735
- Data Types
  736
- The Cortex Microcontroller Software Interface Standard
  736
- Memory Model
  737
- Memory Regions, Types and Attributes
  737
- Memory System Ordering of Memory Accesses
  738
- Behavior of Memory Accesses
  739
- Software Ordering of Memory Accesses
  739
- Bit-Banding
  740
- Directly Accessing an Alias Region
  742
- Directly Accessing a Bit-Band Region
  742
- Memory Endianness
  743
- Little-Endian Format
  743
- Synchronization Primitives
  743
- Programming Hints for the Synchronization Primitives
  744
- Exception Model
  746
- Exception States
  746
- Exception Types
  746
- Exception Handlers
  748
- Vector Table
  749
- Exception Priorities
  749
- Interrupt Priority Grouping
  750
- Exception Entry and Return
  750
- Exception Entry
  751
- Exception Return
  752
- Fault Handling
  754
- Fault Types
  754
- Fault Escalation and Hard Faults
  755
- Fault Status Registers and Fault Address Registers
  755
- Lockup
  756
- Power Management
  757
- Entering Sleep Mode
  757
- Wait for Interrupt
  757
- Wait for Event
  757
- Sleep-On-Exit
  758
- Wakeup from Sleep Mode
  758
- Wakeup from WFI or Sleep-On-Exit
  758
- Wakeup from WFE
  758
- The Wake-Up Interrupt Controller
  758
- Power Management Programming Hints
  759
ARM Cortex-M3 User Guide: Peripherals

760
- About the Cortex-M3 Peripherals
  760
- Nested Vectored Interrupt Controller
  761
- The CMSIS Mapping of the Cortex-M3 NVIC Registers
  761
- Interrupt Set-Enable Registers
  762
- Interrupt Clear-Enable Registers
  762
- Interrupt Set-Pending Registers
  763
- Interrupt Clear-Pending Registers
  763
- Interrupt Active Bit Registers
  764
- Interrupt Priority Registers
  764
- Software Trigger Interrupt Register
  765
- Level-Sensitive and Pulse Interrupts
  765
- Hardware and Software Control of Interrupts
  766
- NVIC Design Hints and Tips
  766
- NVIC Programming Hints
  767
- System Control Block
  768
- The CMSIS Mapping of the Cortex-M3 SCB Registers
  768
- Auxiliary Control Register
  768
- About IT Folding
  769
- CPUID Base Register
  769
- Interrupt Control and State Register
  769
- Vector Table Offset Register
  771
- Application Interrupt and Reset Control Register
  772
- Binary Point
  773
- System Control Register
  773
- Configuration and Control Register
  774
- System Handler Priority Registers
  775
- System Handler Priority Register 1
  776
- System Handler Priority Register 2
  776
- System Handler Priority Register 3
  776
- System Handler Control and State Register
  776
  - Caution
    777
- Configurable Fault Status Register
  778
- Memory Management Fault Status Register
  778
- Bus Fault Status Register
  779
- Usage Fault Status Register
  780
- Hard Fault Status Register
  782
  - Register
    782
- Bus Fault Address Register
  782
- System Control Block Design Hints and Tips
  783
- System Timer, Systick
  784
- Systick Control and Status Register
  784
- Systick Reload Value Register
  785
- Calculating the RELOAD Value
  785
- Systick Current Value Register
  785
- Systick Calibration Value Register
  785
- Systick Design Hints and Tips
  786
- Memory Protection Unit
  787
- MPU Type Register
  788
- MPU Control Register
  789
- MPU Region Number Register
  790
- MPU Region Base Address Register
  790
- The ADDR Field
  791
- MPU Region Attribute and Size Register
  791
- SIZE Field Values
  792
- MPU Access Permission Attributes
  793
- MPU Mismatch
  794
- Updating an MPU Region
  794
  - Words
    794
  - Writes
    795
- Subregions
  796
- MPU Design Hints and Tips
  797
- MPU Configuration for a Microcontroller
  797
ARM Cortex-M3 User Guide: Glossary

798
Abbreviations

802
Legal Information

803
- Definitions
  803
- Disclaimers
  803
- Trademarks
  803
Tables

804
Figures

816
Contents

818

NXP Semiconductors Categories

Motherboard Microcontrollers Computer Hardware Control Unit Controller

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NXP Semiconductors LPC1767 Manuals

NXP Semiconductors LPC1767 User Manual (841 pages)

Table of Contents

Chapter 1: Lpc176X/5X Introductory Information

Introduction

Features

Applications

Ordering Information

Simplified Block Diagram

Chapter 35 : Supplementary Information

Architectural Overview

ARM Cortex-M3 Processor

On-Chip Flash Memory System

On-Chip Static RAM

Block Diagram

Chapter 2: Lpc176X/5X Memory Map

Memory Map and Peripheral Addressing

Memory Maps

APB Peripheral Addresses

Memory Re-Mapping

AHB Arbitration

Bus Fault Exceptions

Chapter 3: Lpc176X/5X System Control

Introduction

Pin Description

Register Description

Reset

Brown-Out Detection

External Interrupt Inputs

Other System Controls and Status Flags

Chapter 4: Lpc176X/5X Clocking and Power Control

Summary of Clocking and Power Control Functions

Register Description

Oscillators

Clock Source Selection Multiplexer

PLL0 (Phase Locked Loop 0)

PLL1 (Phase Locked Loop 1)

Clock Dividers

Power Control

Wake-Up Timer

External Clock Output Pin

Chapter 5: Lpc176X/5X Flash Accelerator

Introduction

Flash Accelerator Blocks

Register Description

Flash Accelerator Configuration Register

Operation

Chapter 6: Lpc176X/5X Nested Vectored Interrupt Controller (NVIC)

Features

Description

Interrupt Sources

Vector Table Remapping

Register Description

Chapter 7: Lpc176X/5X Pin Configuration

Lpc176X/5X Pin Configuration

Lpc176X/5X Pin Description

Chapter 8: Lpc176X/5X Pin Connect Block

How to Read this Chapter

Description

Pin Function Select Register Values

Pin Mode Select Register Values

Register Description

Chapter 9 : Lpc176X/5X General Purpose Input/Output (GPIO)

Basic Configuration

Features

Applications

Pin Description

Register Description

GPIO Usage Notes

Chapter 10: Lpc176X/5X Ethernet

Basic Configuration

Introduction

Features

Architecture and Operation

DMA Engine Functions

Overview of DMA Operation

Ethernet Packet

Overview

Pin Description

Registers and Software Interface