NXP Semiconductors LPC1102 User Manual
  1. Manuals
  2. Brands
  3. NXP Semiconductors Manuals
  4. Microcontrollers
  5. LPC1102
  6. User manual
NXP Semiconductors LPC1102 User Manual

NXP Semiconductors LPC1102 User Manual

Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
UM10429
LPC1102 User manual
Rev. 1 — 20 October 2010
Document information
Info
Content
Keywords
ARM Cortex-M0, LPC1102, LPC1102UK
Abstract
LPC1102 User manual
User manual

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the LPC1102 and is the answer not in the manual?

Questions and answers

Related Manuals for NXP Semiconductors LPC1102

Summary of Contents for NXP Semiconductors LPC1102

  • Page 1 UM10429 LPC1102 User manual Rev. 1 — 20 October 2010 User manual Document information Info Content Keywords ARM Cortex-M0, LPC1102, LPC1102UK Abstract LPC1102 User manual...
  • Page 2 UM10429 NXP Semiconductors LPC1102 UM Revision history Date Description 20101020 LPC1102 User manual Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com UM10429 All information provided in this document is subject to legal disclaimers.

  • Page 3: Chapter 1: Lpc1102 Introductory Information

    The LPC1102 operates at CPU frequencies of up to 50 MHz. The peripheral complement of the LPC1102 includes 32 kB of flash memory, 8 kB of data memory, one RS-485/EIA-485 UART, one SPI interface with SSP features, four general purpose counter/timers, a 10-bit ADC, and 11 general purpose I/O pins.

  • Page 4: Ordering Information

    UM10429 NXP Semiconductors Chapter 1: LPC1102 Introductory information • Serial interfaces: – UART with fractional baud rate generation, internal FIFO, and RS-485 support. – One SPI controller with SSP features and with FIFO and multi-protocol capabilities. • Clock generation: – 12 MHz internal RC oscillator trimmed to 1% accuracy that can optionally be used as a system clock.
  • Page 5 UM10429 NXP Semiconductors Chapter 1: LPC1102 Introductory information 1.4 Block diagram XTALIN RESET LPC1102 CLOCK GENERATION, POWER CONTROL, TEST/DEBUG SYSTEM INTERFACE FUNCTIONS clocks and CORTEX-M0 controls FLASH SRAM 32 kB 8 kB system bus slave slave slave slave HIGH-SPEED GPIO port...
  • Page 6 1.5 ARM Cortex-M0 processor The ARM Cortex-M0 processor is described in detail in Section 19.2 “About the Cortex-M0 processor and core peripherals”. For the LPC1102, the ARM Cortex-M0 processor core is configured as follows: • System options: – The Nested Vectored Interrupt Controller (NVIC) is included and supports up to 32 interrupts.

  • Page 7: Chapter 2: Lpc1102 Memory Mapping

    The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals. On the LPC1102, the GPIO ports are the only AHB peripherals. The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals. Each peripheral of either type is allocated 16 kB of space.
  • Page 8 UM10429 NXP Semiconductors Chapter 2: LPC1102 Memory mapping AHB peripherals LPC1102 0x5020 0000 4 GB 0xFFFF FFFF reserved 0xE010 0000 127 - 16 reserved private peripheral bus 0xE000 0000 0x5004 0000 reserved reserved 15-12 0x5003 0000 0x5020 0000 reserved 11-8...

  • Page 9: Chapter 3: Lpc1102 System Configuration

    3.2 Introduction The system configuration block controls oscillators, start logic, and clock generation of the LPC1102. Also included in this block are registers for setting the priority for AHB access and a register for remapping flash, SRAM, and ROM memory areas.

  • Page 10: Register Description

    UM10429 NXP Semiconductors Chapter 3: LPC1102 System configuration AHB clock 0 (system) system clock SYSTEM CLOCK DIVIDER AHB clocks 1 to 18 (memories and peripherals) AHBCLKCTRL[1:18] SPI0 PERIPHERAL SPI0_PCLK CLOCK DIVIDER IRC oscillator main clock UART PERIPHERAL UART_PCLK CLOCK DIVIDER...
  • Page 11 UM10429 NXP Semiconductors Chapter 3: LPC1102 System configuration Table 5. Register overview: system control block (base address 0x4004 8000) …continued Name Access Address offset Description Reset Reference value SYSRSTSTAT 0x030 System reset status register 0x000 Table 13 0x034 - 0x03C...

  • Page 12: System Memory Remap Register

    UM10429 NXP Semiconductors Chapter 3: LPC1102 System configuration Table 5. Register overview: system control block (base address 0x4004 8000) …continued Name Access Address offset Description Reset Reference value PDRUNCFG 0x238 Power-down configuration register 0x0000 Table 35 EDF0 0x23C - 0x3F0...

  • Page 13: System Pll Control Register

    UM10429 NXP Semiconductors Chapter 3: LPC1102 System configuration 3.5.3 System PLL control register This register connects and enables the system PLL and configures the PLL multiplier and divider values. The PLL accepts an input frequency from 10 MHz to 25 MHz from various clock sources.

  • Page 14: Watchdog Oscillator Control Register

    UM10429 NXP Semiconductors Chapter 3: LPC1102 System configuration Table 10. System oscillator control register (SYSOSCCTRL, address 0x4004 8020) bit description Symbol Value Description Reset value FREQRANGE Determines frequency range for Low-power oscillator. 1 - 20 MHz frequency range. 15 - 25 MHz frequency range...

  • Page 15: Internal Resonant Crystal Control Register

    UM10429 NXP Semiconductors Chapter 3: LPC1102 System configuration Table 11. Watchdog oscillator control register (WDTOSCCTRL, address 0x4004 8024) bit description …continued Symbol Value Description Reset value FREQSEL Select watchdog oscillator analog output frequency 0x00 (Fclkana). 0.5 MHz 0.8 MHz 1.1 MHz 1.4 MHz...

  • Page 16: System Reset Status Register

    UM10429 NXP Semiconductors Chapter 3: LPC1102 System configuration 3.5.8 System reset status register if another reset signal - for example EXTRST - remains asserted after the POR signal is negated, then its bit is set to detected. Table 13. System reset status register (SYSRSTSTAT, address 0x4004 8030) bit description...

  • Page 17: System Pll Clock Source Update Enable Register

    UM10429 NXP Semiconductors Chapter 3: LPC1102 System configuration 3.5.10 System PLL clock source update enable register This register updates the clock source of the system PLL with the new input clock after the SYSPLLCLKSEL register has been written to. In order for the update to take effect, first write a zero to the SYSPLLUEN register and then write a one to SYSPLLUEN.

  • Page 18: System Ahb Clock Divider Register

    UM10429 NXP Semiconductors Chapter 3: LPC1102 System configuration Table 17. Main clock source update enable register (MAINCLKUEN, address 0x4004 8074) bit description Symbol Value Description Reset value Enable main clock source update No change Update clock source 31:1 Reserved 0x00 3.5.13 System AHB clock divider register...
  • Page 19 UM10429 NXP Semiconductors Chapter 3: LPC1102 System configuration Table 19. System AHB clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit description …continued Symbol Value Description Reset value FLASHREG Enables clock for flash register interface. Disabled Enabled FLASHARRAY Enables clock for flash array access.

  • Page 20: Spi0 Clock Divider Register

    UM10429 NXP Semiconductors Chapter 3: LPC1102 System configuration Table 19. System AHB clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit description …continued Symbol Value Description Reset value IOCON Enables clock for I/O configuration block. Disable Enable 31:17 Reserved 0x00 3.5.15 SPI0 clock divider register This register configures the SPI0 peripheral clock SPI0_PCLK.

  • Page 21: Wdt Clock Source Update Enable Register

    UM10429 NXP Semiconductors Chapter 3: LPC1102 System configuration Table 22. WDT clock source select register (WDTCLKSEL, address 0x4004 80D0) bit description Symbol Value Description Reset value WDT clock source 0x00 IRC oscillator Main clock Watchdog oscillator Reserved 31:2 Reserved 0x00 3.5.18 WDT clock source update enable register...

  • Page 22: Bod Control Register

    UM10429 NXP Semiconductors Chapter 3: LPC1102 System configuration Table 25. POR captured PIO status registers 0 (PIOPORCAP0, address 0x4004 8100) bit description Symbol Description Reset value CAPPIO0_0 Raw reset status input PIO0_0 User implementation dependent Reserved. CAPPIO0_8 Raw reset status input PIO0_8...

  • Page 23: System Tick Counter Calibration Register

    UM10429 NXP Semiconductors Chapter 3: LPC1102 System configuration Table 26. BOD control register (BODCTRL, address 0x4004 8150) bit description Symbol Value Description Reset value BODRSTENA BOD reset enable Disable reset function. Enable reset function. 31:5 - Reserved 0x00 3.5.22 System tick counter calibration register...

  • Page 24: Start Logic Signal Enable Register 0

    UM10429 NXP Semiconductors Chapter 3: LPC1102 System configuration Table 28. Start logic edge control register 0 (STARTAPRP0, address 0x4004 8200) bit description …continued Symbol Value Description Reset value APRPIO0_10 Edge select for start logic input PIO0_10 Falling edge Rising edge...

  • Page 25: Start Logic Reset Register 0

    UM10429 NXP Semiconductors Chapter 3: LPC1102 System configuration 3.5.25 Start logic reset register 0 Writing a one to a bit in the STARTRSRP0CLR register resets the start logic state. The bit assignment is identical to Table 28. The start-up logic uses the input signals to generate a clock edge for registering a start signal.

  • Page 26: Deep-Sleep Mode Configuration Register

    UM10429 NXP Semiconductors Chapter 3: LPC1102 System configuration Table 31. Start logic status register 0 (STARTSRP0, address 0x4004 820C) bit description Symbol Value Description Reset value SRPIO0_8 Start signal status for start logic input PIO0_8 No start signal received Start signal pending...
  • Page 27 UM10429 NXP Semiconductors Chapter 3: LPC1102 System configuration the WDTOSCCTRL = 0001, see Table 11) and all peripheral clocks other than the timer clock must be disabled in the SYSAHBCLKCTRL register (see Table 19) before entering Deep-sleep mode. The watchdog oscillator, if running, contributes an additional current drain in Deep-sleep mode.
  • Page 28 UM10429 NXP Semiconductors Chapter 3: LPC1102 System configuration Table 34. Wake-up configuration register (PDAWAKECFG, address 0x4004 8234) bit description …continued Symbol Value Description Reset value FLASH_PD Flash wake-up configuration Powered Powered down BOD_PD BOD wake-up configuration Powered Powered down ADC_PD...
  • Page 29 Reserved. Always write these bits as 111. 31:16 Reserved 3.5.30 Device ID register This device ID register is a read-only register and contains the part ID for each LPC1102 part. This register is also read by the ISP/IAP commands (Section 19.5.11).
  • Page 30 26). 3.8 Power management The LPC1102 support a variety of power control features. In Active mode, when the chip is running, power and clocks to selected peripherals can be optimized for power consumption. In addition, there are three special modes of processor power reduction: Sleep mode and Deep-sleep mode mode.

  • Page 31: Power Configuration In Active Mode

    UM10429 NXP Semiconductors Chapter 3: LPC1102 System configuration 3.8.1.1 Power configuration in Active mode Power consumption in Active mode is determined by the following configuration choices: • The SYSAHBCLKCTRL register controls which memories and peripherals are running (Table 19). •...

  • Page 32: Wake-Up From Sleep Mode

    UM10429 NXP Semiconductors Chapter 3: LPC1102 System configuration 3.8.2.3 Wake-up from Sleep mode Sleep mode is exited automatically when an interrupt enabled by the NVIC arrives at the processor or a reset occurs. After wake-up due to an interrupt, the microcontroller returns to its original power configuration defined by the contents of the PDRUNCFG and the SYSAHBCLKDIV registers.

  • Page 33: Wake-Up From Deep-Sleep Mode

    3.9 Deep-sleep mode details 3.9.1 IRC oscillator The IRC is the only oscillator on the LPC1102 that can always shut down glitch-free. Therefore it is recommended that the user switches the clock source to IRC before the chip enters Deep-sleep mode.

  • Page 34: Using The General Purpose Counter/Timers To Create A Self-Wake-Up Event

    10. Use the ARM WFI instruction to enter Deep-sleep mode. 3.10 System PLL functional description The LPC1102 uses the system PLL to create the clocks for the core and peripherals. UM10429 All information provided in this document is subject to legal disclaimers.

  • Page 35: Lock Detector

    UM10429 NXP Semiconductors Chapter 3: LPC1102 System configuration irc_osc_clk sys_osc_clk PSEL<1:0> SYSPLLCLKSEL LOCK FCLKOUT LOCK DETECT analog section MSEL<4:0> Fig 4. System PLL block diagram The block diagram of this PLL is shown in Figure 4. The input frequency range is 10 MHz to 25 MHz.

  • Page 36: Divider Ratio Programming

    UM10429 NXP Semiconductors Chapter 3: LPC1102 System configuration stopped and the dividers will enter a reset state. While in Power-down mode, the lock output will be low to indicate that the PLL is not in lock. When the Power-down mode is terminated by setting the SYSPLL_PD bits to zero, the PLL will resume its normal operation and will make the lock signal high once it has regained lock on the input clock.

  • Page 37: Power-Down Mode

    FLASHCFG register at address 0x4003 C010. This register is part of the flash configuration block (see Figure Remark: Improper setting of this register may result in incorrect operation of the LPC1102 flash memory. UM10429 All information provided in this document is subject to legal disclaimers.
  • Page 38 UM10429 NXP Semiconductors Chapter 3: LPC1102 System configuration Table 39. Flash configuration register (FLASHCFG, address 0x4003 C010) bit description Symbol Value Description Reset value FLASHTIM Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access.

  • Page 39: Power Control Register

    Reserved. This bit must always be written as 0. Reserved. These bits must always be written as 0. SLEEPFLAG Sleep mode flag Read: No power-down mode entered. LPC1102 is in Active mode. Write: No effect. Read: Sleep/Deep-sleepmode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0.

  • Page 40: Definitions

    UM10429 Chapter 5: LPC1102 Power profiles Rev. 1 — 20 October 2010 User manual 5.1 Features • Includes ROM-based application services • Power Management services • Clocking services 5.2 Description This chapter describes calls that applications can make to code that is included in on-chip ROM to facilitate power management and clocking setup.

  • Page 41: System Pll Input Frequency And Expected System Clock

    UM10429 NXP Semiconductors Chapter 5: LPC1102 Power profiles The routine returns a result code that indicates if the system PLL was successfully set (PLL_CMD_SUCCESS) or not (in which case the result code identifies what went wrong). The current system frequency value is also returned. The application should use this information to adjust other clocks in the device (the SSP, UART, and WDT clocks, and/or clockout).

  • Page 42: System Pll Lock Timeout

    UM10429 NXP Semiconductors Chapter 5: LPC1102 Power profiles CPU_FREQ_LTE can be used if the requested frequency should not be exceeded (such as overall current consumption and/or power budget reasons). CPU_FREQ_GTE helps applications that need a minimum level of CPU processing capabilities.

  • Page 43: Exact Solution Cannot Be Found (Pll)

    UM10429 NXP Semiconductors Chapter 5: LPC1102 Power profiles 5.4.1.4.3 Exact solution cannot be found (PLL) command[0] = 12000; command[1] = 25000; command[2] = CPU_FREQ_EQU; command[3] = 0; (*rom)->pWRD->set_pll(command, result); The above code specifies a 12 MHz PLL input clock and a system clock of exactly 25 MHz.
  • Page 44 UM10429 NXP Semiconductors Chapter 5: LPC1102 Power profiles 5.5 Power routine 5.5.1 set_power This routine configures the device’s internal power control settings according to the calling arguments. The goal is to reduce active power consumption while maintaining the feature of interest to the application close to its optimum.
  • Page 45 UM10429 NXP Semiconductors Chapter 5: LPC1102 Power profiles using power profiles and changing system clock current_clock, current_mode new_clock, new_mode True current_clock = new_clock? use power routine call False to change mode from current_mode to new_mode current_mode = DEFAULT? True current_mode = new_mode?
  • Page 46 UM10429 NXP Semiconductors Chapter 5: LPC1102 Power profiles Table 43. set_power routine Routine set_power Input Param0: new system clock (in MHz) Param1: mode (PWR_DEFAULT, PWR_CPU_PERFORMANCE, PWR_ EFFICIENCY, PWR_LOW_CURRENT) Param2: current system clock (in MHz) Result Result0: PWR_CMD_SUCCESS | PWR_INVALID_FREQ |...
  • Page 47 UM10429 NXP Semiconductors Chapter 5: LPC1102 Power profiles 5.5.1.4 Code examples The following examples illustrate some of the set_power features discussed above. 5.5.1.4.1 Invalid frequency (device maximum clock rate exceeded) command[0] = 55; command[1] = PWR_CPU_PERFORMANCE; command[2] = 12; (*rom)->pWRD->set_power(command, result);...

  • Page 48: Chapter 6: Lpc1102 Interrupt Controller

    Rev. 1 — 20 October 2010 User manual 6.1 How to read this chapter This chapter applies to the LPC1102 part. 6.2 Introduction The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts.
  • Page 49 UM10429 NXP Semiconductors Chapter 6: LPC1102 Interrupt controller Table 44. Connection of interrupt sources to the Vectored Interrupt Controller Exception Vector Function Flag(s) Number Offset Reserved CT16B0 Match 0 - 2 CT16B1 Match 0 - 1 CT32B0 Match 0 - 3...

  • Page 50: How To Read This Chapter

    Chapter 7: LPC1102 I/O Configuration Rev. 1 — 20 October 2010 User manual 7.1 How to read this chapter This chapter applies to part LPC1102. 7.2 Introduction The I/O configuration registers control the electrical characteristics of the pads. The following features are programmable: •...

  • Page 51: Pin Function

    UM10429 NXP Semiconductors Chapter 7: LPC1102 I/O Configuration output enable pin configured as digital output output driver weak pull-up pull-up enable weak repeater mode pull-down pin configured enable as digital input pull-down enable data input select analog input pin configured...
  • Page 52 7.3.3 Hysteresis The input buffer for digital functions can be configured with hysteresis or as plain buffer through the IOCON registers (see the LPC1102 data sheet for details). If the external pad supply voltage V is between 2.5 V and 3.6 V, the hysteresis buffer can be enabled or disabled.
  • Page 53 UM10429 NXP Semiconductors Chapter 7: LPC1102 I/O Configuration Table 45. Register overview: I/O configuration (base address 0x4004 4000) Name Access Address Description Reset Reference offset value IOCON_SWDIO_PIO1_3 0x090 I/O configuration for pin 0xD0 Table 55 SWDIO/PIO1_3/AD4/CT32B1_MAT2 0x094 - Reserved 0x0A0...
  • Page 54 UM10429 NXP Semiconductors Chapter 7: LPC1102 I/O Configuration Table 47. IOCON_nRESET_PIO0_0 register (IOCON_nRESET_PIO0_0, address 0x4004 400C) bit description Symbol Value Description Reset value Hysteresis. Disable. Enable. Reserved. 31:8 Reserved. Table 48. IOCON_PIO0_8 register (IOCON_PIO0_8, address 0x4004 4060) bit description Symbol...
  • Page 55 UM10429 NXP Semiconductors Chapter 7: LPC1102 I/O Configuration Table 49. IOCON_PIO0_9 register (IOCON_PIO0_9, address 0x4004 4064) bit description Symbol Value Description Reset value Hysteresis. Disable. Enable. Reserved. 31:8 Reserved. Table 50. IOCON_SWCLK_PIO0_10 register (IOCON_SWCLK_PIO0_10, address 0x4004 4068) bit description Symbol Value...
  • Page 56 UM10429 NXP Semiconductors Chapter 7: LPC1102 I/O Configuration Table 51. IOCON_R_PIO0_11 register (IOCON_R_PIO0_11, address 0x4004 4074) bit description …continued Symbol Value Description Reset value MODE Selects function mode (on-chip pull-up/pull-down resistor control). Inactive (no pull-down/pull-up resistor enabled). Pull-down resistor enabled.
  • Page 57 UM10429 NXP Semiconductors Chapter 7: LPC1102 I/O Configuration Table 53. IOCON_R_PIO1_1 register (IOCON_R_PIO1_1, address 0x4004 407C) bit description Symbol Value Description Reset value FUNC Selects pin function. Values 0x4 to 0x7 are reserved. Selects function R. This function is reserved. Select one of the alternate functions below.
  • Page 58 UM10429 NXP Semiconductors Chapter 7: LPC1102 I/O Configuration Table 54. IOCON_R_PIO1_2 register (IOCON_R_PIO1_2, address 0x4004 4080) bit description Symbol Value Description Reset value FUNC Selects pin function. Values 0x4 to 0x7 are reserved. Selects function R. This function is reserved. Select one of the alternate functions below.
  • Page 59 UM10429 NXP Semiconductors Chapter 7: LPC1102 I/O Configuration Table 55. IOCON_SWDIO_PIO1_3 register (IOCON_SWDIO_PIO1_3, address 0x4004 4090) bit description …continued Symbol Value Description Reset value Reserved. ADMODE Select Analog/Digital mode. Analog input mode. Digital functional mode. 31:8 Reserved. Table 56. IOCON_PIO1_6 register (IOCON_PIO1_6, address 0x4004 40A4) bit description...
  • Page 60 UM10429 NXP Semiconductors Chapter 7: LPC1102 I/O Configuration Table 57. IOCON_PIO1_7 register (IOCON_PIO1_7, address 0x4004 40A8) bit description Symbol Value Description Reset value Hysteresis. Disable. Enable. Reserved. 31:8 Reserved. UM10429 All information provided in this document is subject to legal disclaimers.

  • Page 61: Chapter 8: Lpc1102 Pin Configuration

    UM10429 Chapter 8: LPC1102 Pin configuration Rev. 1 — 20 October 2010 User manual 8.1 How to read this chapter The LPC1102 is available in a WLCSP16 package. 8.2 Pin configuration ball A1 index area Fig 7. Pin configuration WLCSP16 package Table 58.
  • Page 62 UM10429 NXP Semiconductors Chapter 8: LPC1102 Pin configuration Table 58. Pin description table …continued Symbol Start Type Reset Description logic state input R/PIO0_11/ I; PU R — Reserved. AD0/CT32B0_MAT3 PIO0_11 — General purpose digital input/output pin. AD0 — A/D converter, input 0.

  • Page 63: How To Read This Chapter

    UM10429 Chapter 9: LPC1102 General Purpose I/O (GPIO) Rev. 1 — 20 October 2010 User manual 9.1 How to read this chapter Table 59 for available GPIO pins: Table 59. GPIO configuration Part Package GPIO port 0 GPIO port 1...

  • Page 64: Gpio Data Register

    UM10429 NXP Semiconductors Chapter 9: LPC1102 General Purpose I/O (GPIO) Table 60. Register overview: GPIO (base address port 0: 0x5000 0000; port 1: 0x5001 0000) Name Access Address offset Description Reset value GPIOnMIS 0x8018 Masked interrupt status register for port n...

  • Page 65: Gpio Data Direction Register

    UM10429 NXP Semiconductors Chapter 9: LPC1102 General Purpose I/O (GPIO) 9.3.2 GPIO data direction register Table 62. GPIOnDIR register (GPIO0DIR, address 0x5000 8000 to GPIO3DIR, address 0x5003 8000) bit description Symbol Description Reset Access value 11:0 Selects pin x as input or output (x = 0 to 11).

  • Page 66: Gpio Interrupt Mask Register

    UM10429 NXP Semiconductors Chapter 9: LPC1102 General Purpose I/O (GPIO) 9.3.6 GPIO interrupt mask register Bits set to HIGH in the GPIOnIE register allow the corresponding pins to trigger their individual interrupts and the combined GPIOnINTR line. Clearing a bit disables interrupt triggering on that pin.

  • Page 67: Write Operation

    UM10429 NXP Semiconductors Chapter 9: LPC1102 General Purpose I/O (GPIO) Table 69. GPIOnIC register (GPIO0IC, address 0x5000 801C to GPIO3IC, address 0x5003 801C) bit description Symbol Description Reset Access value 11:0 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears 0x00 the interrupt edge detection logic.

  • Page 68: Read Operation

    UM10429 NXP Semiconductors Chapter 9: LPC1102 General Purpose I/O (GPIO) Read operation If the address bit associated with the GPIO data bit is HIGH, the value is read. If the address bit is LOW, the GPIO data bit is read as 0. Reading a port DATA register yields the state of port pins 11:0 ANDed with address bits 13:2.
  • Page 69 UM10429 Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART) Rev. 1 — 20 October 2010 User manual 10.1 How to read this chapter The UART block is implemented on the LPC1101 without modem control. 10.2 Basic configuration The UART is configured using the following registers: 1.
  • Page 70 UM10429 NXP Semiconductors Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART) Table 71. Register overview: UART (base address: 0x4000 8000) Name Access Address Description Reset offset value U0RBR 0x000 Receiver Buffer Register. Contains the next received character to be read. (DLAB=0)
  • Page 71 UM10429 NXP Semiconductors Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART) 10.5.1 UART Receiver Buffer Register ( DLAB = 0, Read Only) The U0RBR is the top byte of the UART RX FIFO. The top byte of the RX FIFO contains the oldest character received and can be read via the bus interface.
  • Page 72 UM10429 NXP Semiconductors Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART) Table 74. UART Divisor Latch LSB Register (U0DLL - address 0x4000 8000 when DLAB = 1) bit description Symbol Description Reset value DLLSB The UART Divisor Latch LSB Register, along with the U0DLM 0x01 register, determines the baud rate of the UART.

  • Page 73: Uart Interrupt Identification Register (U0Iir - 0X4004 8008, Read Only)

    UM10429 NXP Semiconductors Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART) Table 76. UART Interrupt Enable Register (U0IER - address 0x4000 8004 when DLAB = 0) bit description …continued Symbol Value Description Reset value ABTOIntEn Enables the auto-baud time-out interrupt. Disable auto-baud time-out Interrupt.
  • Page 74 UM10429 NXP Semiconductors Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART) If the IntStatus bit is one and no interrupt is pending and the IntId bits will be zero. If the IntStatus is 0, a non auto-baud interrupt is pending in which case the IntId bits identify the...

  • Page 75: Uart Fifo Control Register (Write Only)

    UM10429 NXP Semiconductors Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART) Table 78. UART Interrupt Handling U0IIR[3:0] Priority Interrupt Interrupt source Interrupt value type reset 0100 Second RX Data Rx data available or trigger level reached in FIFO U0RBR Available (U0FCR0=1)

  • Page 76: Uart Line Control Register

    UM10429 NXP Semiconductors Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART) Table 79. UART FIFO Control Register (U0FCR - address 0x4000 8008, Write Only) bit description Symbol Value Description Reset value FIFOEN FIFO Enable UART FIFOs are disabled. Must not be used in the application.

  • Page 77: Uart Line Status Register

    UM10429 NXP Semiconductors Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART) Table 80. UART Line Control Register (U0LCR - address 0x4000 800C) bit description Symbol Value Description Reset Value Parity Enable Disable parity generation and checking. Enable parity generation and checking.
  • Page 78 UM10429 NXP Semiconductors Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART) Table 81. UART Line Status Register (U0LSR - address 0x4000 8014, Read Only) bit description …continued Bit Symbol Value Description Reset Value Parity Error When the parity bit of a received character is in the wrong state, a parity error occurs.

  • Page 79: Uart Scratch Pad Register

    UM10429 NXP Semiconductors Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART) Table 81. UART Line Status Register (U0LSR - address 0x4000 8014, Read Only) bit description …continued Bit Symbol Value Description Reset Value RXFE Error in RX FIFO U0LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the U0RBR.

  • Page 80: Auto-Baud

    UM10429 NXP Semiconductors Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART) Table 83. Auto-baud Control Register (U0ACR - address 0x4000 8020) bit description Symbol Value Description Reset value ABEOIntClr End of auto-baud interrupt clear bit (write only accessible). Writing a 0 has no impact.

  • Page 81: Auto-Baud Modes

    UM10429 NXP Semiconductors Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART) × CLK PCLK ≤ ≤ ratemin ------------------------ - ----------------------------------------------------------------------------------------------------------- - UART baudrate ratemax × 16 2 15 × databits paritybits stopbits 10.5.12 Auto-baud modes When the software is expecting an ”AT" command, it configures the UART with the expected character format and sets the U0ACR Start bit.

  • Page 82: Uart Fractional Divider Register (U0Fdr - 0X4000 8028)

    UM10429 NXP Semiconductors Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART) 'A' (0x41) or 'a' (0x61) start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop UARTn RX start bit LSB of 'A' or 'a' U0ACR start rate counter 16xbaud_rate...

  • Page 83: Baud Rate Calculation

    UM10429 NXP Semiconductors Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART) Table 84. UART Fractional Divider Register (U0FDR - address 0x4000 8028) bit description Function Description Reset value DIVADDVAL Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART baud rate.
  • Page 84 UM10429 NXP Semiconductors Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART) Calculating UART baudrate (BR) PCLK, = PCLK/(16 x BR) is an True integer? DIVADDVAL = 0 False MULVAL = 1 = 1.5 Pick another FR from = Int(PCLK/(16 x BR x FR the range [1.1, 1.9]...

  • Page 85: Example 1: Uart_Pclk = 14.7456 Mhz, Br

    UM10429 NXP Semiconductors Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART) Table 85. Fractional Divider setting look-up table DivAddVal/ DivAddVal/ DivAddVal/ DivAddVal/ MulVal MulVal MulVal MulVal 1.000 1.250 1.500 1.750 1.067 1/15 1.267 4/15 1.533 8/15 1.769 10/13 1.071 1/14 1.273 3/11 1.538...

  • Page 86: Uart Rs485 Control Register

    UM10429 NXP Semiconductors Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART) Although Table 86 describes how to use TxEn bit in order to achieve hardware flow control, it is strongly suggested to let UART hardware implemented auto flow control features take care of this, and limit the scope of TxEn to software flow control.

  • Page 87: Uart Rs-485 Address Match Register (U0Rs485Adrmatch - 0X4000 8050)

    UM10429 NXP Semiconductors Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART) 10.5.16 UART RS-485 Address Match register (U0RS485ADRMATCH - 0x4000 8050) The U0RS485ADRMATCH register contains the address match value for RS-485/EIA-485 mode. Table 88. UART RS-485 Address Match register (U0RS485ADRMATCH - address...
  • Page 88 UM10429 NXP Semiconductors Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART) While the receiver is enabled (RS485CTRL bit 1 = ‘0’), all bytes received will be accepted and stored in the RXFIFO until an address byte which does not match the RS485ADRMATCH value is received.
  • Page 89 UM10429 NXP Semiconductors Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART) U0TX NTXRDY U0THR U0TSR U0BRG U0DLL NBAUDOUT U0DLM RCLK U0RX NRXRDY INTERRUPT U0RBR U0RSR U0IER U0INTR U0IIR U0FCR U0LSR U0SCR U0LCR PA[2:0] PSEL PSTB PWRITE PD[7:0] DDIS INTERFACE PCLK Fig 12. UART block diagram UM10429 All information provided in this document is subject to legal disclaimers.

  • Page 90: Chapter 11: Lpc1102 Spi0 With Ssp

    UM10429 Chapter 11: LPC1102 SPI0 with SSP Rev. 1 — 20 October 2010 User manual 11.1 How to read this chapter The LPC1102 includes one SPI interface. Remark: The SPI block includes the full SSP feature set, and all register names use the SSP prefix.

  • Page 91: Pin Description

    UM10429 NXP Semiconductors Chapter 11: LPC1102 SPI0 with SSP 11.5 Pin description Table 89. SPI pin descriptions Interface pin name/function Type Pin description name Microwire SCK0/1 Serial Clock. SCK/CLK/SK is a clock signal used to synchronize the transfer of data. It is driven by the master and received by the slave.

  • Page 92: Spi/Ssp Control Register 0

    UM10429 NXP Semiconductors Chapter 11: LPC1102 SPI0 with SSP Remark: Register names use the SSP prefix to indicate that the SPI controllers have full SSP capabilities. Table 90. Register overview: SPI0 (base address 0x4004 0000) Name Access Address Description Reset...
  • Page 93 UM10429 NXP Semiconductors Chapter 11: LPC1102 SPI0 with SSP Table 91: SPI/SSP Control Register 0 (SSP0CR0 - address 0x4004 0000) bit description Symbol Value Description Reset Value Frame Format. Microwire This combination is not supported and should not be used.

  • Page 94: Spi/Ssp Data Register

    UM10429 NXP Semiconductors Chapter 11: LPC1102 SPI0 with SSP Table 92: SPI/SSP Control Register 1 (SSP0CR1 - address 0x4004 0004) bit description Symbol Value Description Reset Value Master/Slave Mode.This bit can only be written when the SSE bit is 0.

  • Page 95: Spi/Ssp Status Register

    UM10429 NXP Semiconductors Chapter 11: LPC1102 SPI0 with SSP Table 94: SPI/SSP Status Register (SSP0SR - address 0x4004 000C) bit description Symbol Description Reset Value Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not.

  • Page 96: Spi/Ssp Raw Interrupt Status Register

    UM10429 NXP Semiconductors Chapter 11: LPC1102 SPI0 with SSP Table 96: SPI/SSP Interrupt Mask Set/Clear register (SSP0IMSC - address 0x4004 0014) bit description Symbol Description Reset Value RORIM Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received.
  • Page 97 UM10429 NXP Semiconductors Chapter 11: LPC1102 SPI0 with SSP Table 98: SPI/SSP Masked Interrupt Status register (SSP0MIS - address 0x4004 001C) bit description Symbol Description Reset Value RORMIS This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled.
  • Page 98 UM10429 NXP Semiconductors Chapter 11: LPC1102 SPI0 with SSP DX/DR 4 to 16 bits a. Single frame transfer DX/DR 4 to 16 bits 4 to 16 bits b. Continuous/back-to-back frames transfer Fig 13. Texas Instruments Synchronous Serial Frame Format: a) Single and b) Continuous/back-to-back Two...
  • Page 99 UM10429 NXP Semiconductors Chapter 11: LPC1102 SPI0 with SSP The CPHA control bit selects the clock edge that captures data and allows it to change state. It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge.
  • Page 100 UM10429 NXP Semiconductors Chapter 11: LPC1102 SPI0 with SSP In the case of a single word transmission, after all bits of the data word have been transferred, the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured.
  • Page 101 UM10429 NXP Semiconductors Chapter 11: LPC1102 SPI0 with SSP SSEL MOSI MISO 4 to 16 bits a. Single transfer with CPOL=1 and CPHA=0 SSEL MOSI MISO 4 to 16 bits 4 to 16 bits b. Continuous transfer with CPOL=1 and CPHA=0 Fig 16.
  • Page 102 UM10429 NXP Semiconductors Chapter 11: LPC1102 SPI0 with SSP 11.7.2.5 SPI format with CPOL = 1,CPHA = 1 The transfer signal sequence for SPI format with CPOL = 1, CPHA = 1 is shown in Figure 17, which covers both single and continuous transfers.
  • Page 103 UM10429 NXP Semiconductors Chapter 11: LPC1102 SPI0 with SSP 8-bit control 4 to 16 bits of output data Fig 18. Microwire frame format (single transfer) 8-bit control 4 to 16 bits 4 to 16 bits of output data of output data Fig 19.
  • Page 104 UM10429 NXP Semiconductors Chapter 11: LPC1102 SPI0 with SSP turn latches each bit on the rising edge of SK. At the end of the frame, for single transfers, the CS signal is pulled HIGH one clock period after the last bit has been latched in the receive serial shifter, that causes the data to be transferred to the receive FIFO.

  • Page 105: Chapter 12: Lpc1102 16-Bit Counter/Timers (Ct16B0/1)

    UM10429 Chapter 12: LPC1102 16-bit counter/timers (CT16B0/1) Rev. 1 — 20 October 2010 User manual 12.1 How to read this chapter The 16-bit timer blocks do not contain capture inputs and operate in timer mode only. 12.2 Basic configuration The CT16B0/1 are configured using the following registers: 1.

  • Page 106: Pin Description

    UM10429 NXP Semiconductors Chapter 12: LPC1102 16-bit counter/timers (CT16B0/1) In PWM mode, three match registers on CT16B0 can be used to provide a single-edge controlled PWM output on the match output pins. It is recommended to use the match registers that are not pinned out to control the PWM cycle length.

  • Page 107: Tmr16B1Ir)

    UM10429 NXP Semiconductors Chapter 12: LPC1102 16-bit counter/timers (CT16B0/1) Table 101. Register overview: 16-bit counter/timer 0 CT16B0 (base address 0x4000 C000) …continued Name Access Address Description Reset offset value TMR16B0MR3 0x024 Match Register 3 (MR3). See MR0 description. 0x028 Reserved...

  • Page 108: Timer Control Register (Tmr16B0Tcr And Tmr16B1Tcr)

    UM10429 NXP Semiconductors Chapter 12: LPC1102 16-bit counter/timers (CT16B0/1) Table 102. Register overview: 16-bit counter/timer 1 CT16B1 (base address 0x4001 0000) …continued Name Access Address Description Reset offset value 0x040 - Reserved 0x06C 0x070 Reserved TMR16B1PWMC R/W 0x074 PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT16B1_MAT[1:0].

  • Page 109: Timer Counter

    UM10429 NXP Semiconductors Chapter 12: LPC1102 16-bit counter/timers (CT16B0/1) Table 105. Timer counter registers (TMR16B0TC, address 0x4000 C008 and TMR16B1TC 0x4001 0008) bit description Symbol Description Reset value 15:0 Timer counter value. 31:16 Reserved. 12.7.4 Prescale Register The 16-bit Prescale Register specifies the maximum value for the Prescale Counter.
  • Page 110 UM10429 NXP Semiconductors Chapter 12: LPC1102 16-bit counter/timers (CT16B0/1) Table 108. Match Control Register (TMR16B0MCR - address 0x4000 C014 and TMR16B1MCR - address 0x4001 0014) bit description …continued Symbol Value Description Reset value MR0R Reset on MR0: the TC will be reset if MR0 matches it.

  • Page 111: External Match Register

    UM10429 NXP Semiconductors Chapter 12: LPC1102 16-bit counter/timers (CT16B0/1) Table 108. Match Control Register (TMR16B0MCR - address 0x4000 C014 and TMR16B1MCR - address 0x4001 0014) bit description …continued Symbol Value Description Reset value MR3S Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.
  • Page 112 UM10429 NXP Semiconductors Chapter 12: LPC1102 16-bit counter/timers (CT16B0/1) Table 110. External Match Register (TMR16B0EMR - address 0x4000 C03C and TMR16B1EMR - address 0x4001 003C) bit description Symbol Value Description Reset value External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin.

  • Page 113: Pwm Control Register (Tmr16B0Pwmc And Tmr16B1Pwmc)

    UM10429 NXP Semiconductors Chapter 12: LPC1102 16-bit counter/timers (CT16B0/1) Table 110. External Match Register (TMR16B0EMR - address 0x4000 C03C and TMR16B1EMR - address 0x4001 003C) bit description Symbol Value Description Reset value 11:10 EMC3 External Match Control 3. Determines the functionality of External Match 3.

  • Page 114: Rules For Single Edge Controlled Pwm Outputs

    UM10429 NXP Semiconductors Chapter 12: LPC1102 16-bit counter/timers (CT16B0/1) Table 112. PWM Control Register (TMR16B0PWMC - address 0x4000 C074 and TMR16B1PWMC- address 0x4001 0074) bit description Symbol Description Reset value PWM enable When one, PWM mode is enabled for match channel 2 or pin CT16B0_MAT2.

  • Page 115: Example Timer Operation

    UM10429 NXP Semiconductors Chapter 12: LPC1102 16-bit counter/timers (CT16B0/1) PWM2/MAT2 MR2 = 100 PWM1/MAT1 MR1 = 41 PWM0/MAT0 MR0 = 65 (counter is reset) Fig 21. Sample PWM waveforms with a PWM cycle length of 100 (selected by MR3) and MAT3:0 enabled as PWM outputs by the PWCON register.
  • Page 116 UM10429 NXP Semiconductors Chapter 12: LPC1102 16-bit counter/timers (CT16B0/1) 12.9 Architecture The block diagram for counter/timer0 and counter/timer1 is shown in Figure MATCH REGISTER 0 MATCH REGISTER 1 MATCH REGISTER 2 MATCH REGISTER 3 MATCH CONTROL REGISTER EXTERNAL MATCH REGISTER...
  • Page 117 UM10429 Chapter 13: LPC11102 32-bit counter/timers (CT32B0/1) Rev. 1 — 20 October 2010 User manual 13.1 How to read this chapter The 32-bit timer 0 does not contain capture inputs and operates in timer mode only. The 32-bit timer 1 contains one capture channel corresponding to one capture input. 13.2 Basic configuration The CT32B0/1 are configured using the following registers: 1.
  • Page 118 UM10429 NXP Semiconductors Chapter 13: LPC11102 32-bit counter/timers (CT32B0/1) 13.5 Description Each Counter/timer is designed to count cycles of the peripheral clock (PCLK) or an externally supplied clock and can optionally generate interrupts or perform other actions at specified timer values based on four match registers. Each counter/timer also includes one capture input to trap the timer value when an input signal transitions, optionally generating an interrupt.
  • Page 119 UM10429 NXP Semiconductors Chapter 13: LPC11102 32-bit counter/timers (CT32B0/1) Table 114. Register overview: 32-bit counter/timer 0 CT32B0 (base address 0x4001 4000) Name Access Address Description Reset offset value TMR32B0IR 0x000 Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending.
  • Page 120 UM10429 NXP Semiconductors Chapter 13: LPC11102 32-bit counter/timers (CT32B0/1) Table 115. Register overview: 32-bit counter/timer 1 CT32B1 (base address 0x4001 8000) …continued Name Access Address Description Reset offset value TMR32B1PC 0x010 Prescale Counter (PC). The 32-bit PC is a counter which is incremented to the value stored in PR.

  • Page 121: Prescale Register

    UM10429 NXP Semiconductors Chapter 13: LPC11102 32-bit counter/timers (CT32B0/1) 13.7.2 Timer Control Register (TMR32B0TCR and TMR32B1TCR) The Timer Control Register (TCR) is used to control the operation of the counter/timer. Table 117. Timer Control Register (TMR32B0TCR - address 0x4001 4004 and TMR32B1TCR -...

  • Page 122: 0X4001 8010)

    UM10429 NXP Semiconductors Chapter 13: LPC11102 32-bit counter/timers (CT32B0/1) the Timer Counter is incremented, and the Prescale Counter is reset on the next PCLK. This causes the TC to increment on every PCLK when PR = 0, every 2 PCLKs when PR = 1, etc.

  • Page 123: Match Registers (Tmr32B0Mr0/1/2/3 And Tmr32B1Mr0/1/2/3)

    UM10429 NXP Semiconductors Chapter 13: LPC11102 32-bit counter/timers (CT32B0/1) Table 121. Match Control Register (TMR32B0MCR - address 0x4001 4014 and TMR32B1MCR - address 0x4001 8014) bit description Symbol Value Description Reset value MR2S Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.

  • Page 124: Capture Register (Tmr32B1Cr0 - Address 0X4001 802C)

    UM10429 NXP Semiconductors Chapter 13: LPC11102 32-bit counter/timers (CT32B0/1) Table 123. Capture Control Register (TMR32B1CCR - address 0x4001 8028) bit description Symbol Value Description Reset value CAP0FE Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC.
  • Page 125 UM10429 NXP Semiconductors Chapter 13: LPC11102 32-bit counter/timers (CT32B0/1) Table 125. External Match Register (TMR32B0EMR - address 0x4001 403C and TMR32B1EMR - address0x4001 803C) bit description Symbol Value Description Reset value External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin.

  • Page 126: Count Control Register (Tmr32B0Ctcr And Tmr32B1Tcr)

    UM10429 NXP Semiconductors Chapter 13: LPC11102 32-bit counter/timers (CT32B0/1) Table 125. External Match Register (TMR32B0EMR - address 0x4001 403C and TMR32B1EMR - address0x4001 803C) bit description Symbol Value Description Reset value 11:10 EMC3 External Match Control 3. Determines the functionality of External Match 3.

  • Page 127: Pwm Control Register (Tmr32B0Pwmc And Tmr32B1Pwmc)

    UM10429 NXP Semiconductors Chapter 13: LPC11102 32-bit counter/timers (CT32B0/1) Table 127. Count Control Register (TMR32B0CTCR - address 0x4001 4070 and TMR32B1TCR - address 0x4001 8070) bit description Symbol Value Description Reset value Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer’s Prescale Counter (PC), or clear...

  • Page 128: Rules For Single Edge Controlled Pwm Outputs

    UM10429 NXP Semiconductors Chapter 13: LPC11102 32-bit counter/timers (CT32B0/1) Table 128. PWM Control Register (TMR32B0PWMC - 0x4001 4074 and TMR32B1PWMC - 0x4001 8074) bit description Symbol Description Reset value PWM enable When one, PWM mode is enabled for CT32Bn_MAT2. When zero, CT32Bn_MAT2 is controlled by EM2.
  • Page 129 UM10429 NXP Semiconductors Chapter 13: LPC11102 32-bit counter/timers (CT32B0/1) 13.8 Example timer operation Figure 26 shows a timer configured to reset the count and generate an interrupt on match. The prescaler is set to 2 and the match register set to 6. At the end of the timer cycle where the match occurs, the timer count is reset.
  • Page 130 UM10429 NXP Semiconductors Chapter 13: LPC11102 32-bit counter/timers (CT32B0/1) MATCH REGISTER 0 MATCH REGISTER 1 MATCH REGISTER 2 MATCH REGISTER 3 MATCH CONTROL REGISTER EXTERNAL MATCH REGISTER INTERRUPT REGISTER CONTROL MAT[3:0] INTERRUPT CAP0 STOP ON MATCH RESET ON MATCH LOAD[3:0]...

  • Page 131: Chapter 14: Lpc1102 Watchdog Timer (Wdt)

    Rev. 1 — 20 October 2010 User manual 14.1 How to read this chapter The WDT block is implemented on the LPC1102. 14.2 Basic configuration The WDT is configured using the following registers: 1. Pins: The WDT uses no external pins.

  • Page 132: Description

    UM10429 NXP Semiconductors Chapter 14: LPC1102 WatchDog Timer (WDT) 14.5 Description The Watchdog consists of a divide by 4 fixed pre-scaler and a 24-bit counter. The clock is fed to the timer via a pre-scaler. The timer decrements when clocked. The minimum value from which the counter decrements is 0xFF.
  • Page 133 UM10429 NXP Semiconductors Chapter 14: LPC1102 WatchDog Timer (WDT) Table 129. Register overview: Watchdog timer (base address 0x4000 4000) Name Access Address Description Reset offset Value WDMOD 0x000 Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer.
  • Page 134 UM10429 NXP Semiconductors Chapter 14: LPC1102 WatchDog Timer (WDT) Table 131. Watchdog operating modes selection WDEN WDRESET Mode of Operation X (0 or 1) Debug/Operate without the Watchdog running. Watchdog interrupt mode: debug with the Watchdog interrupt but no WDRESET enabled.
  • Page 135 UM10429 NXP Semiconductors Chapter 14: LPC1102 WatchDog Timer (WDT) 14.7.4 Watchdog Timer Value register (WDTV - 0x4000 400C) The WDTV register is used to read the current value of Watchdog timer. When reading the value of the 24-bit timer, the lock and synchronization procedure takes up to 6 WDCLK cycles plus 6 PCLK cycles, so the value of WDTV is older than the actual value of the timer when it's being read by the CPU.

  • Page 136: Chapter 15: Lpc1102 System Tick Timer

    UM10429 Chapter 15: LPC1102 System tick timer Rev. 1 — 20 October 2010 User manual 15.1 How to read this chapter The system tick timer (SysTick timer) is part of the ARM Cortex-M0 core. 15.2 Basic configuration The system tick timer is configured using the following registers: 1.
  • Page 137 UM10429 NXP Semiconductors Chapter 15: LPC1102 System tick timer 15.5 Operation The SysTick timer is a 24-bit timer that counts down to zero and generates an interrupt. The intent is to provide a fixed 10 millisecond time interval between interrupts. The SysTick timer is clocked from the CPU clock.
  • Page 138 UM10429 NXP Semiconductors Chapter 15: LPC1102 System tick timer 15.6.1 System Timer Control and status register The SYST_CSR register contains control information for the SysTick timer and provides a status flag. This register is part of the ARM Cortex-M0 core system timer register block.
  • Page 139 3. Program the SYST_SCR register with the value 0x7 which enables the SysTick timer and the SysTick timer interrupt. The following example illustrates selecting the SysTick timer reload value to obtain a 10 ms time interval with the LPC1102 system clock set to 50 MHz. Example (system clock = 50 MHz) ⁄...

  • Page 140: How To Read This Chapter

    Rev. 1 — 20 October 2010 User manual 16.1 How to read this chapter The ADC is uses channels 0 to 4 on the LPC1102. Channels 5 to 6 are not pinned out. 16.2 Basic configuration The ADC is configured using the following registers: 1.

  • Page 141: Adc Clocking

    UM10429 NXP Semiconductors Chapter 16: LPC1102 Analog-to-Digital Converter (ADC) 16.5 ADC clocking Basic clocking for the A/D converters is determined by the APB clock (PCLK). A programmable divider is included in the A/D converter to scale this clock to the 4.5 MHz (max) clock needed by the successive approximation process.
  • Page 142 UM10429 NXP Semiconductors Chapter 16: LPC1102 Analog-to-Digital Converter (ADC) Table 141. A/D Control Register (AD0CR - address 0x4001 C000) bit description Symbol Value Description Reset Value Selects which of the AD4:0 pins is (are) to be sampled and converted. Bit 0 selects Pin 0x00 AD0, bit 1 selects pin AD1,..., and bit 4 selects pin AD4.

  • Page 143: A/D Global Data Register

    UM10429 NXP Semiconductors Chapter 16: LPC1102 Analog-to-Digital Converter (ADC) Table 141. A/D Control Register (AD0CR - address 0x4001 C000) bit description Symbol Value Description Reset Value 26:24 START When the BURST bit is 0, these bits control whether and when an A/D conversion is started.
  • Page 144 UM10429 NXP Semiconductors Chapter 16: LPC1102 Analog-to-Digital Converter (ADC) Table 142. A/D Global Data Register (AD0GDR - address 0x4001 C004) bit description Symbol Description Reset Value 29:27 Unused These bits always read as zeroes. They could be used for expansion of the CHN field in future compatible A/D converters that can convert more channels.
  • Page 145 UM10429 NXP Semiconductors Chapter 16: LPC1102 Analog-to-Digital Converter (ADC) Table 144. A/D Interrupt Enable Register (AD0INTEN - address 0x4001 C00C) bit description Symbol Description Reset Value ADINTEN 4:0 These bits allow control over which A/D channels generate 0x00 interrupts for conversion completion. When bit 0 is one, completion...
  • Page 146 UM10429 NXP Semiconductors Chapter 16: LPC1102 Analog-to-Digital Converter (ADC) 16.7.2 Interrupts An interrupt is requested to the interrupt controller when the ADINT bit in the ADSTAT register is 1. The ADINT bit is one when any of the DONE bits of A/D channels that are enabled for interrupts (via the ADINTEN register) are one.

  • Page 147: Chapter 17: Lpc1102 Flash Memory Programming Firmware

    The loader can execute the ISP command handler or the user application code. However, in order to enter ISP mode, the user code must provide for an ISP entry mechanism because the LPC1102 does not have an ISP entry pin. Unprogrammed parts boot in ISP mode by default.

  • Page 148: Criterion For Valid User Code

    UM10429 NXP Semiconductors Chapter 17: LPC1102 Flash memory programming firmware described later in this chapter. The interrupt vectors residing in the boot block of the on-chip flash memory also become active after reset, i.e., the bottom 512 bytes of the boot block are also visible in the memory region starting from the address 0x0000 0000.

  • Page 149: Boot Process Flowchart

    UM10429 NXP Semiconductors Chapter 17: LPC1102 Flash memory programming firmware 17.3.4 Boot process flowchart RESET INITIALIZE CRP1/2/3 ENABLED? ENABLE DEBUG WATCHDOG FLAG SET? USER CODE VALID? CRP3 ENABLED? EXECUTE INTERNAL USER CODE USER CODE boot from VALID? UART RUN AUTO-BAUD...

  • Page 150: Sector Numbers

    0x0000 7000 - 0x0000 7FFF 17.3.6 Flash content protection mechanism The LPC1102 is equipped with the Error Correction Code (ECC) capable Flash memory. The purpose of an error correction module is twofold. Firstly, it decodes data words read from the memory into output data words. Secondly, it encodes data words to be written to the memory.
  • Page 151 Important: any CRP change becomes effective only after the device has gone through a power cycle. Remark: The LPC1102 does not provide an ISP entry pin to be monitored at reset. For all three CRP levels, the user’s application code must provide a flash update mechanism which reinvokes ISP by defining a user-selected PIO pin for ISP entry.

  • Page 152: Uart Communication Protocol

    UM10429 NXP Semiconductors Chapter 17: LPC1102 Flash memory programming firmware Table 150. ISP commands allowed for different CRP levels ISP command CRP1 CRP2 CRP3 Unlock Set Baud Rate Echo Write to RAM yes; above 0x1000 0300 only Read Memory Prepare sector(s) for...

  • Page 153: Uart Isp Commands

    UM10429 NXP Semiconductors Chapter 17: LPC1102 Flash memory programming firmware The receiver should compare it with the check-sum of the received bytes. If the check-sum matches then the receiver should respond with "OK<CR><LF>" to continue further transmission. If the check-sum does not match the receiver should respond with "RESEND<CR><LF>".
  • Page 154 UM10429 NXP Semiconductors Chapter 17: LPC1102 Flash memory programming firmware CMD_SUCCESS is sent by ISP command handler only when received ISP command has been completely executed and the new ISP command can be given by the host. Exceptions from this rule are "Set Baud Rate", "Write to RAM", "Read Memory", and "Go"...

  • Page 155: Echo (Uart Isp)

    UM10429 NXP Semiconductors Chapter 17: LPC1102 Flash memory programming firmware Table 153. UART ISP Set Baud Rate command Command Return Code CMD_SUCCESS | INVALID_BAUD_RATE | INVALID_STOP_BIT | PARAM_ERROR Description This command is used to change the baud rate. The new baud rate is effective after the command handler sends the CMD_SUCCESS return code.

  • Page 156: Prepare Sector(S) For Write Operation (Uart Isp)

    UM10429 NXP Semiconductors Chapter 17: LPC1102 Flash memory programming firmware Table 155. UART ISP Write to RAM command Command Return Code CMD_SUCCESS | ADDR_ERROR (Address not on word boundary) | ADDR_NOT_MAPPED | COUNT_ERROR (Byte count is not multiple of 4) |...

  • Page 157: Copy Ram To Flash (Uart Isp)

    UM10429 NXP Semiconductors Chapter 17: LPC1102 Flash memory programming firmware Table 157. UART ISP Prepare sector(s) for write operation command Command Input Start Sector Number End Sector Number: Should be greater than or equal to start sector number. Return Code...
  • Page 158 UM10429 NXP Semiconductors Chapter 17: LPC1102 Flash memory programming firmware Table 158. UART ISP Copy command Command Input Flash Address(DST): Destination flash address where data bytes are to be written. The destination address should be a 256 byte boundary. RAM Address(SRC): Source RAM address from where data bytes are to be read.

  • Page 159: Erase Sector(S) (Uart Isp)

    UM10429 NXP Semiconductors Chapter 17: LPC1102 Flash memory programming firmware 17.5.9 Erase sector(s) <start sector number> <end sector number> (UART ISP) Table 160. UART ISP Erase sector command Command Input Start Sector Number End Sector Number: Should be greater than or equal to start sector number.

  • Page 160: Return Code Cmd_Success

    UM10429 NXP Semiconductors Chapter 17: LPC1102 Flash memory programming firmware 17.5.12 Read Boot code version number (UART ISP) Table 164. UART ISP Read Boot Code version number command Command Input None Return Code CMD_SUCCESS followed by 2 bytes of boot code version number in ASCII format.

  • Page 161: Table Of Contents

    UM10429 NXP Semiconductors Chapter 17: LPC1102 Flash memory programming firmware 17.5.15 UART ISP Return Codes Table 167. UART ISP Return Codes Summary Return Mnemonic Description Code CMD_SUCCESS Command is executed successfully. Sent by ISP handler only when command given by the host has been completely and successfully executed.
  • Page 162 UM10429 NXP Semiconductors Chapter 17: LPC1102 Flash memory programming firmware The maximum number of results is 4, returned by the "ReadUID" command. The command handler sends the status code INVALID_COMMAND when an undefined command is received. The IAP routine resides at 0x1FFF 1FF0 location and it is thumb code.
  • Page 163 UM10429 NXP Semiconductors Chapter 17: LPC1102 Flash memory programming firmware Table 168. IAP Command Summary IAP Command Command Code Described in Prepare sector(s) for write operation Table 169 Copy RAM to flash Table 170 Erase sector(s) Table 171 Blank check sector(s)

  • Page 164: Src_Addr_Error (Address Not On Word Boundary) | Dst_Addr_Error (Address Not On Correct Boundary) | Src_Addr_Not_Mapped

    UM10429 NXP Semiconductors Chapter 17: LPC1102 Flash memory programming firmware Table 169. IAP Prepare sector(s) for write operation command Command Prepare sector(s) for write operation Return Code CMD_SUCCESS | BUSY | INVALID_SECTOR Result None Description This command must be executed before executing "Copy RAM to flash" or "Erase Sector(s)"...

  • Page 165: Sector_Not_Blank

    UM10429 NXP Semiconductors Chapter 17: LPC1102 Flash memory programming firmware 17.6.3 Erase Sector(s) (IAP) Table 171. IAP Erase Sector(s) command Command Erase Sector(s) Input Command code: 5210 Param0: Start Sector Number Param1: End Sector Number (should be greater than or equal to start sector number).

  • Page 166: Compare_Error

    UM10429 NXP Semiconductors Chapter 17: LPC1102 Flash memory programming firmware 17.6.6 Read Boot code version number (IAP) Table 174. IAP Read Boot Code version number command Command Read boot code version number Input Command code: 5510 Parameters: None Return Code...

  • Page 167: Readuid (Iap)

    UM10429 NXP Semiconductors Chapter 17: LPC1102 Flash memory programming firmware 17.6.9 ReadUID (IAP) Table 177. IAP ReadUID command Command Compare Input Command code: 5810 Return Code CMD_SUCCESS Result Result0: The first 32-bit word (at the lowest address). Result1: The second 32-bit word.
  • Page 168 Depending on the system clock frequency, access to the flash memory can be configured with various access times by writing to the FLASHCFG register at address 0x4003 C010. Remark: Improper setting of this register may result in incorrect operation of the LPC1102 flash memory.
  • Page 169 UM10429 NXP Semiconductors Chapter 17: LPC1102 Flash memory programming firmware 17.9.1 Register description for signature generation Table 181. Register overview: FMC (base address 0x4003 C000) Name Access Address Description Reset Reference offset value FMSSTART 0x020 Signature start address register Table 182...
  • Page 170 UM10429 NXP Semiconductors Chapter 17: LPC1102 Flash memory programming firmware Table 183. Flash Module Signature Stop register (FMSSTOP - 0x4003 C024) bit description Symbol Value Description Reset value SIG_START Start control bit for signature generation. Signature generation is stopped Initiate signature generation...
  • Page 171 UM10429 NXP Semiconductors Chapter 17: LPC1102 Flash memory programming firmware Table 188. Flash module Status register (FMSTAT - 0x4003 CFE0) bit description Symbol Description Reset value 31:2 Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
  • Page 172 UM10429 NXP Semiconductors Chapter 17: LPC1102 Flash memory programming firmware After signature generation, a 128-bit signature can be read from the FMSW0 to FMSW3 registers. The 128-bit signature reflects the corrected data read from the flash. The 128-bit signature reflects flash parity bits and check bit values.

  • Page 173: Chapter 18: Lpc1102 Serial Wire Debug (Swd)

    The ARM Cortex-M0 is configured to support up to four breakpoints and two watchpoints. 18.4 Description Debugging with the LPC1102 uses the Serial Wire Debug mode. 18.5 Pin description The tables below indicate the various pin functions related to debug. Some of these functions share pins with other functions which therefore may not be used at the same time.
  • Page 174 Important: The user should be aware of certain limitations during debugging. The most important is that, due to limitations of the ARM Cortex-M0 integration, the LPC1102 cannot wake up in the usual manner from Deep-sleep mode. It is recommended not to use this mode during debug.

  • Page 175: Chapter 19: Appendix Lpc1102 Arm Cortex-M0 Reference

    User manual 19.1 Introduction The following material is using the ARM Cortex-M0 User Guide. Minor changes have been made regarding the specific implementation of the Cortex-M0 for the LPC1102. The ARM Cortex-M0 documentation is also available in Ref. 1 Ref.

  • Page 176: System-Level Interface

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference The Cortex-M0 processor closely integrates a configurable Nested Vectored Interrupt Controller (NVIC), to deliver industry-leading interrupt performance. The NVIC: • includes a non-maskable interrupt (NMI). The NMI is not implemented on the LPC1102.

  • Page 177: Processor

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference System Control Block — The System Control Block (SCB) is the programmers model interface to the processor. It provides system implementation information and system control, including configuration, control, and reporting of system exceptions.

  • Page 178: General-Purpose Registers

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference Low registers General purpose registers High registers SP (R13) Stack Pointer LR (R14) Link Register PC (R15) Program Counter Program Status Register Special registers PRIMASK Interrupt mask register CONTROL Control Register Fig 36.

  • Page 179: Link Register

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference On reset, the processor loads the MSP with the value from address 0x00000000. 19.3.1.3.3 Link Register The Link Register (LR) is register R14. It stores the return information for subroutines, function calls, and exceptions.
  • Page 180 UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference See the instruction descriptions Section 19–19.4.7.6 Section 19–19.4.7.7 for more information about how to access the program status registers. Application Program Status Register: The APSR contains the current state of the condition flags, from previous instruction executions.

  • Page 181: Exception Mask Register

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference Table 196. EPSR bit assignments Bits Name Function [31:25] Reserved [24] Thumb state bit [23:0] Reserved Attempts by application software to read the EPSR directly using the MRS instruction always return zero. Attempts to write the EPSR using the MSR instruction are ignored. Fault handlers can examine the EPSR value in the stacked PSR to determine the cause of the fault.

  • Page 182: Exceptions And Interrupts

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference Table 198. CONTROL register bit assignments Bits Name Function [31:2] Reserved Active stack Defines the current stack: pointer 0 = MSP is the current stack pointer 1 = PSP is the current stack pointer.

  • Page 183: Memory Model

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference For a Cortex-M0 microcontroller system, CMSIS defines: • a common way to: – access peripheral registers – define exception vectors • the names of: – the registers of the core peripherals –...

  • Page 184: Memory Regions, Types And Attributes

    0.5GB 0x00000000 Figure 2 for the LPC1102 specific implementation of the memory map. SRAM and code locations are different on the LPC1102. Fig 38. Generic ARM Cortex-M0 memory map The processor reserves regions of the Private peripheral bus (PPB) address range for...

  • Page 185: Memory System Ordering Of Memory Accesses

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference Strongly-ordered — The processor preserves transaction order relative to all other transactions. The different ordering requirements for Device and Strongly-ordered memory mean that the memory system can buffer a write to Device memory, but must not buffer a write to Strongly-ordered memory.

  • Page 186: Software Ordering Of Memory Accesses

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference Table 199. Memory access behavior Address Memory Memory Description range region type Code Normal Executable region for program 0x00000000- code. You can also put data here. 0x1FFFFFFF SRAM Normal Executable region for data. You 0x20000000- can also put code here.

  • Page 187: Exception Model

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference Vector table — If the program changes an entry in the vector table, and then enables the corresponding exception, use a DMB instruction between the operations. This ensures that if the exception is taken immediately after being enabled the processor uses the new exception vector.

  • Page 188: Exception Types

    19.3.3.2 Exception types The exception types are: Remark: The NMI is not implemented on the LPC1102. Reset — Reset is invoked on power up or a warm reset. The exception model treats reset as a special form of exception. When reset is asserted, the operation of the processor stops, potentially at any point in an instruction.

  • Page 189: Exception Handlers

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference Table 200. Properties of different exception types Exception Exception Priority Vector number number type address 12-13 Reserved PendSV Configurable 0x00000038 SysTick Configurable 0x0000003C 16 and above 0 and above Interrupt (IRQ)

  • Page 190: Exception Priorities

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference Exception number IRQ number Vector Offset IRQ31 0xBC IRQ2 0x48 IRQ1 0x44 IRQ0 0x40 SysTick 0x3C PendSV 0x38 Reserved SVCall 0x2C Reserved 0x10 HardFault 0x0C 0x08 Reset 0x04 Initial SP value 0x00 Fig 41.

  • Page 191: Exception Entry And Return

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference Assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed before IRQ[0].

  • Page 192: Exception Return

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference Sufficient priority means the exception has greater priority than any limit set by the mask register, see Section 19–19.3.1.3.6. An exception with less priority than this is pending but is not handled by the processor.

  • Page 193: Fault Handling

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference not a normal branch operation and, instead, that the exception is complete. Therefore, it starts the exception return sequence. Bits[3:0] of the EXC_RETURN value indicate the required return stack and processor mode, as Table 19–201...

  • Page 194: Power Management

    19.3.5.1.2 Wait for event Remark: The WFE instruction is not implemented on the LPC1102. The Wait For Event instruction, WFE, causes entry to sleep mode conditional on the value of a one-bit event register. When the processor executes a WFE instruction, it checks the value of the event register: 0 —...

  • Page 195: Sleep-On-Exit

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference 19.3.5.1.3 Sleep-on-exit If the SLEEPONEXIT bit of the SCR is set to 1, when the processor completes the execution of an exception handler and returns to Thread mode it immediately enters sleep mode.
  • Page 196 UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference • angle brackets, <>, enclose alternative forms of the operand • braces, {}, enclose optional operands and mnemonic parts • the Operands column is not exhaustive. For more information on the instructions and operands, see the instruction descriptions.

  • Page 197: Intrinsic Functions

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference Table 202. Cortex-M0 instructions Mnemonic Operands Brief description Flags Reference No Operation Section 19–19.4.7.8 ORRS {Rd,} Rn, Rm Logical OR Section 19–19.4.5.2 reglist Pop registers from stack Section 19–19.4.4.6 PUSH...

  • Page 198: About The Instruction Descriptions

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference Table 203. CMSIS intrinsic functions to generate some Cortex-M0 instructions Instruction CMSIS intrinsic function uint32_t __REV(uint32_t int value) REV16 uint32_t __REV16(uint32_t int value) REVSH uint32_t __REVSH(uint32_t int value) void __SEV(void)

  • Page 199: Shift Operations

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference Remark: When you update the PC with a BX, BLX, or POP instruction, bit[0] of any address must be 1 for correct execution. This is because this bit indicates the destination instruction set, and the Cortex-M0 processor only supports Thumb instructions.

  • Page 200: Lsl

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference You can use the LSR operation to divide the value in the register Rm by 2 , if the value is regarded as an unsigned integer. When the instruction is LSRS, the carry flag is updated to the last bit shifted out, bit[n-1], of the register Rm.

  • Page 201: Ror

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference 19.4.3.3.4 ROR Rotate right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the right-hand 32-n bits of the result, and it moves the right-hand n bits of the register into the left-hand n bits of the result.

  • Page 202: Conditional Execution

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference 19.4.3.6 Conditional execution Most data processing instructions update the condition flags in the Application Program Status Register (APSR) according to the result of the operation, see Section . Some instructions update all flags, and some only update a subset. If a flag is not updated, the original value is preserved.

  • Page 203: Memory Access Instructions

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference Table 205 also shows the relationship between condition code suffixes and the N, Z, C, and V flags. Table 205. Condition code suffixes Suffix Flags Meaning Z = 1 Equal, last flag setting result was zero...

  • Page 204: Operation

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference where: Rd is the destination register. label is a PC-relative expression. See Section 19–19.4.3.5. 19.4.4.1.2 Operation ADR generates an address by adding an immediate value to the PC, and writes the result to the destination register.

  • Page 205: Restrictions

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference STR, STRB and STRH instructions store the word, least-significant byte or lower halfword contained in the single register specified by Rt in to memory. The memory address to load from or store to is the sum of the value in the register specified by either Rn or SP and the immediate value imm.

  • Page 206: Operation

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference 19.4.4.3.2 Operation LDR, LDRB, U, LDRSB and LDRSH load the register specified by Rt with either a word, zero extended byte, zero extended halfword, sign extended byte or sign extended halfword value from memory.

  • Page 207: Examples

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference 19.4.4.4.5 Examples R0, LookUpTable ; Load R0 with a word of data from an address ; labelled as LookUpTable. R3, [PC, #100] ; Load R3 with memory word at (PC + 100).

  • Page 208: Condition Flags

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference • the value in the register specified by Rn must be word aligned. See Section 19–19.4.3.4 for more information. • for STM, if Rn appears in reglist, then it must be the first register in the list.

  • Page 209: Examples

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference • The exception is LR for a PUSH and PC for a POP. 19.4.4.6.4 Condition flags These instructions do not change the flags. 19.4.4.6.5 Examples PUSH {R0,R4-R7} ; Push R0,R4,R5,R6,R7 onto the stack...

  • Page 210: Syntax

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference 19.4.5.1 ADC, ADD, RSB, SBC, and SUB Add with carry, Add, Reverse Subtract, Subtract with carry, and Subtract. 19.4.5.1.1 Syntax ADCS {Rd,} Rn, Rm ADD{S} {Rd,} Rn, <Rm|#imm> RSBS {Rd,} Rn, Rm, #0...
  • Page 211 UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference See also Section 19–19.4.4.1. 19.4.5.1.3 Restrictions Table 208 lists the legal combinations of register specifiers and immediate values that can be used with each instruction. Table 208. ADC, ADD, RSB, SBC and SUB operand restrictions...

  • Page 212: Restrictions

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference 19.4.5.2.1 Syntax ANDS {Rd,} Rn, Rm ORRS {Rd,} Rn, Rm EORS {Rd,} Rn, Rm BICS {Rd,} Rn, Rm where: Rd is the destination register. Rn is the register holding the first operand and is the same as the destination register.

  • Page 213: Restrictions

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference LSRS {Rd,} Rm, Rs LSRS {Rd,} Rm, #imm RORS {Rd,} Rm, Rs where: Rd is the destination register. If Rd is omitted, it is assumed to take the same value as Rm is the register holding the value to be shifted.

  • Page 214: Examples

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference 19.4.5.4.1 Syntax CMN Rn, Rm CMP Rn, #imm CMP Rn, Rm where: Rn is the register holding the first operand. Rm is the register to compare with. imm is the immediate value to compare with.

  • Page 215: Muls

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference MVNS Rd, Rm where: S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see Section 19–19.4.3.6. Rd is the destination register.

  • Page 216: Operation

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference where: Rd is the destination register. Rn, Rm are registers holding the values to be multiplied. 19.4.5.6.2 Operation The MUL instruction multiplies the values in the registers specified by Rn and Rm, and places the least significant 32 bits of the result in Rd.

  • Page 217: Restrictions

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference REVSH — converts 16-bit signed big-endian data into 32-bit signed little-endian data or 16-bit signed little-endian data into 32-bit signed big-endian data. 19.4.5.7.3 Restrictions In these instructions, Rd, and Rn must only specify R0-R7.

  • Page 218: Examples

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference 19.4.5.8.5 Examples SXTH R4, R6 ; Obtain the lower halfword of the ; value in R6 and then sign extend to ; 32 bits and write the result to R4.

  • Page 219: Syntax

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference Table 209. Branch and control instructions Mnemonic Brief description Branch with Link Section 19–19.4.6.1 Branch indirect with Link Section 19–19.4.6.1 Branch indirect Section 19–19.4.6.1 19.4.6.1 B, BL, BX, and BLX Branch instructions.

  • Page 220: Condition Flags

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference • For BX and BLX, bit[0] of Rm must be 1 for correct execution. Bit[0] is used to update the EPSR T-bit and is discarded from the target address. Remark: Bcond is the only conditional instruction on the Cortex-M0 processor.

  • Page 221: Syntax

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference Table 211. Miscellaneous instructions Mnemonic Brief description Supervisor Call Section 19–19.4.7. Wait For Event Section 19–19.4.7. Wait For Interrupt Section 19–19.4.7. 19.4.7.1 BKPT Breakpoint. 19.4.7.1.1 Syntax BKPT #imm where: imm is an integer in the range 0-255.

  • Page 222: Restrictions

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference 19.4.7.2.3 Restrictions There are no restrictions. 19.4.7.2.4 Condition flags This instruction does not change the condition flags. 19.4.7.2.5 Examples CPSID i ; Disable all interrupts except NMI (set PRIMASK) CPSIE i ; Enable interrupts (clear PRIMASK) 19.4.7.3 DMB...

  • Page 223: Examples

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference 19.4.7.4.4 Condition flags This instruction does not change the flags. 19.4.7.4.5 Examples DSB ; Data Synchronisation Barrier 19.4.7.5 ISB Instruction Synchronization Barrier. 19.4.7.5.1 Syntax 19.4.7.5.2 Operation ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so that all instructions following the ISB are fetched from cache or memory again, after the ISB instruction has been completed.

  • Page 224: Examples

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference 19.4.7.6.4 Condition flags This instruction does not change the flags. 19.4.7.6.5 Examples MRS R0, PRIMASK ; Read PRIMASK value and write it to R0 19.4.7.7 MSR Move the contents of a general-purpose register into the specified special register.

  • Page 225: Examples

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference 19.4.7.8.4 Condition flags This instruction does not change the flags. 19.4.7.8.5 Examples NOP ; No operation 19.4.7.9 SEV Send Event. 19.4.7.9.1 Syntax 19.4.7.9.2 Operation SEV causes an event to be signaled to all processors within a multiprocessor system. It...

  • Page 226: Restrictions

    ; by locating it via the stacked PC) 19.4.7.11 WFE Wait For Event. Remark: The WFE instruction is not implemented on the LPC1102. 19.4.7.11.1 Syntax 19.4.7.11.2 Operation If the event register is 0, WFE suspends execution until one of the following events occurs: •...

  • Page 227: Operation

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference 19.4.7.12.2 Operation suspends execution until one of the following events occurs: • an exception • an interrupt becomes pending which would preempt if PRIMASK was clear • a Debug Entry request, regardless of whether debug is enabled.

  • Page 228: Accessing The Cortex-M0 Nvic Registers Using Cmsis

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference • A programmable priority level of 0-3 for each interrupt. A higher level corresponds to a lower priority, so level 0 is the highest interrupt priority. • Level and pulse detection of interrupt signals.

  • Page 229: Interrupt Clear-Enable Register

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference Table 215. ISER bit assignments Bits Name Function [31:0] SETENA Interrupt set-enable bits. Write: 0 = no effect 1 = enable interrupt. Read: 0 = interrupt disabled 1 = interrupt enabled.

  • Page 230: Interrupt Clear-Pending Register

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference • a disabled interrupt sets the state of that interrupt to pending. 19.5.2.5 Interrupt Clear-pending Register The ICPR removes the pending state from interrupts, and shows which interrupts are pending. See the register summary in Table 19–213...

  • Page 231: Level-Sensitive And Pulse Interrupts

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference Section 19–19.5.2.1 for more information about the access to the interrupt priority array, which provides the software view of the interrupt priorities. Find the IPR number and byte offset for interrupt M as follows: •...

  • Page 232: System Control Block

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference – For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this is pulsed the state of the interrupt changes to pending and active. In this case, when the processor returns from the ISR the state of the interrupt changes to pending, which might cause the processor to immediately re-enter the ISR.

  • Page 233: Cpuid Register

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference Table 221. Summary of the SCB registers Address Name Type Reset value Description CPUID Section 19.5.3.2 0xE000ED00 0x410CC200 ICSR Section 19–19.5.3.3 0xE000ED04 0x00000000 AIRCR Section 19–19.5.3.4 0xE000ED0C 0xFA050000 Section 19–19.5.3.5...
  • Page 234 UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference – whether any interrupts are pending. See the register summary in Table 19–221 for the ICSR attributes. The bit assignments are: Table 223. ICSR bit assignments Bits Name Type Function...

  • Page 235: Application Interrupt And Reset Control Register

    This is the same value as IPSR bits[5:0], see Table 19–195. The NMI is not implemented on the LPC1102. When you write to the ICSR, the effect is Unpredictable if you: • write 1 to the PENDSVSET bit and write 1 to the PENDSVCLR bit •...

  • Page 236: System Control Register

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference Table 224. AIRCR bit assignments Bits Name Type Function [31:16] Read: Reserved Register key: Write: VECTKEY Reads as Unknown On writes, write 0x05FA to VECTKEY, otherwise the write is ignored.

  • Page 237: Configuration And Control Register

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference 19.5.3.6 Configuration and Control Register The CCR is a read-only register and indicates some aspects of the behavior of the Cortex-M0 processor. See the register summary in Table 19–221 for the CCR attributes.

  • Page 238: Scb Usage Hints And Tips

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference Table 228. SHPR2 register bit assignments Bits Name Function [31:24] PRI_11 Priority of system handler 11, SVCall [23:0] Reserved 19.5.3.7.2 System Handler Priority Register 3 The bit assignments are: Table 229. SHPR3 register bit assignments...

  • Page 239: Systick Control And Status Register

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference 19.5.4.1 SysTick Control and Status Register The SYST_CSR enables the SysTick features. See the register summary in for its attributes. The bit assignments are: Table 231. SYST_CSR bit assignments Bits...

  • Page 240: Systick Calibration Value Register

    UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference Table 233. SYST_CVR bit assignments Bits Name Function [31:24] Reserved. [23:0] CURRENT Reads return the current value of the SysTick counter. A write of any value clears the field to 0, and also clears the SYST_CSR.COUNTFLAG bit to 0.
  • Page 241 UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference Table 235. Cortex M0- instruction summary Operation Description Assembler Cycles 8-bit immediate ADDS Rd, Rd, #<imm> With carry ADCS Rd, Rd, Rm Immediate to SP ADD SP, SP, #<imm> Form address from SP ADD Rd, SP, #<imm>...
  • Page 242 UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference Table 235. Cortex M0- instruction summary Operation Description Assembler Cycles Store Halfword, immediate offset STRH Rd, [Rn, #<imm>] Byte, immediate offset STRB Rd, [Rn, #<imm>] Word, register offset STR Rd, [Rn, Rm]...
  • Page 243 UM10429 NXP Semiconductors Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference Cycle count depends on core and debug configuration. Excludes time spend waiting for an interrupt or event. Executes as NOP. UM10429 All information provided in this document is subject to legal disclaimers.
  • Page 244 UM10429 Chapter 20: LPC1102 Supplementary information Rev. 1 — 20 October 2010 User manual 20.1 Abbreviations Table 236. Abbreviations Acronym Description Analog-to-Digital Converter Advanced High-performance Bus AMBA Advanced Microcontroller Bus Architecture Advanced Peripheral Bus BrownOut Detection GPIO General Purpose Input/Output...

  • Page 245: Disclaimers

    In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost NXP Semiconductors does not accept any liability related to any default,...

  • Page 246: Tables

    8150) bit description..... 22 Table 3. LPC1102 memory configuration ... . .7 Table 27. System tick timer calibration register Table 4.
  • Page 247 UM10429 NXP Semiconductors Chapter 20: LPC1102 Supplementary information Table 54. IOCON_R_PIO1_2 register (IOCON_R_PIO1_2, Table 76. UART Interrupt Enable Register (U0IER - address address 0x4004 4080) bit description ..58 0x4000 8004 when DLAB = 0) bit description 72 Table 55.
  • Page 248 ......121 Table 146. LPC1102 flash configuration ... . . 146 Table 120.
  • Page 249 UM10429 NXP Semiconductors Chapter 20: LPC1102 Supplementary information Table 161. UART ISP Blank check sector command . . .158 Table 204. insic functions to access the special Table 162. UART ISP Read Part Identification command158 registers ......197 Table 163.

  • Page 250: Figures

    Fig 2. LPC1102 memory map .....8 Fig 43. ASR #3 ....... 198 Fig 3.
  • Page 251 Deep-sleep mode configuration register..26 Chapter 4: LPC1102 PMU (Power Management Unit) Introduction ......39 4.2.1...
  • Page 252 Pin configuration..... . . 61 Chapter 9: LPC1102 General Purpose I/O (GPIO) How to read this chapter ....63 9.3.6...
  • Page 253 10.6 Architecture ......88 Chapter 11: LPC1102 SPI0 with SSP 11.1 How to read this chapter ....90 11.6.9...
  • Page 254 16.6.2 A/D Global Data Register ....143 Chapter 17: LPC1102 Flash memory programming firmware 17.1 How to read this chapter ....146 17.4.8...
  • Page 255 17.6.9 ReadUID (IAP) ..... . . 166 Chapter 18: LPC1102 Serial Wire Debug (SWD) 18.1 How to read this chapter ....172 18.5...
  • Page 256 NXP Semiconductors Chapter 20: LPC1102 Supplementary information 19.4.3.3.1 ASR ....... 198 19.4.5.2.5 Examples .
  • Page 257 UM10429 NXP Semiconductors Chapter 20: LPC1102 Supplementary information 19.4.7.2.1 Syntax......220 19.4.7.10.4 Condition flags .
  • Page 258 UM10429 NXP Semiconductors Chapter 20: LPC1102 Supplementary information 20.6 Contents ......250 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

Table of Contents