Digital I/O (Dio) - VersaLogic VL-EPM-31 Hardware Reference Manual

Digital I/O (DIO)

The 20-pin I/O connector (J21) incorporates 16 Digital I/O (DIO) lines that are independently
configurable as an input or output. DIO inputs can be set for normal or inverted level. DIO
outputs can be set to be normal HIGH or LOW state. There are pull-up resistors to +3.3 V on all
DIO lines. The pull-ups implemented — in the FPGA — can range in value from 20 kΩ to
40 kΩ. After reset, the DIO lines are set as inputs with pull-ups that will be detected as a HIGH
state to external equipment.
VersaLogic provides a set of application programming interface (API) calls for managing the
DIO lines. See the
Figure 19 shows the location and pin orientation of the digital I/O connector. Table 9 lists the pin
functions of the digital I/O connector and how the pins are routed to the VL-CBR-2004B
paddleboard. Refer to page 64 for information on the VL-CBR-2004B paddleboard.
EPM-31 Hardware Reference Manual
for information.
VersaAPI Support Page
Figure 19. Location and Pin Orientation of Digital I/O Connector
Multi-purpose I/O
40