Dio Guidelines; Voltage; Table 9: J21 I/O Connector Pinout - VersaLogic VL-EPM-31 Hardware Reference Manual

J21 Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
FPGA registers control the mode on pins 11-14 and 16-19. By default, they are DIOs. There are
FPGA register settings to select the timer signals in 4-signal mode (pins 16-19) and 8-signal
mode (11-15 and 16-19).

DIO Guidelines

Consider the following guidelines when using the DIO lines.
V
OLTAGE
The DIO lines are 3.3 V Low-voltage TTL (LVTTL) compatible DIOs capable of
sourcing/sinking up to 4 mA of current. Level shifting or current limiting is necessary when
connecting signals with different voltage rails.
CAUTION:
Do not connect the DIO signals to external +5 V devices; doing so will damage the FPGA and
void the warranty.
EPM-31 Hardware Reference Manual

Table 9: J21 I/O Connector Pinout

Signal
Digital I/O 1
Digital I/O 2
Digital I/O 3
Digital I/O 4
Ground
Digital I/O 5
Digital I/O 6
Digital I/O 7
Digital I/O 8
Ground
Digital I/O 9
(Optional Timer Channel 5 output)
Digital I/O 10
(Optional Timer Channel 5 output)
Digital I/O 11
(Optional Timer Channel 4 Gate input)
Digital I/O 12
(Optional Timer Channel 3 Gate input)
Ground
Digital I/O 13
(Optional Timer 3 output)
Digital I/O 14
(Optional Timer 3 input)
Digital I/O 15
(Optional Timer 4 output)
Digital I/O 16
(Optional Timer 4 input)
Ground
VL-CBR-2004B Terminal Block
Terminal Block
J1
J2
J3
J4
Multi-purpose I/O
Pin
5
4
3
1
2
5
4
2
1
3
5
3
2
1
4
4
3
2
1
5
41