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5.
3.8
.2.6
Standby
Mode
5.
3.8.
2.
6.1
When
the
instrument
is
switched
to
standby,
the
standby
latch
IC26b
(see
page
7-11)
is
clocked
to
the set
state.
The
base
of
Qll
is
pulled high
and IC31a-3
is
pulled low.
The
base
of
Q9
is
pulled
low
by IC31a,
the
base current
of
Q8
is
cut
off,
and
the
regulator
is
shut
down.
When
the voltage of the
+5V
supply
falls,
IC31b~6
goes
more
negative.
The
base
of
Q
7 is
taken towards
OV
by
IC31b
so that the base current
of
Q6
is
cut
off
and the -5.2V regulator
is
shut
down.
5.3.9
Internal
Frequency
Standard Block
5.
3.9.1
Functional Description
5. 3.
9.1.1
The
internal
frequency standard
consists of
a
5
MHz
oscillator
and
a
frequency
doubler.
A
block
diagram
of
the
internal
frequency standard
is
shown
in
Figure
5.11.
Figure
5.11 - Internal
Frequency
Standard Block
Diagram
5.
3.9. 1.2
The
10
MHz
signal
is
passed
to
the
measurement
block
via
a buffer
(IC2)
on
the
motherboard.
5. 3.
9.1.
3
Signals
from an
external frequency standard are applied to a
signal
conditioning
circuit
on
the
motherboard.
If
a 10
MHz
external frequency standard
is
used,
the
output
of
this
circuit
is
connected
directly to
the
measurement
circuitry.
5.3.9. 2
Circuit Description
5.3.9.2.1
Frequency Doubler
5. 3.
9.2.1.
1
The schematic
of the frequency
doubler,
used with
the internal
frequency
standard
is
given
on page
7-30.
The
5
MHz
input
is
applied
to the
balanced
amplifier
containing
Q1
and Q2.
The base
of
Q3
is
driven by the differential outputs
from
the
amplifier
via
D1 and D2
so that
the frequency here
is
10
MHz.
5.
3.9.
2.1. 2
The
10
MHz
signal
is
amplified
and
filtered in
the
two
stages containing
Q3
and Q5, and fed
to pin
3
via
buffer
Q6.
TO
MEASUREMENT
SLOCK
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