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5.
3.9. 2.1.3
The
output
signal
is
fed
back
via
C6
to
switch
Q4
on during
the positive
peaks
of the
signal.
The
gain
of
Q5
is
controlled
by the
potential across
C3 which
charges
via
R12
and
discharges
via
Q4,
If
the output
signal
increases, the
time
for
which
Q4
conducts
increases
so that the
mean
potential across
C3
decreases.
The
resulting
decrease
in
gain of
Q5
provides
automatic
level control.
5.3.9.2.2
Internal
Frequency
Standard Buffer
5.
3.9.
2. 2.1
The
buffer circuit
is
shown
on page
7-12.
The
10
MHz
input at
PL14
pin 4
is
shaped and buffered
in
IC2a, IC2b, and IC2c before being fed
to the
measurement
block
at
IC39-2.
The
inverting inputs of
IC2
are
connected
to the
bias
voltage
at
IC2-11.
5.
3.9
.2.
3
External
Frequency
Standard Buffer
5. 3. 9. 2. 3.1
The
buffer circuit
is
shown
on page
7-12,
The
signal
connected
to
the
EXT.
STD.
INPUT
socket on the rear panel
is
fed to
PL20
pin
4.
Protection against
excessive
signal
amplitude
is
provided by D6, D7, and R32.
5. 3.
9.2.
3.
2
The
buffer
comprises
IC14a, IC14b, and IC14c.
The
inverting
inputs
are
connected
to
the
bias
voltage at
IC14-U. The
final
stage has
feedback connected
via
Rll
to give a
Schmitt
trigger action.
5. 3.
9. 2.3.3
Link
LK1
is
fitted
between
pins
8
and
9
of
the
PUS
to connect the
differential
output
of
the
final
stage
to
the
measurement
block
at
IC39-3.
5.3.10
GPIB
Interface
5.3.10.1
Introduction
5.3.10.1.1
The
GPIB
interface
is
a
self-contained,
microprocessor-controlled
system.
It
handles the transfer
of
data
between
its
internal
memory
and
the
GPIB
without
involving the
main
instrument's microprocessor.
Data
transfer
is
made
one byte
at
a time,
each
transfer
being controlled by the
IEEE
-48
8
handshake
protocol.
Refer
to
the
schematic on
page
7-18.
5.3.10.1.2
The
microprocessor
RESET
signal
is
derived
from
the
standby and
IRQ
block.
The
clock
signal
is
derived
from
MCC1,
IC18,
shown
on page
7-11.
5.3.10.1.3
The
microprocessor
uses
a multiplexed
bus, the eight
low-order
bits
being
used
for
both address and data.
The
low-order address
bits
are put
onto
the bus
first
and
are latched
into
ICU
by the address
strobe.
The
bus
is
then free
for
data
use.
5.3.10.1.4
Data
transfer
between
the microprocessors
is
initiated
by an
interrupt
and
is
controlled by
a
3-wire
handshake
protocol.
The
transfer
is
in
the
form
of
a data
string,
the
number
of
bytes
in
the string
being
indicated
by the
first
byte.
5.3.10.2
Address
Setting
and
Recognition
5.3.10.2.1
The
microprocessor
reads
the
settings
of
the
address
switches
in
switchbank
SI, via
its
port
B
inputs,
approximately every
1
ms
and
writes the settings
into
an address
register
within the general purpose interface
adapter (GPIA) IC12.
5.3.10.2.2
When
the
interface address
is
set
on the bus by
the controller,
it
is
recognized by the
GPIA
by comparison with
the contents
of
the
internal
address
register.
5-21
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