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5.3.10.5
Serial Poll
5.3.10.5.1
The
status byte register
of
the
GPIA
is
normally
updated approximately
every
1
ms
by
the microprocessor.
When
the interface
is
addressed
to talk
following
the
receipt of the
serial
poll
enable (SPE)
message,
the
GPIA
puts the status byte
onto
the
bus
without
further action
by
the microprocessor.
5.3.10.5.2
When
the
serial poll
is
completed,
the controller
sends
the serial
poll
disable
(SPD) message, which
is
detected by IC26,
IC7, IC18,
and
IC19.
The
resulting
logic
1
at
IC17B-3
clocks
IC17B
to
the reset condition,
and
gives a logic
1
at
IC18-12.
5.3.10.6
Data
Transfer
Between
Microprocessors
5.3.10.6.1
Data
transfer
between
microprocessors
is
made
using the multiplexed data
bus on both devices. Connections
between
the
buses
is
made
by
means
of a
D-type
latch,
IC1
or IC2,
depending on
the direction of data transfer.
All
data
transfers are
initiated
by
the
sending
device.
The
first
byte indicates
the
number
of
bytes to be transferred.
5.3.10.6.2
For
data
transf
er
to
t
he
GPIB
microprocessor,
the
instrument's
microprocessor
sets
SKI
pin
22
(GPIB IRQ)
low.
This provides an interrupt request (IRQ)
to
the
GPIB
microprocessor
via
IC4.
As
part of
the
interrupt routine,
IC8
is
enabled
and
addressed
to give an enabling signal
for
IC5A. The
microprocessor reads
the
IRQ
flag via
IC5A
and data bus
line 7
to establish
that the
IRQ
is
from
the
instrument and
not
the
GPIA.
5.3.10.6.3
The GPIB
microprocessor prepares
to
receive data,
and
then enables and
addresses
IC8
to
give a
signal
which
clocks
IC16B
via
IC2G-6.
The
level set
on
line 0 of
the
data bus
is
transferred
to
IC16B-5, and forms
the
ready
for
data
(RFD)
signal to the
instrument's microprocessor.
5.3.10.6.4
The
instrument's
microprocessor
enables and addresses IC3 to give an
enabling
signal to
IC5B, reads the
RFD
signal,
puts
the
first
data byte on
the
bus,
and
readdresses IC3 to
give a
clock signal
which
latches
the
data
into
I
Cl.
It
then addresses
ICS
to
give a clock
signal
for
IC16A,
so that
the
logic level set
at
IC16A-12
is
transferred to
IC16A-19
to
form
the
data
valid
(DAV)
signal to
the
GPIB
microprocessor.
5.3.10.6.5
The GPIB
microprocessor addresses ICS
to
give
a
signal to
enable IC5A,
and reads
the
DAV
signal
via
data bus
line
6.
It
then cancels
its
RFD
signal,
addresses
IC8
to
give
an output enable
signal for
IC1
(via
IC20-8)
and reads
the data.
A
data
accepted
(DAC)
signal
is
sent via
IC2 and
the
RFD
signal
is
reset.
The
instrument's
microprocessor responds by
cancelling
its
DAV
signal
and entering the next data byte
into
I
Cl.
Data
transfer
continues
in this
manner
until
the
required
number
of
bytes have
been received.
5.3.10.6.6
Data
transfer
from
the
GPIB
microprocessor
to
the
instrument's
microprocessor
follows
a
similar
pattern.
The
IRQ
signal
is
passed
from
port
A
line 0 via
IC18 and
IC4.
The
IRQ
flag
is
read by
the instrument's
microprocessor during
its
interrupt routine, via
IC5B
(enabled
by an output from
IC3).
The
IRQ
signal
is
cancelled
by the instrument's microprocessor setting
data bus
line 0
to logic
0
and
then addressing
IC3
to
clock
IC17A. The
resulting logic 0 at
IC17B-9
disables
IC18-4.
5.3.10.6.7
During data
transfer
from
the
GPIB
interface to the
instrument,
the
RFD
signal
is
passed
via
IC16A
and ICS
A, the
DAV
signal via
IC16B and
IC5B, the
DAC
signal
via IC1,
and
the
data
via IC2.
5-23
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